JP5160787B2 - 過剰消去されたセルを復旧させるために、正のゲートストレスを使用したメモリデバイスおよびそのための方法 - Google Patents
過剰消去されたセルを復旧させるために、正のゲートストレスを使用したメモリデバイスおよびそのための方法 Download PDFInfo
- Publication number
- JP5160787B2 JP5160787B2 JP2006533936A JP2006533936A JP5160787B2 JP 5160787 B2 JP5160787 B2 JP 5160787B2 JP 2006533936 A JP2006533936 A JP 2006533936A JP 2006533936 A JP2006533936 A JP 2006533936A JP 5160787 B2 JP5160787 B2 JP 5160787B2
- Authority
- JP
- Japan
- Prior art keywords
- memory cells
- applying
- charge storage
- volts
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 35
- 210000004027 cell Anatomy 0.000 claims description 90
- 230000015654 memory Effects 0.000 claims description 70
- 210000000352 storage cell Anatomy 0.000 claims description 37
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 9
- 239000002784 hot electron Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005513 bias potential Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 description 24
- 230000000295 complement effect Effects 0.000 description 7
- 238000009826 distribution Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000012795 verification Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 240000005020 Acaciella glauca Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Description
米国特許第5,680,350号は、それぞれが導電層に電荷を蓄積しているフローティングゲートメモリデバイスへの正のゲートストレスの印加を開示している。
米国特許第5,400,286号も、それぞれが導電層に電荷を蓄積しているフローティングゲートメモリデバイスへの正のワード線(ゲート)ストレスの印加を開示している。
上記に鑑み、過剰消去を低減させ、スレッショルド電圧分布を低減するデバイス、ならびにマルチビットメモリセルのアレイの消去方法が所望されている。
Claims (8)
- 上部誘電体層(30)および下部誘電層(26)の間に配置され、第1電荷蓄積セル(36)および第2電荷蓄積セル(38)を少なくとも有する電荷トラップ誘電体層(28)と、前記上部誘電体層(30)の上部に配置されたゲート電極(32)とを有し、前記下部誘電層(26)は、前記第1電荷蓄積セル(36)の近くにある第1の導電領域(16)と前記第2電荷蓄積セル(38)の近くにある第2の導電領域(14)とを有する基板(12)に配置されている電荷トラップ型誘電体メモリセル(10)を複数有するフラッシュ電気的消去可能プログラマブル読出し専用メモリ(EEPROM)デバイスの消去方法であって、
(a)前記複数のメモリセル(10)に消去パルス(110)を印加するステップと、
(b)前記複数のメモリセル(10)に消去不足のメモリセルがあるかどうかを判定するために、前記複数のメモリセル(10)を消去検証する(120)ステップとを有し、
前記方法は更に、
(c)前記電荷トラップ誘電体層(28)内の陽電荷(40)の量を低減させるために前記複数のメモリセル(10)に正のゲートストレス(130)を印加するステップを有し、
ステップ(c)は、前記電荷トラップ誘電体層(28)内の前記電荷蓄積セル(36、38)の一方または両方の近くの前記電荷トラップ誘電体層(28)内の陽電荷(40)の量を低減させるために、前記複数のメモリセル(10)に正のゲートストレス(130)を印加するステップを有し、
前記複数のメモリセル(10)のうち、スレッショルド電圧が所定の最小値(VTMIN)を下回るメモリセルにソフトプログラミングパルスを印加するステップ(135)を更に有し、
ソフトプログラミングパルスを印加する前記ステップ(135)の前に、前記メモリセル(10)のいずれかのスレッショルド電圧が前記所定の最小値(VTMIN)を下回っているかどうかを判定するため、前記複数のメモリセル(10)のソフトプログラミングを検証するステップを更に有し、
前記複数のメモリセル(10)は、動作中に、ソースおよびドレインのいずれかが電子の供給源として機能し、ソースおよびドレインのいずれかが接地またはバイアス電位に接続されている、仮想接地デバイスとして構成され、
前記第1電荷蓄積セル(36)は、ホットエレクトロン注入を使用して、ドレインおよびゲート電極に電圧を印加することによりプログラミングされ、ソースに関しては、前記第1電荷蓄積セル(36)のチャネルホットエレクトロン注入のプログラミング用の電子の供給源として機能する、方法。 - 前記メモリセル(10)の全てが消去不足ではないと判定されるまでステップ(a)およびステップ(b)を繰り返すステップを更に有する、請求項1に記載の方法。
- 前記複数のメモリセル(10)を所定レベルにプリプログラミングする(100)ステップを更に有する、請求項1または2に記載の方法。
- 前記正のゲートストレスを印加するステップ(130)は、過剰消去されたメモリセル(10)を復旧させるのに有効である、請求項1〜3のいずれか1項に記載の方法。
- 前記複数のメモリセル(10)の各メモリセルの前記第1の導電領域および前記第2の導電領域(14,16)の少なくとも一方に結合されているビット線(BL0,BL1,…BLn)の全てを接地するステップと、
前記複数のメモリセル(10)の各メモリセルの前記ゲート電極(32)に結合されているワード線(WL0,WL1,…WLm)の全てに正電圧を印加するステップとを有する、請求項1〜3のいずれか1項に記載の方法。 - 前記ワード線(WL0,WL1,…WLm)の全てに印加される前記正電圧は約+9ボルト〜約+11ボルトである、請求項5に記載の方法。
- ソフトプログラミングパルスを印加する前記ステップ(135)は、
前記ゲート電極(32)に約+4ボルト〜約+8ボルトの電位を印加するステップと、
前記第1の導電領域および前記第2の導電領域(14,16)の少なくとも一方に約+3ボルト〜約+5ボルトの電位を印加するステップとを有する、請求項1〜6のいずれか1項に記載の方法。 - ステップ(a)は、前記複数のメモリセル(10)の前記ゲート電極(32)に、約−5ボルト〜−10ボルトの負のゲート消去電位を印加するステップと、
前記複数のメモリセル(10)の前記第1の導電領域および前記第2の導電領域(14,16)の少なくとも一方に約+4ボルト〜約+8ボルトの電位を印加するステップとを有する、請求項2〜7のいずれか1項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/677,790 US6967873B2 (en) | 2003-10-02 | 2003-10-02 | Memory device and method using positive gate stress to recover overerased cell |
US10/677,790 | 2003-10-02 | ||
PCT/US2004/030694 WO2005038815A1 (en) | 2003-10-02 | 2004-09-16 | Memory device and method using positive gate stress to recover overerased cell |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007507830A JP2007507830A (ja) | 2007-03-29 |
JP5160787B2 true JP5160787B2 (ja) | 2013-03-13 |
Family
ID=34393805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006533936A Active JP5160787B2 (ja) | 2003-10-02 | 2004-09-16 | 過剰消去されたセルを復旧させるために、正のゲートストレスを使用したメモリデバイスおよびそのための方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6967873B2 (ja) |
JP (1) | JP5160787B2 (ja) |
KR (1) | KR101099772B1 (ja) |
CN (1) | CN1864231B (ja) |
DE (1) | DE112004001862T5 (ja) |
GB (1) | GB2425201B (ja) |
TW (1) | TWI363349B (ja) |
WO (1) | WO2005038815A1 (ja) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7164177B2 (en) * | 2004-01-02 | 2007-01-16 | Powerchip Semiconductor Corp. | Multi-level memory cell |
DE602004026934D1 (de) * | 2004-08-30 | 2010-06-10 | Spansion Llc | Löschverfahren für nichtflüchtige speicherung und nichtflüchtige speicherung |
JP4521243B2 (ja) * | 2004-09-30 | 2010-08-11 | 株式会社東芝 | 不揮発性半導体記憶装置及びそのデータ消去方法 |
US7535771B2 (en) * | 2004-11-04 | 2009-05-19 | Macronix International Co., Ltd. | Devices and methods to improve erase uniformity and to screen for marginal cells for NROM memories |
US7224619B2 (en) * | 2005-09-09 | 2007-05-29 | Macronix International Co., Ltd. | Method and apparatus for protection from over-erasing nonvolatile memory cells |
KR100705220B1 (ko) | 2005-09-15 | 2007-04-06 | 주식회사 하이닉스반도체 | 프로그램 속도를 증가시키기 위한 플래시 메모리 장치의소거 및 프로그램 방법 |
KR100841980B1 (ko) * | 2006-12-19 | 2008-06-27 | 삼성전자주식회사 | 소거된 셀의 산포를 개선할 수 있는 플래시 메모리 장치의소거 방법 |
US7821838B2 (en) * | 2007-11-19 | 2010-10-26 | Macronix International Co., Ltd. | Method for erasing/programming/correcting a multi-level cell (MLC) |
US7944746B2 (en) * | 2007-11-27 | 2011-05-17 | Spansion Llc | Room temperature drift suppression via soft program after erase |
US7924610B2 (en) * | 2009-01-08 | 2011-04-12 | Elite Semiconductor Memory Technology Inc. | Method for conducting over-erase correction |
CN101923900B (zh) * | 2009-06-09 | 2014-06-11 | 北京兆易创新科技股份有限公司 | 一种非易失存储器的擦除方法及装置 |
CN101923899B (zh) * | 2009-06-09 | 2013-09-18 | 北京兆易创新科技股份有限公司 | 一种非易失存储器的擦除方法及装置 |
US20110002169A1 (en) | 2009-07-06 | 2011-01-06 | Yan Li | Bad Column Management with Bit Information in Non-Volatile Memory Systems |
US8725935B2 (en) | 2009-12-18 | 2014-05-13 | Sandisk Technologies Inc. | Balanced performance for on-chip folding of non-volatile memories |
US20110153912A1 (en) * | 2009-12-18 | 2011-06-23 | Sergey Anatolievich Gorobets | Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory |
US8468294B2 (en) | 2009-12-18 | 2013-06-18 | Sandisk Technologies Inc. | Non-volatile memory with multi-gear control using on-chip folding of data |
US8416624B2 (en) * | 2010-05-21 | 2013-04-09 | SanDisk Technologies, Inc. | Erase and programming techniques to reduce the widening of state distributions in non-volatile memories |
KR20120030818A (ko) | 2010-09-20 | 2012-03-29 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 소거 방법 |
US8289773B2 (en) | 2010-11-09 | 2012-10-16 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) erase operation with brownout recovery technique |
US9342446B2 (en) | 2011-03-29 | 2016-05-17 | SanDisk Technologies, Inc. | Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache |
US8743622B2 (en) | 2012-01-13 | 2014-06-03 | Micron Technology, Inc. | Memory devices and programming methods that program a memory cell with a data value, read the data value from the memory cell and reprogram the memory cell with the read data value |
US8713406B2 (en) | 2012-04-30 | 2014-04-29 | Freescale Semiconductor, Inc. | Erasing a non-volatile memory (NVM) system having error correction code (ECC) |
US8681548B2 (en) | 2012-05-03 | 2014-03-25 | Sandisk Technologies Inc. | Column redundancy circuitry for non-volatile memory |
CN103426473B (zh) * | 2012-05-16 | 2016-07-06 | 北京兆易创新科技股份有限公司 | 收敛存储器擦除单元阈值范围的方法及装置 |
US8995202B2 (en) | 2012-05-21 | 2015-03-31 | Freescale Semiconductor, Inc. | Test flow to detect a latent leaky bit of a non-volatile memory |
US9076506B2 (en) | 2012-09-28 | 2015-07-07 | Sandisk Technologies Inc. | Variable rate parallel to serial shift register |
US8897080B2 (en) | 2012-09-28 | 2014-11-25 | Sandisk Technologies Inc. | Variable rate serial to parallel shift register |
US9490035B2 (en) | 2012-09-28 | 2016-11-08 | SanDisk Technologies, Inc. | Centralized variable rate serializer and deserializer for bad column management |
US8947958B2 (en) | 2012-10-09 | 2015-02-03 | Freescale Semiconductor, Inc. | Latent slow bit detection for non-volatile memory |
US9225356B2 (en) | 2012-11-12 | 2015-12-29 | Freescale Semiconductor, Inc. | Programming a non-volatile memory (NVM) system having error correction code (ECC) |
US8830756B2 (en) | 2013-01-23 | 2014-09-09 | Freescale Semiconductor, Inc. | Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory |
EP3035337B1 (en) * | 2013-08-15 | 2018-11-21 | Renesas Electronics Corporation | Semiconductor device |
EP3128517A4 (en) * | 2014-03-31 | 2018-03-14 | Renesas Electronics Corporation | Semiconductor device, pre-write program, and restoration program |
US9257191B1 (en) | 2014-08-29 | 2016-02-09 | Sandisk Technologies Inc. | Charge redistribution during erase in charge trapping memory |
KR102358463B1 (ko) | 2014-10-20 | 2022-02-07 | 삼성전자주식회사 | 불휘발성 메모리 장치의 동작 방법 |
US9934872B2 (en) | 2014-10-30 | 2018-04-03 | Sandisk Technologies Llc | Erase stress and delta erase loop count methods for various fail modes in non-volatile memory |
US9224502B1 (en) | 2015-01-14 | 2015-12-29 | Sandisk Technologies Inc. | Techniques for detection and treating memory hole to local interconnect marginality defects |
US10032524B2 (en) | 2015-02-09 | 2018-07-24 | Sandisk Technologies Llc | Techniques for determining local interconnect defects |
US9269446B1 (en) | 2015-04-08 | 2016-02-23 | Sandisk Technologies Inc. | Methods to improve programming of slow cells |
US9564219B2 (en) | 2015-04-08 | 2017-02-07 | Sandisk Technologies Llc | Current based detection and recording of memory hole-interconnect spacing defects |
KR102274280B1 (ko) | 2015-06-22 | 2021-07-07 | 삼성전자주식회사 | 불휘발성 메모리 장치의 동작 방법 |
US10510406B1 (en) * | 2018-10-23 | 2019-12-17 | National Tsing Hua University | Soft-verify write assist circuit of resistive memory and operating method thereof |
CN112349328B (zh) * | 2020-10-21 | 2021-08-17 | 中天弘宇集成电路有限责任公司 | 电荷捕获型快闪存储器的编程方法 |
CN115295058B (zh) * | 2022-09-30 | 2023-03-24 | 芯天下技术股份有限公司 | nor flash的全片擦除方法、装置、设备及介质 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5400286A (en) | 1993-08-17 | 1995-03-21 | Catalyst Semiconductor Corp. | Self-recovering erase scheme to enhance flash memory endurance |
US5680350A (en) | 1994-12-14 | 1997-10-21 | Micron Technology, Inc. | Method for narrowing threshold voltage distribution in a block erased flash memory array |
US5936883A (en) * | 1996-03-29 | 1999-08-10 | Sanyo Electric Co., Ltd. | Split gate type transistor memory device |
US5963465A (en) * | 1997-12-12 | 1999-10-05 | Saifun Semiconductors, Ltd. | Symmetric segmented memory array architecture |
US6125059A (en) * | 1999-05-14 | 2000-09-26 | Gatefield Corporation | Method for erasing nonvolatile memory cells in a field programmable gate array |
KR100305030B1 (ko) * | 1999-06-24 | 2001-11-14 | 윤종용 | 플래시 메모리 장치 |
KR100331563B1 (ko) * | 1999-12-10 | 2002-04-06 | 윤종용 | 낸드형 플래쉬 메모리소자 및 그 구동방법 |
US6233177B1 (en) * | 2000-06-22 | 2001-05-15 | Xilinx, Inc. | Bitline latch switching circuit for floating gate memory device requiring zero volt programming voltage |
JP2002299473A (ja) * | 2001-03-29 | 2002-10-11 | Fujitsu Ltd | 半導体記憶装置及びその駆動方法 |
US6532175B1 (en) * | 2002-01-16 | 2003-03-11 | Advanced Micro Devices, In. | Method and apparatus for soft program verification in a memory device |
AU2002367512A1 (en) | 2002-01-16 | 2003-09-02 | Advanced Micro Devices, Inc. | System and method for programming ono dual bit memory cells |
JP4071967B2 (ja) * | 2002-01-17 | 2008-04-02 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置及びそのデータ消去方法 |
US6614694B1 (en) * | 2002-04-02 | 2003-09-02 | Macronix International Co., Ltd. | Erase scheme for non-volatile memory |
US6834012B1 (en) * | 2004-06-08 | 2004-12-21 | Advanced Micro Devices, Inc. | Memory device and methods of using negative gate stress to correct over-erased memory cells |
-
2003
- 2003-10-02 US US10/677,790 patent/US6967873B2/en not_active Expired - Lifetime
-
2004
- 2004-09-16 WO PCT/US2004/030694 patent/WO2005038815A1/en active Application Filing
- 2004-09-16 KR KR1020067006390A patent/KR101099772B1/ko active IP Right Grant
- 2004-09-16 JP JP2006533936A patent/JP5160787B2/ja active Active
- 2004-09-16 GB GB0606725A patent/GB2425201B/en not_active Expired - Fee Related
- 2004-09-16 CN CN2004800289529A patent/CN1864231B/zh active Active
- 2004-09-16 DE DE112004001862T patent/DE112004001862T5/de not_active Ceased
- 2004-09-30 TW TW093129527A patent/TWI363349B/zh active
Also Published As
Publication number | Publication date |
---|---|
GB0606725D0 (en) | 2006-05-10 |
DE112004001862T5 (de) | 2006-08-17 |
KR20060092238A (ko) | 2006-08-22 |
KR101099772B1 (ko) | 2011-12-28 |
GB2425201A (en) | 2006-10-18 |
TWI363349B (en) | 2012-05-01 |
TW200519949A (en) | 2005-06-16 |
JP2007507830A (ja) | 2007-03-29 |
GB2425201B (en) | 2007-04-25 |
WO2005038815A1 (en) | 2005-04-28 |
CN1864231B (zh) | 2010-10-27 |
CN1864231A (zh) | 2006-11-15 |
US6967873B2 (en) | 2005-11-22 |
US20050073886A1 (en) | 2005-04-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5160787B2 (ja) | 過剰消去されたセルを復旧させるために、正のゲートストレスを使用したメモリデバイスおよびそのための方法 | |
US6744675B1 (en) | Program algorithm including soft erase for SONOS memory device | |
JP4869623B2 (ja) | 電荷トラップ不揮発性メモリのための電荷均衡化を有する動作方式 | |
US6269023B1 (en) | Method of programming a non-volatile memory cell using a current limiter | |
US6384447B2 (en) | Flash memory cell for high efficiency programming | |
JP5306115B2 (ja) | 不揮発性半導体記憶装置およびその製造方法 | |
US7414889B2 (en) | Structure and method of sub-gate and architectures employing bandgap engineered SONOS devices | |
KR100761091B1 (ko) | 소프트 프로그래밍이 vt 분포의 폭을 좁힐 수 있게 하는 게이트 램핑 기술 | |
US6618290B1 (en) | Method of programming a non-volatile memory cell using a baking process | |
JP5376414B2 (ja) | メモリアレイの操作方法 | |
US6487121B1 (en) | Method of programming a non-volatile memory cell using a vertical electric field | |
US20060146632A1 (en) | Flash memory device and method for fabricating the same, and programming and erasing method thereof | |
US6778442B1 (en) | Method of dual cell memory device operation for improved end-of-life read margin | |
JP2008506217A (ja) | ダミーワード線を備えたフラッシュメモリアレイの消去電圧分布の改良方法 | |
JP4907173B2 (ja) | 不揮発性メモリセル、これを有するメモリアレイ、並びに、セル及びアレイの操作方法 | |
US6459618B1 (en) | Method of programming a non-volatile memory cell using a drain bias | |
US6452840B1 (en) | Feedback method to optimize electric field during channel erase of flash memory devices | |
US6285599B1 (en) | Decoded source lines to tighten erase Vt distribution | |
US6366501B1 (en) | Selective erasure of a non-volatile memory cell of a flash memory device | |
US6775187B1 (en) | Method of programming a dual cell memory device | |
US6349062B1 (en) | Selective erasure of a non-volatile memory cell of a flash memory device | |
US6331953B1 (en) | Intelligent ramped gate and ramped drain erasure for non-volatile memory cells | |
US6331952B1 (en) | Positive gate erasure for non-volatile memory cells | |
JP4550206B2 (ja) | 不揮発性半導体記憶装置の駆動方法 | |
US7170796B1 (en) | Methods and systems for reducing the threshold voltage distribution following a memory cell erase |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070907 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20071122 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20071122 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100204 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100209 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100324 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100412 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100507 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100818 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100907 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101206 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20110614 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111013 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20111115 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20111209 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120501 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120508 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20120831 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121107 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121213 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5160787 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151221 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |