JP5112275B2 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
JP5112275B2
JP5112275B2 JP2008320008A JP2008320008A JP5112275B2 JP 5112275 B2 JP5112275 B2 JP 5112275B2 JP 2008320008 A JP2008320008 A JP 2008320008A JP 2008320008 A JP2008320008 A JP 2008320008A JP 5112275 B2 JP5112275 B2 JP 5112275B2
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Prior art keywords
chip
sealing
semiconductor
resin
conductive
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JP2008320008A
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English (en)
Japanese (ja)
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JP2010147096A5 (https=
JP2010147096A (ja
Inventor
昭仁 高野
直寛 真篠
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2008320008A priority Critical patent/JP5112275B2/ja
Priority to US12/638,358 priority patent/US8101461B2/en
Publication of JP2010147096A publication Critical patent/JP2010147096A/ja
Publication of JP2010147096A5 publication Critical patent/JP2010147096A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2008320008A 2008-12-16 2008-12-16 半導体装置及び半導体装置の製造方法 Active JP5112275B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008320008A JP5112275B2 (ja) 2008-12-16 2008-12-16 半導体装置及び半導体装置の製造方法
US12/638,358 US8101461B2 (en) 2008-12-16 2009-12-15 Stacked semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008320008A JP5112275B2 (ja) 2008-12-16 2008-12-16 半導体装置及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010147096A JP2010147096A (ja) 2010-07-01
JP2010147096A5 JP2010147096A5 (https=) 2012-01-05
JP5112275B2 true JP5112275B2 (ja) 2013-01-09

Family

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JP2008320008A Active JP5112275B2 (ja) 2008-12-16 2008-12-16 半導体装置及び半導体装置の製造方法

Country Status (2)

Country Link
US (1) US8101461B2 (https=)
JP (1) JP5112275B2 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2932004B1 (fr) * 2008-06-03 2011-08-05 Commissariat Energie Atomique Dispositif electronique empile et procede de realisation d'un tel dispositif electronique
JP5136449B2 (ja) * 2009-02-06 2013-02-06 富士通株式会社 半導体装置の製造方法
US8951839B2 (en) * 2010-03-15 2015-02-10 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP
US8816513B2 (en) * 2012-08-22 2014-08-26 Texas Instruments Incorporated Electronic assembly with three dimensional inkjet printed traces
CN104094401B (zh) * 2012-10-22 2017-04-05 晟碟信息科技（上海）有限公司 用于半导体装置的尾线连接器
ITMI20130473A1 (it) 2013-03-28 2014-09-29 St Microelectronics Srl Metodo per fabbricare dispositivi elettronici
KR101681360B1 (ko) * 2013-11-25 2016-11-30 삼성전기주식회사 전자부품 패키지의 제조방법
JP6421083B2 (ja) 2015-06-15 2018-11-07 株式会社東芝 半導体装置の製造方法
US9935082B2 (en) 2015-12-29 2018-04-03 Micron Technology, Inc. Stacked semiconductor dies with selective capillary under fill
JP2021034606A (ja) * 2019-08-27 2021-03-01 キオクシア株式会社 半導体装置およびその製造方法
US11456272B2 (en) * 2020-09-11 2022-09-27 Western Digital Technologies, Inc. Straight wirebonding of silicon dies

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466634A (en) * 1994-12-20 1995-11-14 International Business Machines Corporation Electronic modules with interconnected surface metallization layers and fabrication methods therefore
JP3847432B2 (ja) * 1997-12-25 2006-11-22 沖電気工業株式会社 樹脂封止半導体装置及びその製造方法
JP3476383B2 (ja) * 1999-05-27 2003-12-10 シャープ株式会社 半導体積層パッケージ
JP3681155B2 (ja) * 1999-12-22 2005-08-10 新光電気工業株式会社 電子部品の実装構造、電子部品装置、電子部品の実装方法及び電子部品装置の製造方法
JP3405456B2 (ja) * 2000-09-11 2003-05-12 沖電気工業株式会社 半導体装置，半導体装置の製造方法，スタック型半導体装置及びスタック型半導体装置の製造方法
JP4014912B2 (ja) * 2001-09-28 2007-11-28 株式会社ルネサステクノロジ 半導体装置
US7215018B2 (en) * 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
CN100539135C (zh) * 2004-09-08 2009-09-09 松下电器产业株式会社 立体电路装置、使用它的电子机器及其制造方法
JP4551321B2 (ja) * 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
WO2007066409A1 (ja) * 2005-12-09 2007-06-14 Spansion Llc 半導体装置およびその製造方法
KR100794658B1 (ko) * 2006-07-07 2008-01-14 삼성전자주식회사 반도체 칩 제조 방법, 이에 의해 형성된 반도체 칩 및 이를포함하는 칩 스택 패키지
KR100813625B1 (ko) * 2006-11-15 2008-03-14 삼성전자주식회사 반도체 소자 패키지
JP5110995B2 (ja) * 2007-07-20 2012-12-26 新光電気工業株式会社 積層型半導体装置及びその製造方法
JP5049684B2 (ja) * 2007-07-20 2012-10-17 新光電気工業株式会社 積層型半導体装置及びその製造方法
JP5110996B2 (ja) * 2007-07-20 2012-12-26 新光電気工業株式会社 積層型半導体装置の製造方法
JP2009071095A (ja) * 2007-09-14 2009-04-02 Spansion Llc 半導体装置の製造方法
TWI355061B (en) * 2007-12-06 2011-12-21 Nanya Technology Corp Stacked-type chip package structure and fabricatio
TW200931634A (en) * 2008-01-10 2009-07-16 Abounion Technology Corp Multi-channel stacked semiconductor device and method for fabricating the same, and stacking substrate applied to the semiconductor device

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Publication number Publication date
JP2010147096A (ja) 2010-07-01
US8101461B2 (en) 2012-01-24
US20100148340A1 (en) 2010-06-17

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