JP5091916B2 - 配線基板及び半導体装置 - Google Patents

配線基板及び半導体装置 Download PDF

Info

Publication number
JP5091916B2
JP5091916B2 JP2009138835A JP2009138835A JP5091916B2 JP 5091916 B2 JP5091916 B2 JP 5091916B2 JP 2009138835 A JP2009138835 A JP 2009138835A JP 2009138835 A JP2009138835 A JP 2009138835A JP 5091916 B2 JP5091916 B2 JP 5091916B2
Authority
JP
Japan
Prior art keywords
wiring
solder
pad
wiring pattern
substrate body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009138835A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010287646A5 (enExample
JP2010287646A (ja
Inventor
太 塚田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009138835A priority Critical patent/JP5091916B2/ja
Publication of JP2010287646A publication Critical patent/JP2010287646A/ja
Publication of JP2010287646A5 publication Critical patent/JP2010287646A5/ja
Application granted granted Critical
Publication of JP5091916B2 publication Critical patent/JP5091916B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)
JP2009138835A 2009-06-10 2009-06-10 配線基板及び半導体装置 Expired - Fee Related JP5091916B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009138835A JP5091916B2 (ja) 2009-06-10 2009-06-10 配線基板及び半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009138835A JP5091916B2 (ja) 2009-06-10 2009-06-10 配線基板及び半導体装置

Publications (3)

Publication Number Publication Date
JP2010287646A JP2010287646A (ja) 2010-12-24
JP2010287646A5 JP2010287646A5 (enExample) 2012-06-07
JP5091916B2 true JP5091916B2 (ja) 2012-12-05

Family

ID=43543154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009138835A Expired - Fee Related JP5091916B2 (ja) 2009-06-10 2009-06-10 配線基板及び半導体装置

Country Status (1)

Country Link
JP (1) JP5091916B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9293405B2 (en) * 2011-03-22 2016-03-22 Renesas Electronics Corporation Semiconductor device
JP2013236039A (ja) * 2012-05-11 2013-11-21 Renesas Electronics Corp 半導体装置
JP6251828B2 (ja) * 2017-01-30 2017-12-20 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04255291A (ja) * 1991-02-07 1992-09-10 Nec Corp 印刷配線板
JP4150511B2 (ja) * 2001-05-16 2008-09-17 株式会社日立製作所 半導体レ−ザ装置
JP3877642B2 (ja) * 2002-05-21 2007-02-07 ローム株式会社 半導体チップを使用した半導体装置
JP2008047761A (ja) * 2006-08-18 2008-02-28 Ricoh Printing Systems Ltd 半導体レーザ装置
JP2008060159A (ja) * 2006-08-29 2008-03-13 Renesas Technology Corp 半導体装置およびその製造方法
JP5018155B2 (ja) * 2007-03-16 2012-09-05 富士通セミコンダクター株式会社 配線基板、電子部品の実装構造、及び半導体装置
JP2009105139A (ja) * 2007-10-22 2009-05-14 Shinko Electric Ind Co Ltd 配線基板及びその製造方法と半導体装置

Also Published As

Publication number Publication date
JP2010287646A (ja) 2010-12-24

Similar Documents

Publication Publication Date Title
US20190295980A1 (en) Flip chip package utilizing trace bump trace interconnection
US10224270B1 (en) Fine pitch copper pillar package and method
US9111818B2 (en) Packaging substrate
JP2013236039A (ja) 半導体装置
US8258617B2 (en) Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method
CN103443915B (zh) 半导体器件
US20170062301A1 (en) Semiconductor device
JP5091916B2 (ja) 配線基板及び半導体装置
TWI493675B (zh) 封裝結構及其製法
TWI613771B (zh) 半導體封裝
JP4494249B2 (ja) 半導体装置
KR20100000328A (ko) 조인트 신뢰성이 향상된 반도체 패키지 및 그 제조방법
US11670574B2 (en) Semiconductor device
JP3949077B2 (ja) 半導体装置、基板、半導体装置の製造方法、及び半導体装置の実装方法
JP2013110264A (ja) 半導体装置及び半導体装置の製造方法
JP4728079B2 (ja) 半導体装置用基板および半導体装置
JP2010192938A (ja) 半導体装置
JP2012199283A (ja) 半導体装置
JP6251828B2 (ja) 半導体装置
KR20250072686A (ko) 반도체 패키지
JP2011077200A (ja) 半導体装置およびその製造方法
JP2012043925A (ja) 半導体装置及びその製造方法
JP2005268604A (ja) 半導体装置及びその製造方法
JP2015201661A (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120417

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120417

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120828

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120911

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120914

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150921

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5091916

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees