JP5081902B2 - レベルシフト・ワード線ドライバを伴うメモリ、およびその動作方法 - Google Patents

レベルシフト・ワード線ドライバを伴うメモリ、およびその動作方法 Download PDF

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JP5081902B2
JP5081902B2 JP2009511128A JP2009511128A JP5081902B2 JP 5081902 B2 JP5081902 B2 JP 5081902B2 JP 2009511128 A JP2009511128 A JP 2009511128A JP 2009511128 A JP2009511128 A JP 2009511128A JP 5081902 B2 JP5081902 B2 JP 5081902B2
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Prior art keywords
voltage
word line
transistor
line driver
cell array
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Japanese (ja)
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JP2009537933A (ja
JP2009537933A5 (enExample
Inventor
ダブリュ． リストン、トーマス
ピー． チョウダリー−ネーグル、シャーナズ
ザ サード、ペリー エイチ． ペレー
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NXP USA Inc
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NXP USA Inc
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Application filed by NXP USA Inc filed Critical NXP USA Inc
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Publication of JP2009537933A5 publication Critical patent/JP2009537933A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144—Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)
JP2009511128A 2006-05-15 2007-03-22 レベルシフト・ワード線ドライバを伴うメモリ、およびその動作方法 Active JP5081902B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/433,998 2006-05-15
US11/433,998 US7440354B2 (en) 2006-05-15 2006-05-15 Memory with level shifting word line driver and method thereof
PCT/US2007/064583 WO2007133849A2 (en) 2006-05-15 2007-03-22 Memory with level shifting word line driver and method thereof

Publications (3)

Publication Number Publication Date
JP2009537933A JP2009537933A (ja) 2009-10-29
JP2009537933A5 JP2009537933A5 (enExample) 2010-05-06
JP5081902B2 true JP5081902B2 (ja) 2012-11-28

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ID=38684957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009511128A Active JP5081902B2 (ja) 2006-05-15 2007-03-22 レベルシフト・ワード線ドライバを伴うメモリ、およびその動作方法

Country Status (6)

Country Link
US (2) US7440354B2 (enExample)
JP (1) JP5081902B2 (enExample)
KR (1) KR20090017521A (enExample)
CN (1) CN101443851B (enExample)
TW (1) TWI462117B (enExample)
WO (1) WO2007133849A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100644224B1 (ko) * 2005-12-06 2006-11-10 삼성전자주식회사 누설전류를 감소시키는 레벨 쉬프트 및 이를 포함하는불휘발성 반도체 메모리 장치의 블락 드라이버
JP2008010082A (ja) * 2006-06-29 2008-01-17 Nec Electronics Corp 不揮発性半導体記憶装置及びワード線駆動方法
US7876612B2 (en) * 2008-10-08 2011-01-25 Nanya Technology Corp. Method for reducing leakage current of a memory and related device
US7940580B2 (en) * 2008-12-19 2011-05-10 Advanced Micro Devices, Inc. Voltage shifting word-line driver and method therefor
US8358540B2 (en) * 2010-01-13 2013-01-22 Micron Technology, Inc. Access line dependent biasing schemes
CN102194517B (zh) * 2010-03-08 2015-05-20 上海华虹宏力半导体制造有限公司 具有输入电压转换单元的存储器
US9411391B2 (en) * 2014-02-07 2016-08-09 Apple Inc. Multistage low leakage address decoder using multiple power modes
KR102155611B1 (ko) * 2014-02-28 2020-09-14 에스케이하이닉스 주식회사 데이터 저장 장치
US9875783B2 (en) * 2014-03-03 2018-01-23 Intel Corporation High voltage tolerant word-line driver
US9922702B1 (en) * 2017-01-03 2018-03-20 Intel Corporation Apparatus for improving read stability
US9881669B1 (en) 2017-03-01 2018-01-30 Globalfoundries Inc. Wordline driver with integrated voltage level shift function
US10388355B1 (en) 2017-12-08 2019-08-20 Rambus Inc. Dual-domain memory
CN110277125B (zh) * 2019-06-28 2020-07-28 长江存储科技有限责任公司 一种存储单元阵列外围电路及存储器件
TWI723944B (zh) 2020-09-21 2021-04-01 崛智科技有限公司 記憶體裝置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3082091B2 (ja) * 1990-07-25 2000-08-28 株式会社日立製作所 半導体集積回路
JP3705842B2 (ja) * 1994-08-04 2005-10-12 株式会社ルネサステクノロジ 半導体装置
JPH0973783A (ja) * 1995-09-07 1997-03-18 Fujitsu Ltd 半導体記憶装置
TW318932B (enExample) * 1995-12-28 1997-11-01 Hitachi Ltd
TW382164B (en) * 1996-04-08 2000-02-11 Hitachi Ltd Semiconductor IC device with tunnel current free MOS transistors for power supply intercept of main logic
JP4017248B2 (ja) * 1998-04-10 2007-12-05 株式会社日立製作所 半導体装置
US6009023A (en) * 1998-05-26 1999-12-28 Etron Technology, Inc. High performance DRAM structure employing multiple thickness gate oxide
JP2000036193A (ja) * 1998-07-17 2000-02-02 Hitachi Ltd 半導体集積回路装置
KR100283907B1 (ko) * 1998-12-09 2001-03-02 김영환 서브워드라인 구동회로를 구비한 반도체 메모리
JP3296319B2 (ja) * 1999-03-02 2002-06-24 日本電気株式会社 ワード線駆動回路及び半導体記憶装置
KR100311041B1 (ko) * 1999-05-07 2001-11-02 윤종용 대기 상태시 누설전류가 발생되지 않는 로우 디코더들 및 칼럼디코더들을 갖는 반도체 메모리장치
JP2001110184A (ja) * 1999-10-14 2001-04-20 Hitachi Ltd 半導体装置
JP3838892B2 (ja) * 2000-08-31 2006-10-25 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置およびそのリフレッシュ方法
JP2003092364A (ja) * 2001-05-21 2003-03-28 Mitsubishi Electric Corp 半導体記憶装置
US7064984B2 (en) * 2002-01-16 2006-06-20 Micron Technology, Inc. Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation
US7205218B2 (en) * 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US20040104756A1 (en) * 2002-12-03 2004-06-03 Payne James E. Voltage level shifter circuit having high speed and low switching power
TWI221059B (en) * 2003-10-21 2004-09-11 Novatek Microelectronics Corp Voltage level shifter
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same
US7242626B2 (en) * 2005-05-06 2007-07-10 Freescale Semiconductor, Inc. Method and apparatus for low voltage write in a static random access memory

Also Published As

Publication number Publication date
JP2009537933A (ja) 2009-10-29
CN101443851A (zh) 2009-05-27
US20070263474A1 (en) 2007-11-15
CN101443851B (zh) 2012-06-13
US7440354B2 (en) 2008-10-21
US7706207B2 (en) 2010-04-27
TW200807439A (en) 2008-02-01
TWI462117B (zh) 2014-11-21
WO2007133849A2 (en) 2007-11-22
WO2007133849A3 (en) 2008-04-10
KR20090017521A (ko) 2009-02-18
US20090021990A1 (en) 2009-01-22

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