JP5079511B2 - 歪みチャネル、及びヘテロ接合ソース／ドレインを有する半導体素子を形成する方法 - Google Patents

歪みチャネル、及びヘテロ接合ソース／ドレインを有する半導体素子を形成する方法 Download PDF

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JP5079511B2
JP5079511B2 JP2007533497A JP2007533497A JP5079511B2 JP 5079511 B2 JP5079511 B2 JP 5079511B2 JP 2007533497 A JP2007533497 A JP 2007533497A JP 2007533497 A JP2007533497 A JP 2007533497A JP 5079511 B2 JP5079511 B2 JP 5079511B2
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layer
semiconductor
source
channel
drain
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JP2008515188A (ja
JP2008515188A5 (enExample
Inventor
テアン、ブーン−ユー
ジー． サダカ、マリアム
アール． ホワイト、テッド
エル． バール、アレクサンドル
アール． コラグンタ、ベンカト
グエン、ビック−イェン
エイチ． バータニアン、ビクター
ジャン、ダ
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/026—Manufacture or treatment of FETs having insulated gates [IGFET] having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2007533497A 2004-09-29 2005-08-31 歪みチャネル、及びヘテロ接合ソース／ドレインを有する半導体素子を形成する方法 Expired - Fee Related JP5079511B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/954,121 US7018901B1 (en) 2004-09-29 2004-09-29 Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
US10/954,121 2004-09-29
PCT/US2005/031001 WO2006039038A2 (en) 2004-09-29 2005-08-31 Method for forming a semiconductor device having a strained channel and a heterojunction source/drain

Publications (3)

Publication Number Publication Date
JP2008515188A JP2008515188A (ja) 2008-05-08
JP2008515188A5 JP2008515188A5 (enExample) 2008-08-28
JP5079511B2 true JP5079511B2 (ja) 2012-11-21

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JP2007533497A Expired - Fee Related JP5079511B2 (ja) 2004-09-29 2005-08-31 歪みチャネル、及びヘテロ接合ソース／ドレインを有する半導体素子を形成する方法

Country Status (5)

Country Link
US (1) US7018901B1 (enExample)
EP (1) EP1797583A2 (enExample)
JP (1) JP5079511B2 (enExample)
KR (1) KR20070061841A (enExample)
WO (1) WO2006039038A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
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EP4033517A1 (fr) * 2021-01-26 2022-07-27 Commissariat à l'Energie Atomique et aux Energies Alternatives Procédé de réalisation de zones à base de sige à différentes concentrations en ge

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FR3119268A1 (fr) * 2021-01-26 2022-07-29 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de réalisation de zones à base de SiGe à différentes concentrations en Ge
US11854805B2 (en) 2021-01-26 2023-12-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for producing SiGe-based zones at different concentrations of Ge

Also Published As

Publication number Publication date
US20060068553A1 (en) 2006-03-30
WO2006039038A2 (en) 2006-04-13
US7018901B1 (en) 2006-03-28
WO2006039038A3 (en) 2006-11-09
JP2008515188A (ja) 2008-05-08
KR20070061841A (ko) 2007-06-14
EP1797583A2 (en) 2007-06-20

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