JP5072584B2 - 積層実装構造体 - Google Patents

積層実装構造体 Download PDF

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Publication number
JP5072584B2
JP5072584B2 JP2007338121A JP2007338121A JP5072584B2 JP 5072584 B2 JP5072584 B2 JP 5072584B2 JP 2007338121 A JP2007338121 A JP 2007338121A JP 2007338121 A JP2007338121 A JP 2007338121A JP 5072584 B2 JP5072584 B2 JP 5072584B2
Authority
JP
Japan
Prior art keywords
mounting structure
stacked
stacked mounting
substrate
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007338121A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009158856A (ja
JP2009158856A5 (https=
Inventor
学 五閑
昭久 中橋
直樹 鈴木
羽生 岩本
祐伯　　聖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2007338121A priority Critical patent/JP5072584B2/ja
Priority to US12/337,267 priority patent/US7875974B2/en
Publication of JP2009158856A publication Critical patent/JP2009158856A/ja
Publication of JP2009158856A5 publication Critical patent/JP2009158856A5/ja
Application granted granted Critical
Publication of JP5072584B2 publication Critical patent/JP5072584B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2007338121A 2007-12-27 2007-12-27 積層実装構造体 Expired - Fee Related JP5072584B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007338121A JP5072584B2 (ja) 2007-12-27 2007-12-27 積層実装構造体
US12/337,267 US7875974B2 (en) 2007-12-27 2008-12-17 Laminated mounting structure and memory card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007338121A JP5072584B2 (ja) 2007-12-27 2007-12-27 積層実装構造体

Publications (3)

Publication Number Publication Date
JP2009158856A JP2009158856A (ja) 2009-07-16
JP2009158856A5 JP2009158856A5 (https=) 2010-11-18
JP5072584B2 true JP5072584B2 (ja) 2012-11-14

Family

ID=40797144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007338121A Expired - Fee Related JP5072584B2 (ja) 2007-12-27 2007-12-27 積層実装構造体

Country Status (2)

Country Link
US (1) US7875974B2 (https=)
JP (1) JP5072584B2 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056099A (ja) * 2008-08-26 2010-03-11 Hitachi Ltd 半導体装置
JP2013219268A (ja) * 2012-04-11 2013-10-24 Sumitomo Electric Ind Ltd 半導体デバイス
US10178786B2 (en) 2015-05-04 2019-01-08 Honeywell International Inc. Circuit packages including modules that include at least one integrated circuit
US9741644B2 (en) * 2015-05-04 2017-08-22 Honeywell International Inc. Stacking arrangement for integration of multiple integrated circuits
JP6380581B1 (ja) 2017-03-08 2018-08-29 日本電気株式会社 基板、回路基板、電子部品、および電子部品組立体
KR102152101B1 (ko) * 2018-11-02 2020-09-07 진영글로벌 주식회사 차량 전장용 디바이스
US11023394B2 (en) 2019-02-19 2021-06-01 Western Digital Technologies, Inc. Socket interconnector with compressible ball contacts for high pad count memory cards
US12159824B2 (en) * 2020-12-23 2024-12-03 Ccs Technology Corporation 3D package configuration
US12354942B2 (en) * 2020-12-23 2025-07-08 Ccs Technology Corporation 3D package configuration
US12255180B2 (en) * 2020-12-23 2025-03-18 Ccs Technology Corporation 3D package configuration
TWI765490B (zh) * 2020-12-23 2022-05-21 晶云科技股份有限公司 3d封裝構造

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2682200B2 (ja) * 1990-05-24 1997-11-26 三菱電機株式会社 半導体装置
JP3012184B2 (ja) * 1996-01-12 2000-02-21 富士通株式会社 実装装置
JP3186700B2 (ja) * 1998-06-24 2001-07-11 日本電気株式会社 半導体装置及びその製造方法
JP2001217388A (ja) 2000-02-01 2001-08-10 Sony Corp 電子装置およびその製造方法
JP4436582B2 (ja) 2000-10-02 2010-03-24 パナソニック株式会社 カード型記録媒体及びその製造方法
US7907420B2 (en) * 2005-03-09 2011-03-15 Panasonic Corporation Bare chip mounted structure and mounting method
JP2007019415A (ja) * 2005-07-11 2007-01-25 Renesas Technology Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US7875974B2 (en) 2011-01-25
JP2009158856A (ja) 2009-07-16
US20090166838A1 (en) 2009-07-02

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