JP5064321B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5064321B2 JP5064321B2 JP2008178768A JP2008178768A JP5064321B2 JP 5064321 B2 JP5064321 B2 JP 5064321B2 JP 2008178768 A JP2008178768 A JP 2008178768A JP 2008178768 A JP2008178768 A JP 2008178768A JP 5064321 B2 JP5064321 B2 JP 5064321B2
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- 239000004065 semiconductor Substances 0.000 title claims description 83
- 238000002955 isolation Methods 0.000 claims description 110
- 239000000758 substrate Substances 0.000 claims description 53
- 238000000926 separation method Methods 0.000 claims description 36
- 239000013078 crystal Substances 0.000 claims description 24
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 18
- 239000010410 layer Substances 0.000 description 51
- 229910021332 silicide Inorganic materials 0.000 description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Description
)。また、図7(a)、(b)は、図6に示すVIIa-VIIa線、およびVIIb-VIIb線における従来の半導体装置の断面図である。
図1は、本発明の第1の実施形態に係る半導体装置において、2入力NANDゲート(左側)と2入力NORゲート(右側)とをMISトランジスタのゲート長方向(図中の左右方向)に隣接させたレイアウト図である。また、図2(a)、(b)は、図1に示すIIa-IIa線、およびIIb-IIb線における第1の実施形態に係る半導体装置の断面図である。ここで、2入力NANDゲートと2入力NORゲートの回路構成は図5(a)、(b)に示す通りである。
次に、活性領域21aを含むN型ウエル領域3a上をマスクで覆った状態で、活性領域21b、21cのうち各ゲート配線およびサイドウォールスペーサ7の外側方に位置する領域にN型不純物をイオン注入してN型ソース/ドレイン領域8bを形成する。なお、P型ソース/ドレイン領域8aとN型ソース/ドレイン領域8bとはどちらを先に形成してもよい。
図3は、本発明の第2の実施形態に係る半導体装置において、2入力NANDゲート(左側)と2入力NORゲート(右側)とをMISトランジスタのゲート長方向(図中の左右方向)に隣接させたレイアウト図である。また、図4(a)、(b)は、図3に示すIVa-IVa線、およびIVb-IVb線における第2の実施形態に係る半導体装置の断面図である。本実施形態の半導体装置は、N型MISトランジスタのN型ソース/ドレイン領域をSiC層で構成し、隣接する2つのN型MISトランジスタ間の電気的分離のためにゲート分離方式を採用したものである。以下の説明において、第1の実施形態と同様の箇所には同一の符号を付し、その説明を省略または簡略化する。
2、2A、2B 素子分離領域
3a N型ウエル領域
3b P型ウエル領域
4 ゲート絶縁膜
6a P型エクステンション領域
6b N型エクステンション領域
7 サイドウォールスペーサ
8a、18a P型ソース/ドレイン領域
8ax P型ソース/ドレイン領域
8b、18b N型ソース/ドレイン領域
18bx N型ソース/ドレイン領域
9 ソース/ドレイン上シリサイド層
10 層間絶縁膜
11 コンタクトプラグ
12 金属配線
21a、31a、31b 活性領域
21b、21c、31c 活性領域
21d、31d N型基板コンタクト領域
21e、31e P型基板コンタクト領域
30 ゲート上シリサイド層
5G1、5G2、5G3、5G4 ゲート配線
5N1、5N2、5N3 分離用ゲート配線
5P1、5P2、5P3 分離用ゲート配線
DN1、DN2、DN3 分離用MISトランジスタ
DP1、DP2、DP3 分離用MISトランジスタ
MN1、MN2、MN3、MN4 N型MISトランジスタ
MP1、MP2、MP3、MP4 P型MISトランジスタ
Claims (14)
- 共に半導体基板内に形成され、ゲート幅方向に隣接する第1導電型の第1のウエル領域および第2導電型の第2のウエル領域と、
前記第1のウエル領域内に形成された素子分離領域に囲まれた前記半導体基板からなる第1の活性領域と、
前記第2のウエル領域内に形成された前記素子分離領域に囲まれた前記半導体基板からなる第2の活性領域と、
前記第1の活性領域上に形成された第1のゲート電極と、前記第1の活性領域における前記第1のゲート電極の側方下の領域に設けられた凹部内に埋め込まれた第1のSi混晶層からなる第2導電型の第1のソース/ドレイン領域とを有する第2導電型の第1のMISトランジスタと、
前記第2の活性領域上に形成された第2のゲート電極と、前記第2の活性領域における前記第2のゲート電極の側方下の領域に形成された第1導電型の第2のソース/ドレイン領域を有する第1導電型の第2のMISトランジスタと、
前記第1の活性領域上に形成され、前記第1のウエル領域と同電位に接続された第1の分離用ゲート電極を有する第2導電型の第1の分離用MISトランジスタとを備え、
前記第2の活性領域には、分離用MISトランジスタは形成されておらず、
前記第1のMISトランジスタの前記第1のソース/ドレイン領域は、前記第1の活性領域におけるゲート長方向の端部に位置する前記素子分離領域には接していないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1のMISトランジスタの前記第1のゲート電極と前記第2のMISトランジスタの前記第2のゲート電極とを含む第1のゲート配線は、前記第1の活性領域上から前記第2の活性領域上に亘って形成されていることを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第1のウエル領域内に、前記第1の活性領域から見てゲート幅方向に前記素子分離領域を挟んで設けられ、前記第2のウエル領域との間で前記第1の活性領域を挟む位置に形成された第1導電型の第1の基板コンタクト領域と、
前記第2のウエル領域内に、前記第2の活性領域から見てゲート幅方向に前記素子分離領域を挟んで設けられ、前記第1のウエル領域との間で前記第2の活性領域を挟む位置に形成された第2導電型の第2の基板コンタクト領域とをさらに備え、
前記第1の分離用MISトランジスタの第1の分離用ゲート電極を含む第1の分離用ゲート配線は、少なくとも前記第1の活性領域を跨いで前記第1の基板コンタクト領域上にまで延びており、前記第1の基板コンタクト領域と同電位に接続されていることを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記第1の分離用ゲート配線は、前記第2の活性領域の側方に位置する前記素子分離領域上まで延びていることを特徴とする半導体装置。 - 請求項1〜4のうちいずれか1項に記載の半導体装置において、
前記第1の活性領域における前記第1の分離用ゲート電極の一側方下の領域には、前記第1のSi混晶層が形成されており、
前記第1の活性領域における前記第1の分離用ゲート電極の他側方下の領域には、前記第1の活性領域に設けられた凹部内に埋め込まれ、前記第1の活性領域におけるゲート長方向の端部に位置する前記素子分離領域に接する第2のSi混晶層が形成されていることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記第2のSi混晶層は、前記第1の混晶層に比べて上面が凹んでいることを特徴とする半導体装置。 - 請求項1〜6に記載の半導体装置において、
前記第1の活性領域上に形成された第3のゲート電極と、前記第1の活性領域における前記第3のゲート電極の側方下の領域に設けられた凹部内に埋め込まれた前記第1のSi混晶層からなる第2導電型の第3のソース/ドレイン領域とを有する第2導電型の第3のMISトランジスタと、
前記第1の活性領域における前記第1のソース/ドレイン領域と前記第3のソース/ドレイン領域との間に位置する領域上に形成され、前記第1のウエル領域と同電位に接続された第2の分離用ゲート電極を有する第2導電型の第2の分離用MISトランジスタとをさらに備えていることを特徴とする半導体装置。 - 請求項7に記載の半導体装置において、
前記第2のウエル領域内に形成された前記素子分離領域に囲まれ、前記第2の活性領域から見てゲート長方向に前記素子分離領域を挟んで設けられた前記半導体基板からなる第3の活性領域と、
前記第3の活性領域上に形成された第4のゲート電極と、前記第3の活性領域における前記第4のゲート電極の側方下の領域に形成された第1導電型の第4のソース/ドレイン領域を有する第1導電型の第4のMISトランジスタとをさらに備え、
前記第2の分離用ゲート電極は、前記第2の活性領域と前記第3の活性領域との間に位置する前記素子分離領域上まで延びていることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記第3のMISトランジスタの前記第3のゲート電極と前記第4のMISトランジスタの前記第4のゲート電極とを含む第2のゲート配線は、前記第1の活性領域上から前記第3の活性領域上に亘って形成されていることを特徴とする半導体装置。 - 請求項1〜4に記載の半導体装置において、
前記第1の活性領域上に形成された第3のゲート電極と、前記第1の活性領域における前記第3のゲート電極の側方下の領域に設けられた凹部内に埋め込まれた前記第1のSi混晶層からなる第2導電型の第3のソース/ドレイン領域とを有する第2導電型の第3のMISトランジスタをさらに備え、
前記第1の分離用ゲート電極は、前記第1の活性領域における前記第1のソース/ドレイン領域と前記第3のソース/ドレイン領域との間に位置する領域上に形成されていることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記第2のウエル領域内に形成された前記素子分離領域に囲まれ、前記第2の活性領域から見てゲート長方向に前記素子分離領域を挟んで設けられた前記半導体基板からなる第3の活性領域と、
前記第3の活性領域上に形成された第4のゲート電極と、前記第3の活性領域における前記第4のゲート電極の側方下の領域に形成された第1導電型の第4のソース/ドレイン領域を有する第1導電型の第4のMISトランジスタとをさらに備えていることを特徴とする半導体装置。 - 請求項11に記載の半導体装置において、
前記第3のMISトランジスタの前記第3のゲート電極と前記第4のMISトランジスタの前記第4のゲート電極とを含む第2のゲート配線は、前記第1の活性領域上から前記第3の活性領域上に亘って形成されていることを特徴とする半導体装置。 - 請求項1〜12に記載の半導体装置において、
前記第1のMISトランジスタはPチャネル型、前記第2のMISトランジスタはNチャネル型であり、
前記第1の分離用ゲート電極は、電源線に接続されており、
前記第1のSi混晶層はSiGeからなることを特徴とする半導体装置。 - 請求項1〜12に記載の半導体装置において、
前記第1のMISトランジスタはNチャネル型、前記第2のMISトランジスタはPチャネル型であり、
前記第1の分離用ゲート電極は、接地線に接続されており、
前記第1のSi混晶層はSiCからなることを特徴とする半導体装置。
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