JP5062558B2 - アクティブマトリクス基板の製造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims description 41
- 239000000758 substrate Substances 0.000 title claims description 26
- 239000011159 matrix material Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000001312 dry etching Methods 0.000 claims description 50
- 239000007789 gas Substances 0.000 claims description 50
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 29
- 230000008021 deposition Effects 0.000 claims description 29
- 238000004380 ashing Methods 0.000 claims description 23
- 229920000642 polymer Polymers 0.000 claims description 18
- 229910045601 alloy Inorganic materials 0.000 claims description 15
- 239000000956 alloy Substances 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- 239000011737 fluorine Substances 0.000 claims description 7
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 65
- 238000005530 etching Methods 0.000 description 46
- 238000001020 plasma etching Methods 0.000 description 27
- 238000000151 deposition Methods 0.000 description 26
- 150000002500 ions Chemical class 0.000 description 19
- 229910021417 amorphous silicon Inorganic materials 0.000 description 12
- 229910018507 Al—Ni Inorganic materials 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 150000003254 radicals Chemical class 0.000 description 3
- 238000007086 side reaction Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- -1 SF5 radicals Chemical class 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013626 chemical specie Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010828 elution Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Description
Cr膜又はAl膜と透明導電膜との間のコンタクト抵抗を低くするためには、ドライエッチングの圧力を高圧化し、自己バイアス電圧を低くすることが有効である。しかし、SF6ガス単体を用いたRIE方式ドライエッチングにおいて、約30Pa以上まで高圧化すると、深い位置に在る電極上のSi絶縁層(ゲート絶縁層)と浅い位置に在る電極上のSi絶縁層(保護膜)との界面において、SF5ラジカルによる等方性エッチングが起こり、界面部分がくさび状にオーバーエッチングされてしまう。この問題は、CF4ガス単体を用いた場合でも同様に起こる。このように、CF4やSF6等のフッ素系ガス単体を用いたRIE方式ドライエッチングでは、コンタクト抵抗の制御と、良好なコンタクトホール形状の形成とを両立する最適条件を得ることが困難である。
SF6ガス単体を用いた場合は、Sの質量数が大きくかつFの結合数も多いため、重いイオンがプラズマ中に生成される。Si絶縁層を除去した後にCr膜又はAl膜表面に存在するCrシリサイド層やAlシリサイド層を除去するためには、最低限のイオン性エッチングが必要である。SF6のイオンが重いために短時間でCrシリサイドが除去され、また、SF6ガスにより生成される化学種はC系ガスのようにCr膜やAl膜の表面を被覆するようなデポジションは起こさないため、Cr膜やAl膜表面のフッ化が進行し、コンタクト抵抗が上昇する。
また、コンタクト抵抗を下げるべくドライエッチング圧力を高圧化した場合には、イオンの分子衝突確率が増加するためCr膜又はAl膜の表面への、RIE方式ドライエッチングの長所である異方性エッチングの効果が弱くなり、等方性でエッチングが進行するラジカル種の寄与が大きくなる。この結果、二層のSi絶縁層間の界面に異常エッチングが進行し易くなり、コンタクトホールのエッチング形状の制御が困難になる。異常エッチングが進行すると、コンタクトホールに形成される透明導電膜が断線し、このアクティブマトリクス基板を用いた液晶表示装置の点欠陥の原因となる。
それ故、本発明の課題は、簡素な工程にも拘わらず、Cr膜又はAl膜から成る電極とコンタクトホールに形成される透明導電膜との間のコンタクト抵抗を低減できるアクティプマトリクス基板の製造方法を提供することである。
本発明においては、エッチング反応に重要なCF3+を選択的に生成し易いCHF3ガスと、デポジション反応に重要なCF4およびO2との混合ガスを用いることによって、イオンダメージを抑制できる。本発明のドライエッチング中に、C系重合物デポジション17が形成される。このC系重合物デポジション17は、Cr膜又はAl膜の保護機能をなすものであると共に、その保護機能が不要になった際にはO2アッシング(図3参照)によって容易に除去できる。
・(ソース・ドレイン電極14a、ドレイン端子電極14bそれぞれの上のSi絶縁層膜厚)=(Si絶縁層15の成膜膜厚)
ここで、Si絶縁層13の残厚とは、半導体(n+a−Si:H/a−Si:H)層のエッチング時にSi絶縁層13の一部もエッチングされるため、Si絶縁層13の成膜膜厚がフルには残存していないからである。水素化アモルファスシリコンTFT製造工程において、半導体(n+a−Si:H/a−Si:H)層の除去時のSi絶縁層エッチング量は、一般的に数十nmである。
12、62 第1の電極
12a ゲート電極
12b ゲート端子電極
13、63 Si絶縁層
14、64 第2の電極
14a ソース・ドレイン電極
14b ドレイン端子電極
15、65 Si絶縁層
16、66 レジスト層
17 C系重合物デポジション
18 真性半導体層
19 オーミック層
Claims (7)
- 絶縁層中の異なる深さ位置に在るフッ素を含むガスを用いたドライエッチングにより揮発しない金属膜にそれぞれ達するように1マスクプロセスによって複数のコンタクトホールを形成するアクティブマトリクス基板の製造方法において、
CHF3とCF4とO2との混合ガスを用いてドライエッチングを行って前記複数のコンタクトホールを形成する工程と、
前記コンタクトホールの表面および該コンタクトホールから露出した前記金属膜の表面に、前記CHF3とCF4とO2との混合ガスに起因するC系重合物デポジションを形成する工程と、
前記混合ガスによって前記C系重合物デポジションをCO2として部分的に除去する工程と、
前記複数のコンタクトホールに対して酸素アッシングを行い前記C系重合物デポジションを完全に除去する工程と、
前記複数のコンタクトホール内に透明導電膜を形成する工程とを有することを特徴とするアクティブマトリクス基板の製造方法。 - 前記金属膜はCr膜、Crを主体とする合金膜、Al膜又はAlを主体とする合金膜であることを特徴とする請求項1に記載のアクティブマトリクス基板の製造方法。
- 前記CHF3とCF4とO2との混合ガスのうちのCHF3およびCF4のガス流量は、CHF3>CF4の関係を満たすことを特徴とする請求項1又請求項2に記載のアクティブマトリクス基板の製造方法。
- 前記ドライエッチング工程において、前記コンタクトホールから露出した前記金属膜がプラズマに晒される時間は、60〜300秒の範囲であることを特徴とする請求項1乃至請求項3の何れかに記載のアクティブマトリクス基板の製造方法。
- 前記酸素アッシングを行う時間は、120〜240秒の範囲であることを特徴とする請求項1乃至請求項4の何れかに記載のアクティブマトリクス基板の製造方法。
- 前記ドライエッチング工程に先立ち、ウェットエッチングを行う工程を有することを特徴とする請求項1乃至請求項5の何れかに記載のアクティブマトリクス基板の製造方法。
- 前記ドライエッチング工程において、前記コンタクトホールおよび該コンタクトホールから露出した前記金属膜に、オーバーエッチングを施すことを特徴とする請求項1乃至請求項6の何れかに記載のアクティブマトリクス基板の製造方法。
Priority Applications (3)
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JP2007154003A JP5062558B2 (ja) | 2006-07-25 | 2007-06-11 | アクティブマトリクス基板の製造方法 |
CN2007101386165A CN101114613B (zh) | 2006-07-25 | 2007-07-24 | 制造有源矩阵基板的方法 |
US11/782,929 US7855152B2 (en) | 2006-07-25 | 2007-07-25 | Method of producing active matrix substrate |
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JP5276926B2 (ja) * | 2008-08-25 | 2013-08-28 | ラピスセミコンダクタ株式会社 | コンタクトホール側壁の抵抗値測定方法 |
JP5442234B2 (ja) | 2008-10-24 | 2014-03-12 | 株式会社半導体エネルギー研究所 | 半導体装置及び表示装置 |
JP4752967B2 (ja) * | 2009-01-27 | 2011-08-17 | カシオ計算機株式会社 | 多層膜の形成方法及び表示パネルの製造方法 |
KR101682092B1 (ko) | 2009-11-12 | 2016-12-05 | 삼성디스플레이 주식회사 | 박막 트랜지스터 표시판 및 이를 포함하는 액정 표시 장치 |
CN102802655A (zh) | 2010-01-15 | 2012-11-28 | 康奈尔大学 | 降低细胞内蛋白质水平的方法 |
JP6294429B2 (ja) * | 2016-10-26 | 2018-03-14 | 株式会社半導体エネルギー研究所 | 液晶表示装置 |
JP6639732B2 (ja) * | 2017-03-27 | 2020-02-05 | 株式会社アルバック | 電子部品の製造方法 |
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CN107833833B (zh) * | 2017-11-28 | 2020-01-21 | 上海华力微电子有限公司 | 一种形成不同深度接触孔的刻蚀方法 |
WO2020049690A1 (ja) * | 2018-09-06 | 2020-03-12 | シャープ株式会社 | アクティブマトリクス基板の製造方法及びアクティブマトリクス基板 |
CN110941124B (zh) * | 2019-12-02 | 2021-06-01 | Tcl华星光电技术有限公司 | 一种阵列基板、阵列基板制程方法及显示面板 |
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JP2001308182A (ja) * | 2000-04-27 | 2001-11-02 | Nec Corp | Cr膜とのコンタクトの形成方法 |
JP2002110641A (ja) * | 2000-09-27 | 2002-04-12 | Ricoh Co Ltd | 半導体装置の製造方法 |
US6271084B1 (en) * | 2001-01-16 | 2001-08-07 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process |
JP2002296609A (ja) * | 2001-03-29 | 2002-10-09 | Nec Corp | 液晶表示装置及びその製造方法 |
US20020142610A1 (en) * | 2001-03-30 | 2002-10-03 | Ting Chien | Plasma etching of dielectric layer with selectivity to stop layer |
JP2003109955A (ja) * | 2001-10-01 | 2003-04-11 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
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2007
- 2007-06-11 JP JP2007154003A patent/JP5062558B2/ja active Active
- 2007-07-24 CN CN2007101386165A patent/CN101114613B/zh active Active
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US20080026573A1 (en) | 2008-01-31 |
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US7855152B2 (en) | 2010-12-21 |
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