JP5010031B2 - ページ内・ページ間オンチップデータ擬似ランダム化のための不揮発性メモリおよび方法 - Google Patents

ページ内・ページ間オンチップデータ擬似ランダム化のための不揮発性メモリおよび方法 Download PDF

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JP5010031B2
JP5010031B2 JP2010524087A JP2010524087A JP5010031B2 JP 5010031 B2 JP5010031 B2 JP 5010031B2 JP 2010524087 A JP2010524087 A JP 2010524087A JP 2010524087 A JP2010524087 A JP 2010524087A JP 5010031 B2 JP5010031 B2 JP 5010031B2
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page
data
memory
programming
read
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JP2010538408A (ja
JP2010538408A5 (enExample
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リ，ヤン
カーウイング フォング，ユーピン
モクレシー，ニーマ
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SanDisk Corp
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SanDisk Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5647—Multilevel memory with bit inversion arrangement

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2010524087A 2007-09-07 2008-08-20 ページ内・ページ間オンチップデータ擬似ランダム化のための不揮発性メモリおよび方法 Expired - Fee Related JP5010031B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/852,229 2007-09-07
US11/852,229 US7885112B2 (en) 2007-09-07 2007-09-07 Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages
PCT/US2008/073750 WO2009035834A2 (en) 2007-09-07 2008-08-20 Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages

Related Child Applications (1)

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JP2012087398A Division JP5537590B2 (ja) 2007-09-07 2012-04-06 ページ内・ページ間オンチップデータ擬似ランダム化のための不揮発性メモリおよび方法

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JP2010538408A JP2010538408A (ja) 2010-12-09
JP2010538408A5 JP2010538408A5 (enExample) 2011-09-22
JP5010031B2 true JP5010031B2 (ja) 2012-08-29

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JP2012087398A Expired - Fee Related JP5537590B2 (ja) 2007-09-07 2012-04-06 ページ内・ページ間オンチップデータ擬似ランダム化のための不揮発性メモリおよび方法

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US (1) US7885112B2 (enExample)
EP (1) EP2186094B1 (enExample)
JP (2) JP5010031B2 (enExample)
KR (1) KR101533965B1 (enExample)
CN (1) CN102318007B (enExample)
AT (1) ATE549719T1 (enExample)
TW (1) TWI383396B (enExample)
WO (1) WO2009035834A2 (enExample)

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EP2186094A2 (en) 2010-05-19
CN102318007B (zh) 2015-02-18
CN102318007A (zh) 2012-01-11
US7885112B2 (en) 2011-02-08
WO2009035834A2 (en) 2009-03-19
JP5537590B2 (ja) 2014-07-02
JP2012169034A (ja) 2012-09-06
KR20100075833A (ko) 2010-07-05
WO2009035834A3 (en) 2009-05-22
US20090067244A1 (en) 2009-03-12
TWI383396B (zh) 2013-01-21
EP2186094B1 (en) 2012-03-14
TW200929219A (en) 2009-07-01
ATE549719T1 (de) 2012-03-15
KR101533965B1 (ko) 2015-07-06

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