JP4989821B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP4989821B2 JP4989821B2 JP2001029215A JP2001029215A JP4989821B2 JP 4989821 B2 JP4989821 B2 JP 4989821B2 JP 2001029215 A JP2001029215 A JP 2001029215A JP 2001029215 A JP2001029215 A JP 2001029215A JP 4989821 B2 JP4989821 B2 JP 4989821B2
- Authority
- JP
- Japan
- Prior art keywords
- memory array
- row
- column
- data bus
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001029215A JP4989821B2 (ja) | 2001-02-06 | 2001-02-06 | 半導体記憶装置 |
| US09/907,743 US6496441B2 (en) | 2001-02-06 | 2001-07-19 | Semiconductor memory device with improved data propagation characteristics of a data bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001029215A JP4989821B2 (ja) | 2001-02-06 | 2001-02-06 | 半導体記憶装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010204363A Division JP5036856B2 (ja) | 2010-09-13 | 2010-09-13 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002230976A JP2002230976A (ja) | 2002-08-16 |
| JP2002230976A5 JP2002230976A5 (enExample) | 2008-01-10 |
| JP4989821B2 true JP4989821B2 (ja) | 2012-08-01 |
Family
ID=18893589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001029215A Expired - Fee Related JP4989821B2 (ja) | 2001-02-06 | 2001-02-06 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6496441B2 (enExample) |
| JP (1) | JP4989821B2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002237188A (ja) * | 2001-02-13 | 2002-08-23 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2003100073A (ja) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP4497327B2 (ja) * | 2006-12-19 | 2010-07-07 | エルピーダメモリ株式会社 | 半導体記憶装置 |
| TW200845003A (en) * | 2007-05-01 | 2008-11-16 | Nanya Technology Corp | Semiconductor device and memory circuit layout method |
| US8159898B2 (en) * | 2008-01-18 | 2012-04-17 | Hynix Semiconductor Inc. | Architecture of highly integrated semiconductor memory device |
| KR100996187B1 (ko) * | 2008-01-18 | 2010-11-24 | 주식회사 하이닉스반도체 | 고집적 반도체 메모리 장치의 내부 구조 |
| US9700286B2 (en) | 2012-04-25 | 2017-07-11 | Kph Diagnostics Inc. | Fluid sample collection and testing device |
| KR102127966B1 (ko) * | 2013-12-20 | 2020-06-30 | 에스케이하이닉스 주식회사 | 반도체 장치 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209694A (ja) * | 1990-01-12 | 1991-09-12 | Sharp Corp | 半導体記憶装置 |
| KR0164391B1 (ko) * | 1995-06-29 | 1999-02-18 | 김광호 | 고속동작을 위한 회로 배치 구조를 가지는 반도체 메모리 장치 |
| JPH09231760A (ja) * | 1995-12-20 | 1997-09-05 | Toshiba Corp | 半導体記憶装置 |
| KR970051258A (ko) * | 1995-12-28 | 1997-07-29 | 문정환 | 반도체 메모리의 데이타 버스 구동 회로 |
| JPH11145420A (ja) | 1997-11-07 | 1999-05-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH11265573A (ja) * | 1998-01-13 | 1999-09-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH11203862A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6072743A (en) | 1998-01-13 | 2000-06-06 | Mitsubishi Denki Kabushiki Kaisha | High speed operable semiconductor memory device with memory blocks arranged about the center |
| JPH11204749A (ja) * | 1998-01-19 | 1999-07-30 | Mitsubishi Electric Corp | 半導体装置 |
-
2001
- 2001-02-06 JP JP2001029215A patent/JP4989821B2/ja not_active Expired - Fee Related
- 2001-07-19 US US09/907,743 patent/US6496441B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002230976A (ja) | 2002-08-16 |
| US20020105849A1 (en) | 2002-08-08 |
| US6496441B2 (en) | 2002-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9390780B2 (en) | Semiconductor memory device | |
| KR100855586B1 (ko) | 반도체 메모리 장치 및 그의 레이아웃 방법 | |
| JP4982711B2 (ja) | 高速動作のためのメモリチップ構造 | |
| US20040004897A1 (en) | Layout structures of data input/output pads and peripheral circuits of integrated circuit memory devices | |
| JP4989821B2 (ja) | 半導体記憶装置 | |
| JP2010272168A (ja) | 半導体装置 | |
| JP4667708B2 (ja) | 半導体メモリ装置及びコンピュータシステム | |
| JP6054017B2 (ja) | 半導体記憶装置 | |
| US6215721B1 (en) | Multi-bank memory device and method for arranging input/output lines | |
| KR100533977B1 (ko) | 셀영역의 면적을 감소시킨 반도체 메모리 장치 | |
| US6118727A (en) | Semiconductor memory with interdigitated array having bit line pairs accessible from either of two sides of the array | |
| JP5036856B2 (ja) | 半導体記憶装置 | |
| JPH08255479A (ja) | 半導体記憶装置 | |
| KR100696770B1 (ko) | 고속력 디램을 위한 프리패치 장치 | |
| JP3732111B2 (ja) | 半導体装置 | |
| EP0788109B1 (en) | Semiconductor integrated circuit having improved wiring in input terminal | |
| KR100734323B1 (ko) | 분산 배치된 데이터 입출력 라인들을 가지는 반도체 메모리장치 | |
| US6477074B2 (en) | Semiconductor memory integrated circuit having high-speed data read and write operations | |
| KR100382739B1 (ko) | 비대칭 데이터 경로를 갖는 반도체 메모리 장치 | |
| JPH09231760A (ja) | 半導体記憶装置 | |
| US9396773B2 (en) | Semiconductor device | |
| KR100703834B1 (ko) | 고속 동작을 위한 메모리 칩 아키텍쳐 | |
| KR100849071B1 (ko) | 반도체 메모리 장치 | |
| JP3586946B2 (ja) | 半導体記憶装置 | |
| KR0172360B1 (ko) | 반도체 메모리 장치의 칩내부 배치방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071119 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071119 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100519 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100713 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100720 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100913 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110621 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110809 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120424 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120501 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150511 Year of fee payment: 3 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |