JP4964091B2 - メモリアクセス方法およびメモリ制御装置 - Google Patents

メモリアクセス方法およびメモリ制御装置 Download PDF

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Publication number
JP4964091B2
JP4964091B2 JP2007281979A JP2007281979A JP4964091B2 JP 4964091 B2 JP4964091 B2 JP 4964091B2 JP 2007281979 A JP2007281979 A JP 2007281979A JP 2007281979 A JP2007281979 A JP 2007281979A JP 4964091 B2 JP4964091 B2 JP 4964091B2
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Japan
Prior art keywords
block
row address
address
access
memory
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JP2007281979A
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English (en)
Japanese (ja)
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JP2009110600A5 (enExample
JP2009110600A (ja
Inventor
慎祐 佐藤
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Kawasaki Microelectronics Inc
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Kawasaki Microelectronics Inc
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Priority to JP2007281979A priority Critical patent/JP4964091B2/ja
Priority to US12/289,446 priority patent/US8064282B2/en
Priority to CN2008101751356A priority patent/CN101425040B/zh
Publication of JP2009110600A publication Critical patent/JP2009110600A/ja
Publication of JP2009110600A5 publication Critical patent/JP2009110600A5/ja
Application granted granted Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2007281979A 2007-10-30 2007-10-30 メモリアクセス方法およびメモリ制御装置 Active JP4964091B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007281979A JP4964091B2 (ja) 2007-10-30 2007-10-30 メモリアクセス方法およびメモリ制御装置
US12/289,446 US8064282B2 (en) 2007-10-30 2008-10-28 Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same
CN2008101751356A CN101425040B (zh) 2007-10-30 2008-10-30 存储器的存取方法、存储控制电路和存储系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007281979A JP4964091B2 (ja) 2007-10-30 2007-10-30 メモリアクセス方法およびメモリ制御装置

Publications (3)

Publication Number Publication Date
JP2009110600A JP2009110600A (ja) 2009-05-21
JP2009110600A5 JP2009110600A5 (enExample) 2012-01-19
JP4964091B2 true JP4964091B2 (ja) 2012-06-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007281979A Active JP4964091B2 (ja) 2007-10-30 2007-10-30 メモリアクセス方法およびメモリ制御装置

Country Status (3)

Country Link
US (1) US8064282B2 (enExample)
JP (1) JP4964091B2 (enExample)
CN (1) CN101425040B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009169257A (ja) * 2008-01-18 2009-07-30 Kawasaki Microelectronics Inc メモリ制御回路および画像処理装置
CN101511021B (zh) * 2009-03-24 2014-10-29 北京中星微电子有限公司 在sdram中存取图像数据的方法
US20110194606A1 (en) * 2010-02-09 2011-08-11 Cheng-Yu Hsieh Memory management method and related memory apparatus
JP2013231918A (ja) * 2012-05-01 2013-11-14 Samsung R&D Institute Japan Co Ltd フレームメモリの制御回路、表示装置及びフレームメモリの制御方法
CN111831212B (zh) * 2019-04-19 2023-07-04 杭州海康威视数字技术股份有限公司 一种数据写入、读取方法、装置及设备

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710879A (en) 1980-06-20 1982-01-20 Mitsubishi Electric Corp Picture memory device
US4482979A (en) 1982-02-04 1984-11-13 May George A Video computing system with automatically refreshed memory
JPS5954095A (ja) 1982-09-20 1984-03-28 Toshiba Corp ビデオｒａｍリフレッシュ方式
US4587559A (en) 1983-03-11 1986-05-06 Welch Allyn, Inc. Refreshing of dynamic memory
JPS60113395A (ja) 1983-11-25 1985-06-19 Hitachi Ltd メモリ制御回路
JPS6251095A (ja) 1985-08-29 1987-03-05 Nec Corp 画像メモリ駆動方式
KR920009770B1 (ko) * 1990-10-31 1992-10-22 삼성전자 주식회사 영상기록재생장치에서 메모리내 프레임 데이타 어드레싱 방식
JPH04285790A (ja) * 1991-03-14 1992-10-09 Murata Mach Ltd テレビ電話機用フレームメモリ装置
JPH07287668A (ja) * 1994-04-19 1995-10-31 Hitachi Ltd データ処理装置
JPH08123953A (ja) * 1994-10-21 1996-05-17 Mitsubishi Electric Corp 画像処理装置
JPH08204921A (ja) * 1995-01-31 1996-08-09 Sony Corp スキャナ装置
US5784698A (en) * 1995-12-05 1998-07-21 International Business Machines Corporation Dynamic memory allocation that enalbes efficient use of buffer pool memory segments
JP3359270B2 (ja) 1997-10-24 2002-12-24 キヤノン株式会社 メモリー制御装置と液晶表示装置
JP2000284771A (ja) 1999-03-31 2000-10-13 Fujitsu General Ltd 映像データ処理装置
JP2000315386A (ja) * 1999-04-30 2000-11-14 Sony Corp メモリのアドレシング方法およびデータ処理装置
JP2003068072A (ja) 2001-08-30 2003-03-07 Fujitsu General Ltd フレームメモリ回路

Also Published As

Publication number Publication date
JP2009110600A (ja) 2009-05-21
US8064282B2 (en) 2011-11-22
CN101425040A (zh) 2009-05-06
CN101425040B (zh) 2013-01-16
US20090109784A1 (en) 2009-04-30

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