JP4926275B2 - トランジスタスナップバック保護を組み込むレベルシフタ回路 - Google Patents

トランジスタスナップバック保護を組み込むレベルシフタ回路 Download PDF

Info

Publication number
JP4926275B2
JP4926275B2 JP2010501285A JP2010501285A JP4926275B2 JP 4926275 B2 JP4926275 B2 JP 4926275B2 JP 2010501285 A JP2010501285 A JP 2010501285A JP 2010501285 A JP2010501285 A JP 2010501285A JP 4926275 B2 JP4926275 B2 JP 4926275B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
node
coupled
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010501285A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010524303A (ja
JP2010524303A5 (enExample
Inventor
ジェイ． ソープ，タイラー
ジー． ファゾーリ，ルカ
Original Assignee
サンディスク スリーディー，エルエルシー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/695,011 external-priority patent/US7696804B2/en
Priority claimed from US11/695,013 external-priority patent/US7696805B2/en
Application filed by サンディスク スリーディー，エルエルシー filed Critical サンディスク スリーディー，エルエルシー
Publication of JP2010524303A publication Critical patent/JP2010524303A/ja
Publication of JP2010524303A5 publication Critical patent/JP2010524303A5/ja
Application granted granted Critical
Publication of JP4926275B2 publication Critical patent/JP4926275B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
JP2010501285A 2007-03-31 2008-03-31 トランジスタスナップバック保護を組み込むレベルシフタ回路 Active JP4926275B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/695,011 US7696804B2 (en) 2007-03-31 2007-03-31 Method for incorporating transistor snap-back protection in a level shifter circuit
US11/695,013 US7696805B2 (en) 2007-03-31 2007-03-31 Level shifter circuit incorporating transistor snap-back protection
US11/695,011 2007-03-31
US11/695,013 2007-03-31
PCT/US2008/058933 WO2008121977A2 (en) 2007-03-31 2008-03-31 Level shifter circuit incorporating transistor snap-back protection

Publications (3)

Publication Number Publication Date
JP2010524303A JP2010524303A (ja) 2010-07-15
JP2010524303A5 JP2010524303A5 (enExample) 2010-08-26
JP4926275B2 true JP4926275B2 (ja) 2012-05-09

Family

ID=39808890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010501285A Active JP4926275B2 (ja) 2007-03-31 2008-03-31 トランジスタスナップバック保護を組み込むレベルシフタ回路

Country Status (6)

Country Link
EP (1) EP2132873B1 (enExample)
JP (1) JP4926275B2 (enExample)
KR (1) KR101505396B1 (enExample)
CN (1) CN101682328B (enExample)
TW (1) TWI350055B (enExample)
WO (1) WO2008121977A2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7755392B1 (en) * 2009-05-21 2010-07-13 Ememory Technology Inc. Level shift circuit without high voltage stress of transistors and operating at low voltages
TWI413892B (zh) * 2009-08-18 2013-11-01 Ememory Technology Inc 負電壓位準移位器
TWI410048B (zh) * 2010-06-03 2013-09-21 Orise Technology Co Ltd 轉壓器
US9270273B2 (en) * 2011-10-28 2016-02-23 Texas Instruments Incorporated Level shifter
WO2014020724A1 (ja) * 2012-08-01 2014-02-06 ルネサスエレクトロニクス株式会社 レベルシフト回路、半導体装置
US9608615B2 (en) * 2015-06-12 2017-03-28 Cypress Semiconductor Corporation Negative high voltage hot switching circuit
US11223359B2 (en) * 2016-03-31 2022-01-11 Qualcomm Incorporated Power efficient voltage level translator circuit
US10164637B2 (en) * 2017-02-24 2018-12-25 Qualcomm Incorporated Level shifter for voltage conversion
CN108667450B (zh) * 2017-03-29 2022-08-09 台湾积体电路制造股份有限公司 位准移位器与位准移位方法
US10535386B2 (en) * 2017-05-23 2020-01-14 Arm Limited Level shifter with bypass
CN108173544A (zh) * 2017-12-30 2018-06-15 惠州市蓝微新源技术有限公司 一种可兼容输入或输出控制的io端口电路
US10284201B1 (en) * 2018-01-23 2019-05-07 Stmicroelectronics International N.V. High range positive voltage level shifter using low voltage devices
CN112865255B (zh) * 2018-02-06 2025-05-09 凹凸电子（武汉）有限公司 管理电池组的控制器、系统和方法
CN109347473A (zh) * 2018-09-04 2019-02-15 上海东软载波微电子有限公司 电平移位电路
US10797064B2 (en) * 2018-09-19 2020-10-06 Ememory Technology Inc. Single-poly non-volatile memory cell and operating method thereof
US11152937B2 (en) 2019-05-31 2021-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifter
DE102020106236A1 (de) 2019-05-31 2020-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Pegelumsetzer
EP3813261B1 (en) * 2019-10-25 2024-12-11 Nxp B.V. An apparatus including a level shifter
TWI770999B (zh) * 2021-05-12 2022-07-11 友達光電股份有限公司 電壓調變電路及其操作方法
CN115378421A (zh) 2021-07-13 2022-11-22 台湾积体电路制造股份有限公司 电平移位电路和方法
TWI901313B (zh) * 2024-08-19 2025-10-11 世界先進積體電路股份有限公司 信號產生電路及控制裝置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100197188B1 (ko) * 1995-04-17 1999-06-15 모리시다 요이치 고내압회로 및 전압레벨 변환회로
JPH0918328A (ja) * 1995-06-30 1997-01-17 Hitachi Ltd 電圧レベルシフト回路
US5723987A (en) * 1996-06-06 1998-03-03 Intel Corporation Level shifting output buffer with p channel pulldown transistors which are bypassed
JP3037236B2 (ja) * 1997-11-13 2000-04-24 日本電気アイシーマイコンシステム株式会社 レベルシフタ回路
GB2349996A (en) * 1999-05-12 2000-11-15 Sharp Kk Voltage level converter for an active matrix LCD
CN1214531C (zh) * 1999-10-15 2005-08-10 威盛电子股份有限公司 使用栅极电压控制的单端输入电压电平转换器
FR2817413B1 (fr) * 2000-11-29 2003-02-28 St Microelectronics Sa Dispositif de commutation d'une haute tension et application a une memoire non volatile
FR2822309B1 (fr) 2001-03-19 2003-06-13 St Microelectronics Sa Circuit de translation de signaux de commutation
JP2006295252A (ja) * 2005-04-05 2006-10-26 Matsushita Electric Ind Co Ltd レベルシフト回路及びレベルシフト装置

Also Published As

Publication number Publication date
CN101682328B (zh) 2014-04-30
EP2132873B1 (en) 2012-08-22
WO2008121977A3 (en) 2008-12-04
EP2132873A2 (en) 2009-12-16
WO2008121977A2 (en) 2008-10-09
TWI350055B (en) 2011-10-01
JP2010524303A (ja) 2010-07-15
EP2132873A4 (en) 2010-06-02
KR101505396B1 (ko) 2015-03-25
CN101682328A (zh) 2010-03-24
TW200847627A (en) 2008-12-01
KR20100016050A (ko) 2010-02-12

Similar Documents

Publication Publication Date Title
JP4926275B2 (ja) トランジスタスナップバック保護を組み込むレベルシフタ回路
US7696805B2 (en) Level shifter circuit incorporating transistor snap-back protection
US7696804B2 (en) Method for incorporating transistor snap-back protection in a level shifter circuit
US6459322B1 (en) Level adjustment circuit and data output circuit thereof
EP3197051A1 (en) Driving circuit for non-volatile memory
US8154323B2 (en) Output driver operable over wide range of voltages
KR100419816B1 (ko) 신호 전위 변환 회로
KR960011964B1 (ko) 출력버퍼장치
US11979155B2 (en) Semiconductor integrated circuit device and level shifter circuit
US20060103437A1 (en) Power-on reset circuit
US6809565B2 (en) Semiconductor device
TW567493B (en) Semiconductor device and source voltage control method
US7268613B2 (en) Transistor switch with integral body connection to prevent latchup
US8030987B2 (en) Level shifter circuit and semiconductor device having the same
US20050093610A1 (en) Delay circuit with constant delay time regardless of process condition or voltage variation and pulse generator using the same
CN105405466B (zh) 数据读出电路
US20110102024A1 (en) Data output circuit
US9407255B2 (en) Circuit
CN108564979B (zh) 单端读取电路
JP3255158B2 (ja) 半導体集積回路
US6559678B1 (en) Node predisposition circuit
JP2005516443A (ja) 電圧制限半導体パスゲート回路
KR100904740B1 (ko) 내부전압 보상회로
US8629696B2 (en) Semiconductor device and level shifting circuit for the same
US8194491B2 (en) Power-up circuit

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100430

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110228

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120124

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120207

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150217

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4926275

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350