JP4921898B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- JP4921898B2 JP4921898B2 JP2006241537A JP2006241537A JP4921898B2 JP 4921898 B2 JP4921898 B2 JP 4921898B2 JP 2006241537 A JP2006241537 A JP 2006241537A JP 2006241537 A JP2006241537 A JP 2006241537A JP 4921898 B2 JP4921898 B2 JP 4921898B2
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- photosensitive film
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- hard mask
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- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 238000000034 method Methods 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 239000003431 cross linking reagent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Materials For Photolithography (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Formation Of Insulating Films (AREA)
Description
(1)半導体基板の上部に被食刻層、ハードマスク層、反射防止膜及びシリコンを含む第1の感光膜を順次形成する段階と、
(2)前記第1の感光膜を第1の露光マスクを利用して露光した後現像して第1の感光膜パターンを形成する段階と、
(3)前記第1の感光膜パターンにO2プラズマを処理する段階と、
(4)前記結果物の上部に第2の感光膜を形成し、第2の露光マスクを利用して第1の感光膜パターンと重なり合わない第2の感光膜パターンを形成する段階と、
(5)前記第1及び第2の感光膜パターンを食刻マスクに利用して前記反射防止膜を食刻した後、前記第1及び第2の感光膜パターンを除去して反射防止膜パターンを形成する段階と、
(6)前記反射防止膜パターンを食刻マスクに前記ハードマスク層を食刻してハードマスクパターンを形成した後、前記ハードマスクパターンを食刻マスクに前記被食刻層を食刻して被食刻層パターンを形成する段階とを含む。
図2a及び図2bに示されているように、半導体基板110の上部に被食刻層120、ハードマスク層130、反射防止膜140及び第1の感光膜150を順次形成した後、第1の露光マスク160を利用して全体表面の第1の領域を露光し、前記第1の感光膜150を現像して第1の感光膜パターン150’を形成する。
12、120 被食刻層
13、17、130 ハードマスク層
14、18、140 反射防止膜
15、19、150、190 感光膜
16、160、20、200 露光マスク
12’、120’ 被食刻層パターン
13’、17’、130’ ハードマスクパターン
14’、18’、140’ 反射防止膜パターン
15’、19’、150’、190’ 感光膜パターン
155 O2プラズマ処理されたSiO2含有の感光膜パターン
Claims (7)
- (1)半導体基板の上部に被食刻層、ハードマスク層、反射防止膜及びシリコンを含む第1の感光膜を順次形成する段階と、
(2)前記第1の感光膜を第1の露光マスクを利用して露光した後現像して第1の感光膜パターンを形成する段階と、
(3)前記第1の感光膜パターンにO2プラズマを処理する段階と、
(4)前記結果物の上部に第2の感光膜を形成し、第2の露光マスクを利用して第1の感光膜パターンと重なり合わない第2の感光膜パターンを形成する段階と、
(5)前記第1及び第2の感光膜パターンを食刻マスクに利用して前記反射防止膜を食刻した後、前記第1及び第2の感光膜パターンを除去して反射防止膜パターンを形成する段階と、
(6)前記反射防止膜パターンを食刻マスクに前記ハードマスク層を食刻してハードマスクパターンを形成した後、前記ハードマスクパターンを食刻マスクに前記被食刻層を食刻して被食刻層パターンを形成する段階とを含む半導体素子の製造方法。 - 前記第1の感光膜は10〜40重量%含量のシリコンを含むことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第2の感光膜は前記第1の感光膜と同一であるか、相違する物質で形成することを特徴とする請求項1または2に記載の半導体素子の製造方法。
- 前記露光源はArF(193nm)、KrF(248nm)、EUV、VUV(157nm)、E−ビーム、X線及びイオンビームでなる群から選択されることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記ハードマスク層は、被食刻層の上部に非晶質炭素層及び無機系ハードマスク層の二重層で形成されることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第1の感光膜パターン及び第2の感光膜パターンは互いに交互に形成されることを特徴とする請求項1に記載の半導体素子の製造方法。
- (1)半導体基板の上部に被食刻層、反射防止膜及びシリコンを含む第1の感光膜を順次形成する段階と、
(2)前記第1の感光膜を第1の露光マスクを利用して露光したあと現像して第1の感光膜パターンを形成する段階と、
(3)前記第1の感光膜パターンにO2プラズマを処理する段階と、
(4)前記結果物の上部に第2の感光膜を形成し、第2の露光マスクを利用して第1の感光膜パターンと重なり合わない第2の感光膜パターンを形成する段階と、
(5)前記第1及び第2の感光膜パターンを食刻マスクに利用して前記反射防止膜を食刻した後、前記第1及び第2の感光膜パターンを除去して反射防止膜パターンを形成する段階と、
(6)前記反射防止膜パターンを食刻マスクに前記被食刻層を食刻して被食刻層パターンを形成する段階とを含む半導体素子の製造方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20050132110 | 2005-12-28 | ||
KR10-2005-0132110 | 2005-12-28 | ||
KR1020060069760A KR100811431B1 (ko) | 2005-12-28 | 2006-07-25 | 반도체 소자의 제조 방법 |
KR10-2006-0069760 | 2006-07-25 |
Publications (2)
Publication Number | Publication Date |
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JP2007180489A JP2007180489A (ja) | 2007-07-12 |
JP4921898B2 true JP4921898B2 (ja) | 2012-04-25 |
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Family Applications (1)
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JP2006241537A Expired - Fee Related JP4921898B2 (ja) | 2005-12-28 | 2006-09-06 | 半導体素子の製造方法 |
Country Status (5)
Country | Link |
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US (1) | US7655568B2 (ja) |
JP (1) | JP4921898B2 (ja) |
KR (1) | KR100811431B1 (ja) |
CN (1) | CN100477080C (ja) |
TW (1) | TW200725695A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007180490A (ja) * | 2005-12-28 | 2007-07-12 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
Families Citing this family (17)
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US7959818B2 (en) * | 2006-09-12 | 2011-06-14 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
KR100798738B1 (ko) * | 2006-09-28 | 2008-01-29 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 제조 방법 |
KR100912959B1 (ko) * | 2006-11-09 | 2009-08-20 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 제조 방법 |
KR100819673B1 (ko) * | 2006-12-22 | 2008-04-04 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 패턴 형성 방법 |
KR100876816B1 (ko) * | 2007-06-29 | 2009-01-07 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성 방법 |
US8124323B2 (en) * | 2007-09-25 | 2012-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for patterning a photosensitive layer |
US7935477B2 (en) * | 2007-11-30 | 2011-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double patterning strategy for contact hole and trench |
JP5192795B2 (ja) * | 2007-12-06 | 2013-05-08 | 株式会社日立ハイテクノロジーズ | 電子ビーム測定装置 |
JP2009283674A (ja) * | 2008-05-22 | 2009-12-03 | Elpida Memory Inc | 半導体装置の製造方法 |
US8293460B2 (en) * | 2008-06-16 | 2012-10-23 | Applied Materials, Inc. | Double exposure patterning with carbonaceous hardmask |
KR101523951B1 (ko) * | 2008-10-09 | 2015-06-02 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
US8551689B2 (en) * | 2010-05-27 | 2013-10-08 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices using photolithography |
KR101658492B1 (ko) * | 2010-08-13 | 2016-09-21 | 삼성전자주식회사 | 미세 패턴의 형성 방법 및 이를 이용한 반도체 소자의 제조 방법 |
KR101215645B1 (ko) * | 2010-12-09 | 2012-12-26 | 에스케이하이닉스 주식회사 | 오버레이 버니어 마스크패턴과 그 형성방법 및 오버레이 버니어 패턴을 포함하는 반도체소자와 그 형성방법 |
CN103309165A (zh) * | 2012-03-09 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
KR101926418B1 (ko) * | 2012-05-16 | 2018-12-10 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR102270137B1 (ko) * | 2017-11-29 | 2021-06-28 | 삼성에스디아이 주식회사 | 패턴 형성 방법 |
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-
2006
- 2006-07-25 KR KR1020060069760A patent/KR100811431B1/ko not_active IP Right Cessation
- 2006-08-28 TW TW095131538A patent/TW200725695A/zh unknown
- 2006-08-29 US US11/468,084 patent/US7655568B2/en not_active Expired - Fee Related
- 2006-09-06 JP JP2006241537A patent/JP4921898B2/ja not_active Expired - Fee Related
- 2006-09-11 CN CNB2006101515481A patent/CN100477080C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007180490A (ja) * | 2005-12-28 | 2007-07-12 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
Also Published As
Publication number | Publication date |
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TW200725695A (en) | 2007-07-01 |
US7655568B2 (en) | 2010-02-02 |
KR100811431B1 (ko) | 2008-03-07 |
US20070148983A1 (en) | 2007-06-28 |
CN1992155A (zh) | 2007-07-04 |
KR20070070036A (ko) | 2007-07-03 |
JP2007180489A (ja) | 2007-07-12 |
CN100477080C (zh) | 2009-04-08 |
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