TW200725695A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
TW200725695A
TW200725695A TW095131538A TW95131538A TW200725695A TW 200725695 A TW200725695 A TW 200725695A TW 095131538 A TW095131538 A TW 095131538A TW 95131538 A TW95131538 A TW 95131538A TW 200725695 A TW200725695 A TW 200725695A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
manufacturing semiconductor
manufacturing
disclosed
forming
Prior art date
Application number
TW095131538A
Other languages
English (en)
Inventor
Sung-Koo Lee
Jae-Chang Jung
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200725695A publication Critical patent/TW200725695A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Materials For Photolithography (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Formation Of Insulating Films (AREA)
TW095131538A 2005-12-28 2006-08-28 Method for manufacturing semiconductor device TW200725695A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050132110 2005-12-28
KR1020060069760A KR100811431B1 (ko) 2005-12-28 2006-07-25 반도체 소자의 제조 방법

Publications (1)

Publication Number Publication Date
TW200725695A true TW200725695A (en) 2007-07-01

Family

ID=38214314

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095131538A TW200725695A (en) 2005-12-28 2006-08-28 Method for manufacturing semiconductor device

Country Status (5)

Country Link
US (1) US7655568B2 (zh)
JP (1) JP4921898B2 (zh)
KR (1) KR100811431B1 (zh)
CN (1) CN100477080C (zh)
TW (1) TW200725695A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424469B (zh) * 2007-11-30 2014-01-21 Taiwan Semiconductor Mfg 微影雙重圖形成形方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7807336B2 (en) * 2005-12-28 2010-10-05 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
US7959818B2 (en) * 2006-09-12 2011-06-14 Hynix Semiconductor Inc. Method for forming a fine pattern of a semiconductor device
KR100798738B1 (ko) * 2006-09-28 2008-01-29 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 제조 방법
KR100912959B1 (ko) * 2006-11-09 2009-08-20 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 제조 방법
KR100819673B1 (ko) * 2006-12-22 2008-04-04 주식회사 하이닉스반도체 반도체 소자 및 그의 패턴 형성 방법
KR100876816B1 (ko) * 2007-06-29 2009-01-07 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
US8124323B2 (en) 2007-09-25 2012-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for patterning a photosensitive layer
JP5192795B2 (ja) * 2007-12-06 2013-05-08 株式会社日立ハイテクノロジーズ 電子ビーム測定装置
JP2009283674A (ja) * 2008-05-22 2009-12-03 Elpida Memory Inc 半導体装置の製造方法
US8293460B2 (en) * 2008-06-16 2012-10-23 Applied Materials, Inc. Double exposure patterning with carbonaceous hardmask
KR101523951B1 (ko) * 2008-10-09 2015-06-02 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
US8551689B2 (en) * 2010-05-27 2013-10-08 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices using photolithography
KR101658492B1 (ko) * 2010-08-13 2016-09-21 삼성전자주식회사 미세 패턴의 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
KR101215645B1 (ko) * 2010-12-09 2012-12-26 에스케이하이닉스 주식회사 오버레이 버니어 마스크패턴과 그 형성방법 및 오버레이 버니어 패턴을 포함하는 반도체소자와 그 형성방법
CN103309165A (zh) * 2012-03-09 2013-09-18 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
KR101926418B1 (ko) * 2012-05-16 2018-12-10 삼성전자주식회사 반도체 소자의 제조 방법
KR102270137B1 (ko) * 2017-11-29 2021-06-28 삼성에스디아이 주식회사 패턴 형성 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5186788A (en) * 1987-07-23 1993-02-16 Matsushita Electric Industrial Co., Ltd. Fine pattern forming method
JPH04176123A (ja) * 1990-11-08 1992-06-23 Nec Corp 半導体装置の製造方法
US5667940A (en) 1994-05-11 1997-09-16 United Microelectronics Corporation Process for creating high density integrated circuits utilizing double coating photoresist mask
KR100206597B1 (ko) * 1995-12-29 1999-07-01 김영환 반도체 장치의 미세패턴 제조방법
KR19980028362A (ko) * 1996-10-22 1998-07-15 김영환 반도체소자의 미세 패턴 제조방법
KR19990061090A (ko) * 1997-12-31 1999-07-26 김영환 다층 레지스트 공정용 포토레지스트와 이를 이용한반도체 소자의 미세패턴 제조방법
JP2000077317A (ja) * 1998-09-03 2000-03-14 Sony Corp レジストパターン形成方法
US6140023A (en) * 1998-12-01 2000-10-31 Advanced Micro Devices, Inc. Method for transferring patterns created by lithography
US6586339B1 (en) 1999-10-28 2003-07-01 Advanced Micro Devices, Inc. Silicon barrier layer to prevent resist poisoning
US6534414B1 (en) 2000-06-14 2003-03-18 Integrated Device Technology, Inc. Dual-mask etch of dual-poly gate in CMOS processing
TWI245774B (en) * 2001-03-01 2005-12-21 Shinetsu Chemical Co Silicon-containing polymer, resist composition and patterning process
JP4342767B2 (ja) * 2002-04-23 2009-10-14 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
DE10223997A1 (de) * 2002-05-29 2003-12-18 Infineon Technologies Ag Verfahren zur Herstellung von Fotomasken für die Strukturierung von Halbleitersubstraten durch optische Lithografie
JP2004153073A (ja) 2002-10-31 2004-05-27 Renesas Technology Corp 半導体装置の製造方法
KR100971976B1 (ko) 2003-07-24 2010-07-22 주식회사 포스코 아연도금 강판 스트립의 표면조도 균일화 장치
KR100510558B1 (ko) * 2003-12-13 2005-08-26 삼성전자주식회사 패턴 형성 방법
KR100598105B1 (ko) * 2004-06-17 2006-07-07 삼성전자주식회사 반도체 패턴 형성 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424469B (zh) * 2007-11-30 2014-01-21 Taiwan Semiconductor Mfg 微影雙重圖形成形方法

Also Published As

Publication number Publication date
JP4921898B2 (ja) 2012-04-25
CN100477080C (zh) 2009-04-08
KR20070070036A (ko) 2007-07-03
CN1992155A (zh) 2007-07-04
JP2007180489A (ja) 2007-07-12
US7655568B2 (en) 2010-02-02
KR100811431B1 (ko) 2008-03-07
US20070148983A1 (en) 2007-06-28

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