JP5174335B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- JP5174335B2 JP5174335B2 JP2006243018A JP2006243018A JP5174335B2 JP 5174335 B2 JP5174335 B2 JP 5174335B2 JP 2006243018 A JP2006243018 A JP 2006243018A JP 2006243018 A JP2006243018 A JP 2006243018A JP 5174335 B2 JP5174335 B2 JP 5174335B2
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- pattern
- antireflection film
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- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 238000005530 etching Methods 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000006117 anti-reflective coating Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 239000000203 mixture Substances 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000008199 coating composition Substances 0.000 description 4
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000002835 absorbance Methods 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003431 cross linking reagent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
- Y10S430/151—Matting or other surface reflectivity altering material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Materials For Photolithography (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
(1)半導体基板の上部に被食刻層、ハードマスク層、シリコンを含む第1の反射防止膜及び第1の感光膜を順次形成する段階と、
(2)前記第1の感光膜を第1の露光マスクを利用して露光した後現像して第1の感光膜パターンを形成し、前記第1の感光膜パターンを食刻マスクに前記第1の反射防止膜を食刻して第1の反射防止膜パターンを形成する段階と、
(3)前記第1の反射防止膜パターンにO2プラズマを処理する段階と、
(4)前記結果物の上部に第2の反射防止膜及び第2の感光膜を順次形成し、第2の露光マスクを利用して第1の感光膜パターンと重なり合わない第2の感光膜パターンを形成する段階と、
(5)前記第2の感光膜パターンを食刻マスクに第2の反射防止膜を食刻した後、前記第2の感光膜パターンを除去して第2の反射防止膜パターンを形成する段階と、
(6)前記第1及び第2の反射防止膜パターンを食刻マスクに前記ハードマスク層を食刻してハードマスクパターンを形成する段階と、
(7)前記ハードマスクパターンを食刻マスクに前記被食刻層を食刻して被食刻層パターンを形成する段階とを含む。
12、120 被食刻層
13、17、130 ハードマスク層
14、18、140、180 反射防止膜
15、19、150、190 感光膜
16、160、20、200 露光マスク
12´、120´ 被食刻層パターン
13´、17´、130´ ハードマスクパターン
14´、18´、140´、180´ 反射防止膜パターン
15´、19´、150´、190´ 感光膜パターン
145 O2プラズマ処理されたSiO2含有の反射防止膜パターン
Claims (6)
- (1)半導体基板の上部に被食刻層、ハードマスク層、シリコンを含む第1の反射防止膜及び第1の感光膜を順次形成する段階と、
(2)前記第1の感光膜を第1の露光マスクを利用して露光した後現像して第1の感光膜パターンを形成し、前記第1の感光膜パターンをマスクに前記第1の反射防止膜を食刻して第1の反射防止膜パターンを形成する段階と、
(3)前記第1の反射防止膜パターンにO2プラズマを処理する段階と、
(4)前記結果物の上部に第2の反射防止膜及び第2の感光膜を順次形成し、第2の露光マスクを利用して第1の感光膜パターンと重なり合わない第2の感光膜パターンを形成する段階と、
(5)前記第2の感光膜パターンを食刻マスクに第2の反射防止膜を食刻した後、前記第2の感光膜パターンを除去して第2の反射防止膜パターンを形成する段階と、
(6)前記第1及び第2の反射防止膜パターンを食刻マスクに前記ハードマスク層を食刻してハードマスクパターンを形成する段階と、
(7)前記ハードマスクパターンを食刻マスクに前記被食刻層を食刻して被食刻層パターンを形成する段階とを含む半導体素子の製造方法。 - 前記第1の反射防止膜は30〜40重量%含量のシリコンを含むことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第2の反射防止膜は前記第1の反射防止膜と同一であるか、相違する物質で形成することを特徴とする請求項1または2に記載の半導体素子の製造方法。
- 前記露光源はArF(193nm)、KrF(248nm)、EUV、VUV(157nm)、E−ビーム、X線及びイオンビームでなる群から選択されることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記ハードマスク層は、被食刻層の上部に非晶質炭素層及び無機系ハードマスク層の二重層で形成されることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第1の反射防止膜パターン及び第2の反射防止膜パターンは互いに交互に形成されることを特徴とする請求項1に記載の半導体素子の製造方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20050132109 | 2005-12-28 | ||
KR10-2005-0132109 | 2005-12-28 | ||
KR10-2006-069759 | 2006-07-25 | ||
KR1020060069759A KR100772801B1 (ko) | 2005-12-28 | 2006-07-25 | 반도체 소자의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
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JP2007180490A JP2007180490A (ja) | 2007-07-12 |
JP5174335B2 true JP5174335B2 (ja) | 2013-04-03 |
Family
ID=38194250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006243018A Expired - Fee Related JP5174335B2 (ja) | 2005-12-28 | 2006-09-07 | 半導体素子の製造方法 |
Country Status (2)
Country | Link |
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US (1) | US7807336B2 (ja) |
JP (1) | JP5174335B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100876816B1 (ko) * | 2007-06-29 | 2009-01-07 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성 방법 |
JP5096860B2 (ja) * | 2007-10-04 | 2012-12-12 | パナソニック株式会社 | パターン形成方法 |
JP2009283863A (ja) * | 2008-05-26 | 2009-12-03 | Renesas Technology Corp | 半導体装置の製造方法 |
KR102061919B1 (ko) | 2011-11-21 | 2020-01-02 | 브레우어 사이언스 인코포레이션 | Euv 리소그래피용 보조층 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2919004B2 (ja) * | 1990-07-12 | 1999-07-12 | 沖電気工業株式会社 | パターン形成方法 |
JP2803999B2 (ja) * | 1993-11-10 | 1998-09-24 | 現代電子産業株式会社 | 半導体装置の微細パターン製造法 |
KR100223325B1 (ko) * | 1995-12-15 | 1999-10-15 | 김영환 | 반도체 장치의 미세패턴 제조방법 |
KR19980028362A (ko) * | 1996-10-22 | 1998-07-15 | 김영환 | 반도체소자의 미세 패턴 제조방법 |
US6248168B1 (en) | 1997-12-15 | 2001-06-19 | Tokyo Electron Limited | Spin coating apparatus including aging unit and solvent replacement unit |
JP2000031118A (ja) * | 1998-07-08 | 2000-01-28 | Toshiba Corp | パターン形成方法 |
US6475922B1 (en) * | 2000-04-25 | 2002-11-05 | Koninklijke Philips Electronics N.V. | Hard mask process to control etch profiles in a gate stack |
US6534414B1 (en) * | 2000-06-14 | 2003-03-18 | Integrated Device Technology, Inc. | Dual-mask etch of dual-poly gate in CMOS processing |
KR100520186B1 (ko) * | 2000-06-21 | 2005-10-10 | 주식회사 하이닉스반도체 | 부분적으로 가교화된 2층 포토레지스트용 중합체 |
JP4342767B2 (ja) * | 2002-04-23 | 2009-10-14 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
DE10223997A1 (de) * | 2002-05-29 | 2003-12-18 | Infineon Technologies Ag | Verfahren zur Herstellung von Fotomasken für die Strukturierung von Halbleitersubstraten durch optische Lithografie |
JP2004153073A (ja) * | 2002-10-31 | 2004-05-27 | Renesas Technology Corp | 半導体装置の製造方法 |
ATE372824T1 (de) | 2002-12-06 | 2007-09-15 | Mixpac Systems Ag | Statischer mischer und verfahren |
JP4225544B2 (ja) * | 2003-06-25 | 2009-02-18 | 学校法人東京電機大学 | 感光性材料の積層構造および微細パターン形成方法 |
KR100510558B1 (ko) * | 2003-12-13 | 2005-08-26 | 삼성전자주식회사 | 패턴 형성 방법 |
KR100598105B1 (ko) * | 2004-06-17 | 2006-07-07 | 삼성전자주식회사 | 반도체 패턴 형성 방법 |
WO2007041748A1 (en) | 2005-10-10 | 2007-04-19 | Silverbrook Research Pty Ltd | Method of fabricating suspended beam in a mems process |
KR100811431B1 (ko) * | 2005-12-28 | 2008-03-07 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
-
2006
- 2006-08-29 US US11/468,080 patent/US7807336B2/en not_active Expired - Fee Related
- 2006-09-07 JP JP2006243018A patent/JP5174335B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2007180490A (ja) | 2007-07-12 |
US20070148602A1 (en) | 2007-06-28 |
US7807336B2 (en) | 2010-10-05 |
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