JP4912886B2 - モノリシック集積型エンハンスメントモードおよびデプリーションモードfetおよびその製造方法 - Google Patents
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- H01L21/8232—Field-effect technology
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- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
Description
2 D(デプリーション)モードFET
3,103 E(エンハンスメント)モードFET
5,105,705 多層構造
6 アイソレーション領域
12 半導体基板
14 バッファ層
16 チャネルおよびスペーサ層
18 Eモード障壁層
20 Eモードエッチストップ層
22 Dモード障壁層
24 Dモードエッチストップ層
26 幅広凹み遷移層
28 オームコンタクト層
30,34 金属ゲートコンタクト
38 金属ソースコンタクト
40 金属ドレーンコンタクト
107 障壁層
109 エッチストップ層
111 Eモードゲートコンタクト
113 非晶質化領域
301,307 誘電体層
303,309,313,317 フォトレジストマスク
305,315,319 開孔
Claims (10)
- 集積回路であって、
多層構造の中にデプリーションモード(Dモード)電界効果トランジスタ(FET)およびエンハンスメントモード(Eモード)FETを含み、
前記多層構造が、半導体基板、すなわちチャネル層とその層を覆って形成した障壁層とその障壁層を覆って形成した第1の層とを含む複数のエピタキシャル層であって前記DモードFETおよび前記EモードFETに共通な複数のエピタキシャル層をオーバーレイした半導体基板を含み、
前記DモードFETおよびEモードFETの各々がソースコンタクト、ドレーンコンタクトおよびゲートコンタクトを含み、
前記DモードFETおよびEモードFETのそれぞれの前記ソースコンタクトおよびドレーンコンタクトが前記第1の層にあり、前記DモードFETおよびEモードFETの各々の前記ゲートコンタクトが前記障壁層に接続されており、前記EモードFETのゲートコンタクトが、そのゲートコンタクトの第1の金属層が前記障壁層の半導体材料に拡散して固体非晶質化領域を形成する形で構成されている集積回路。 - 前記固体非晶質化領域が、白金、イリジウム、パラジウム、ニッケル、コバルト、クロム、ルテニウム、オスミウム、ロジウムおよびレニウムの少なくとも一つを含む少なくとも一つの配合物を含む請求項1記載の集積回路。
- 前記固体非晶質化領域が複数の配合物、すなわち白金、イリジウム、パラジウム、ニッケル、コバルト、クロム、ルテニウム、オスミウム、ロジウムおよびレニウムのうちの一つを含む少なくとも一つの配合物を含む複数の配合物を含む請求項1記載の集積回路。
- 前記多層構造が前記障壁層と前記第1の層との間に少なくとも第2のエピタキシャル層をさらに含む請求項1記載の集積回路。
- 前記障壁層が第1の導電型の層であり、
少なくとも前記Eモードゲートコンタクトの下の前記障壁層に形成した第2の導電型のイオン打込み領域をさらに含み、
前記固体非晶質化領域が前記イオン打込み領域の中にある請求項1記載の集積回路。 - DモードFETおよびEモードFETを含む集積回路を製造する方法であって、
前記DモードFETおよび前記EモードFETに共通なチャネル層およびそのチャネル層を覆って形成した障壁層を含む複数のエピタキシャル層をオーバーレイした半導体多層基板を準備する過程と、
前記DモードFETおよびEモードFETのそれぞれのソースコンタクトおよびドレーンコンタクトを前記多層基板の前記エピタキシャル層の一つに形成する過程と、
前記DモードFETのためのゲート凹みおよび前記EモードFETのためのゲート凹みを、前記多層構造の中に、前記障壁層の表面が前記Dモードゲート凹みおよび前記Eモードゲート凹みの両方の底部で露出する形で形成する過程と、
前記Dモードゲート凹みおよび前記Eモードゲート凹みの中の前記障壁層の露出した表面に、DモードゲートコンタクトおよびEモードゲートを形成するように、複数の金属層を堆積させる過程と
を含み、
前記Eモードゲート凹みの中に堆積した第1の金属層が、固体非晶質化領域を形成するように前記障壁層の半導体材料に拡散し、
前記Dモードゲート凹みの中の前記障壁層に接触する形で堆積した第1の金属層が、前記Eモードゲート凹みの中の前記障壁層に接触する形で堆積した第1の金属層とは異なる
方法。 - 前記Eモードゲート凹みの中の前記障壁層に接触する形で堆積した前記第1の金属層を前記障壁層の中に全面的に非晶質化させる過程をさらに含む請求項6記載の方法。
- 前記Eモードゲート凹みの中の前記障壁層の前記露出した表面に接触する形で堆積した前記第1の金属層が、白金、イリジウム、パラジウム、ニッケル、コバルト、クロム、ルテニウム、オスミウム、ロジウムおよびレニウムの一つを含み、前記Dモードゲート凹みの中の前記障壁層と接触する形で堆積した前記第1の金属層がイリジウム、パラジウム、ニッケル、コバルト、クロム、ルテニウム、オスミウム、ロジウムおよびレニウムとは異なる請求項7記載の方法。
- 前記障壁層が第1の導電型の層であり、
少なくとも前記Eモードゲートコンタクトの下の前記障壁層の中に第2の導電型のイオン打込み領域を形成する過程をさらに含み、
前記Eモードゲートコンタクトの前記第1の金属層が前記イオン打込み領域の中に非晶質化する請求項7記載の方法。 - 前記Eモードゲート凹みの中の前記障壁層の前記露出した表面に接触する形で堆積した前記第1の金属層が白金、イリジウム、パラジウム、ニッケル、コバルト、クロム、ルテニウム、オスミウム、ロジウムおよびレニウムの一つを含み、
前記Eモードゲート凹みの中の前記第1の金属層の上に、白金、イリジウム、パラジウム、ニッケル、コバルト、クロム、ルテニウム、オスミウム、ロジウムおよびレニウムのうちの前記第1の金属層とは異なる一つから成る第2の金属層を堆積させる過程と、
前記Eモードゲートコンタクトの前記第2の金属層を前記障壁層の中に非晶質化させる過程と
をさらに含む請求項6記載の方法。
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US10/721,437 | 2003-11-24 | ||
US10/721,437 US7449728B2 (en) | 2003-11-24 | 2003-11-24 | Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same |
PCT/US2004/035609 WO2005055322A1 (en) | 2003-11-24 | 2004-10-26 | Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same |
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JP2007512705A JP2007512705A (ja) | 2007-05-17 |
JP4912886B2 true JP4912886B2 (ja) | 2012-04-11 |
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US (2) | US7449728B2 (ja) |
JP (1) | JP4912886B2 (ja) |
KR (1) | KR20070003803A (ja) |
FR (1) | FR2865851B1 (ja) |
TW (1) | TWI363423B (ja) |
WO (1) | WO2005055322A1 (ja) |
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FR2865851B1 (fr) | 2006-07-21 |
FR2865851A1 (fr) | 2005-08-05 |
TWI363423B (en) | 2012-05-01 |
US20050110054A1 (en) | 2005-05-26 |
US20060027840A1 (en) | 2006-02-09 |
JP2007512705A (ja) | 2007-05-17 |
US7449728B2 (en) | 2008-11-11 |
US7655546B2 (en) | 2010-02-02 |
KR20070003803A (ko) | 2007-01-05 |
WO2005055322A1 (en) | 2005-06-16 |
TW200520227A (en) | 2005-06-16 |
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