CN116031298A - 高电子迁移率晶体管元件及其制造方法 - Google Patents

高电子迁移率晶体管元件及其制造方法 Download PDF

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CN116031298A
CN116031298A CN202111245701.8A CN202111245701A CN116031298A CN 116031298 A CN116031298 A CN 116031298A CN 202111245701 A CN202111245701 A CN 202111245701A CN 116031298 A CN116031298 A CN 116031298A
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forming
electron mobility
high electron
mobility transistor
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李皞明
罗大刚
陈再富
谢守伟
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United Microelectronics Corp
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Abstract

本发明公开一种高电子迁移率晶体管元件及其制造方法，其中该高电子迁移率晶体管元件包括基底、沟道层、阻障层、P型氮化镓间隙壁、栅极、源极与漏极。沟道层设置在基底上。阻障层设置在沟道层上，且具有突出部。P型氮化镓间隙壁设置在突出部的侧壁上。栅极设置在突出部与P型氮化镓间隙壁上。源极与漏极设置在栅极两侧。

Description

高电子迁移率晶体管元件及其制造方法
技术领域
本发明涉及一种半导体元件及其制造方法，且特别是涉及一种高电子迁移率晶体管(high electron mobility transistor device，HEMT)元件及其制造方法。
背景技术
目前，在对高电子迁移率晶体管进行操作之后，负电荷会被捕捉在阻障层的表面，而产生电流崩塌(current collapse)现象。由于电流崩塌现象会增加高电子迁移率晶体管的沟道电阻，因此会降低高电子迁移率晶体管的跨导(transconductance，gm)。
发明内容
本发明提供一种高电子迁移率晶体管元件及其制造方法，其可提升高电子迁移率晶体管的跨导。
本发明提出一种高电子迁移率晶体管元件，包括基底、沟道层、阻障层、P型氮化镓间隙壁(p-type GaN spacer)、栅极、源极与漏极。沟道层设置在基底上。阻障层设置在沟道层上，且具有突出部。P型氮化镓间隙壁设置在突出部的侧壁上。栅极设置在突出部与P型氮化镓间隙壁上。源极与漏极设置在栅极两侧。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，栅极可直接接触突出部与P型氮化镓间隙壁。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，P型氮化镓间隙壁可位于部分栅极与部分阻障层之间。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，沟道层的材料例如是氮化镓(GaN)。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，阻障层的材料例如是氮化铝镓(AlGaN)。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，栅极的材料可不同于源极的材料与漏极的材料。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，栅极的功函数(work function)可不同于源极的功函数与漏极的功函数。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，更可包括缓冲层。缓冲层设置在沟道层与基底之间。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件中，高电子迁移率晶体管元件例如是耗尽型高电子迁移率晶体管(depletion-mode(D-mode)HEMT)元件。
本发明提出一种高电子迁移率晶体管元件的制造方法，包括以下步骤。提供基底。在基底上形成沟道层。在沟道层上形成阻障层，其中阻障层具有突出部。在突出部的侧壁上形成P型氮化镓间隙壁。在突出部与P型氮化镓间隙壁上形成栅极。在栅极两侧形成源极与漏极。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，沟道层的形成方法例如是外延成长法(epitaxial growth method)。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，阻障层的形成方法可包括以下步骤。形成阻障材料层。对阻障材料层进行图案化，而形成阻障层。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，阻障材料层的形成方法例如是外延成长法。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，P型氮化镓间隙壁的形成方法可包括以下步骤。形成P型氮化镓材料层。对P型氮化镓材料层进行回蚀刻制作工艺(etch-back process)，而形成P型氮化镓间隙壁。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，P型氮化镓材料层的形成方法例如是外延成长法。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，回蚀刻制作工艺例如是干式蚀刻制作工艺。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，栅极的形成方法可包括以下步骤。在阻障层与P型氮化镓间隙壁上形成第一介电层。在第一介电层中形成第一开口。第一开口可暴露出突出部与P型氮化镓间隙壁。在第一介电层上且在第一开口中形成第一导电层。对第一导电层进行图案化，而形成栅极。栅极可位于第一开口中。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，源极与漏极的形成方法可包括以下步骤。在第一介电层与栅极上形成第二介电层。在第二介电层与第一介电层中形成第二开口与第三开口。在第二介电层上且在第二开口与第三开口中形成第二导电层。对第二导电层进行图案化，而形成源极与漏极。源极可位于第二开口中，且漏极可位于第三开口中。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，还可包括以下步骤。在形成沟道层之前，在基底上形成缓冲层。
依照本发明的一实施例所述，在上述高电子迁移率晶体管元件的制造方法中，缓冲层的形成方法例如是外延成长法。
基于上述，在本发明所提出的高电子迁移率晶体管元件及其制造方法中，P型氮化镓间隙壁位于阻障层的突出部的侧壁上，且栅极位于突出部与P型氮化镓间隙壁上。因此，可通过在恢复时段(recovery time period)的恢复操作(recovery operation)来产生空穴注入(hole injection)的效果。如此一来，可利用空穴来中和(neutralize)或补偿(compensate)被捕捉在阻障层的表面上的负电荷，由此可解决电流崩塌的问题并且可提升高电子迁移率晶体管的跨导。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1A至图1L为本发明一实施例的高电子迁移率晶体管元件的制造流程剖面图
图2为本发明一实施例的高电子迁移率晶体管元件的操作时段(operation timeperiod)的电压图。
具体实施方式
图1A至图1L为根据本发明一实施例的高电子迁移率晶体管元件的制造流程剖面图。图2为本发明一实施例的高电子迁移率晶体管元件的操作时段的电压图。
请参照图1A，提供基底100。基底100可为半导体基底，如硅基底。接着，可在基底100上形成缓冲层102。缓冲层102的形成方法例如是外延成长法。然后，在基底100上形成沟道层104。在本实施例中，沟道层104可形成在缓冲层102上。沟道层104的材料例如是氮化镓(GaN)。沟道层104的形成方法例如是外延成长法。接下来，可在沟道层104上形成阻障材料层106。阻障材料层106的材料例如是氮化铝镓(AlGaN)。阻障材料层106的形成方法例如是外延成长法。
请参照图1B，可对阻障材料层106进行图案化，而形成阻障层106a。由此，可在沟道层104上形成阻障层106a，其中阻障层106a具有突出部P。举例来说，可通过光刻制作工艺与蚀刻制作工艺(如，干式蚀刻制作工艺)对阻障材料层106进行图案化。此外，阻障层106a的材料例如是氮化铝镓(AlGaN)。
请参照图1C，可形成P型氮化镓材料层108。P型氮化镓材料层108可具有P型掺质(如，镁(Mg))。P型氮化镓材料层108的形成方法例如是外延成长法。
请参照图1D，可对P型氮化镓材料层108进行回蚀刻制作工艺，而形成P型氮化镓间隙壁108a。由此，可在突出部P的侧壁上形成P型氮化镓间隙壁108a。P型氮化镓间隙壁108a可位于部分栅极112a与部分阻障层106a之间。上述回蚀刻制作工艺例如是干式蚀刻制作工艺。
请参照图1E，可在阻障层106a与P型氮化镓间隙壁108a上形成介电层110。在一些实施例中，介电层110的材料例如是氧化硅，如四乙氧基硅烷(tetraethyl orthosilicate，TEOS)氧化硅，但本发明并不以此为限。介电层110的形成方法例如是化学气相沉积法。
请参照图1F，可在介电层110中形成开口OP1。开口OP1可暴露出突出部P与P型氮化镓间隙壁108a。开口OP1的形成方法例如是通过光刻制作工艺与蚀刻制作工艺(如，干式蚀刻制作工艺)对介电层110进行图案化。
请参照图1G，可在介电层110上且在开口OP1中形成导电层112。导电层112的材料例如是可用于形成肖特基接触(Schottky contact)的材料。举例来说，导电层112的材料可为镍(Ni)、金(Au)或其合金。导电层112的形成方法例如是物理气相沉积法。
请参照图1H，可对导电层112进行图案化，而形成栅极112a。由此，可在突出部P与P型氮化镓间隙壁108a上形成栅极112a。栅极112a可直接接触突出部P与P型氮化镓间隙壁108a。栅极112a可位于开口OP1中。举例来说，可通过光刻制作工艺与蚀刻制作工艺(如，干式蚀刻制作工艺)对导电层112进行图案化。
请参照图1I，可在介电层110与栅极112a上形成介电层114。在一些实施例中，介电层114的材料例如是氧化硅，如四乙氧基硅烷氧化硅，但本发明并不以此为限。介电层114的形成方法例如是化学气相沉积法。
请参照图1J，可在介电层114与介电层110中形成开口OP2与开口OP3。在本实施例中，开口OP2可暴露出阻障层106a的一部分，且开口OP3可暴露出部分阻障层106a的另一部分。开口OP2与开口OP3的形成方法例如是通过光刻制作工艺与蚀刻制作工艺(如，干式蚀刻制作工艺)对介电层114与介电层110进行图案化。
请参照图1K，可在介电层114上且在开口OP2与开口OP3中形成导电层116。导电层116的材料例如是可用于形成欧姆接触(Ohmic contact)的材料。举例来说，导电层116的材料可为钛(Ti)。导电层116的形成方法例如是物理气相沉积法。
请参照图1L，可对导电层116进行图案化，而形成源极116a与漏极116b。由此，可在栅极112a两侧形成源极116a与漏极116b。源极116a可位于开口OP2中，且漏极116b可位于开口OP3中。此外，栅极112a的材料可不同于源极116a的材料与漏极116b的材料。另外，栅极112a的功函数可不同于源极116a的功函数与漏极116b的功函数。
以下，通过图1L来说明上述实施例的高电子迁移率晶体管元件10。此外，虽然高电子迁移率晶体管元件10的形成方法是以上述方法为例进行说明，但本发明并不以此为限。
请参照图1L，高电子迁移率晶体管元件10包括基底100、沟道层104、阻障层106a、P型氮化镓间隙壁108a、栅极112a、源极116a与漏极116b。在一些实施例中，高电子迁移率晶体管元件可为耗尽型高电子迁移率晶体管(D-mode HEMT)元件。沟道层104设置在基底100上。阻障层106a设置在沟道层104上，且具有突出部P。P型氮化镓间隙壁108a设置在突出部P的侧壁上。栅极112a设置在突出部P与P型氮化镓间隙壁108a上。源极116a与漏极116b设置在栅极112a两侧。此外，高电子迁移率晶体管元件10还可包括缓冲层102。缓冲层102设置在沟道层104与基底100之间。另外，高电子迁移率晶体管元件10中的各构件的材料、配置方式、形成方法与功效已于上述实施例进行详尽地描述，于此不再重复说明。
以下，通过图2来说明上述实施例的高电子迁移率晶体管元件10的操作方式。
请参照图2，高电子迁移率晶体管元件10的操作时段T可包括开启时段T1、关闭时段T2与恢复时段T3。在开启时段T1，可在漏极116b施加正电压，可在栅极112a施加正电压，且可在源极116a施加0V(伏)的电压，由此可使得高电子迁移率晶体管元件10处于开启状态。
在关闭时段T2，可在漏极116b施加正电压，可在栅极112a施加负电压，且可在源极116a施加0V的电压，由此可使得高电子迁移率晶体管元件10处于关闭状态。此外，在关闭时段T2，电子会从栅极112a注入阻障层106a，且电子会被捕捉在阻障层106a与介电层110之间的界面。如此一来，负电荷会被捕捉在阻障层的表面，而产生电流崩塌现象。
在恢复时段T3，可在漏极116b施加0V的电压，可在栅极112a施加正电压，且可在源极116a施加0V的电压，由此空穴可从P型氮化镓间隙壁108a注入阻障层106a，以对高电子迁移率晶体管元件10进行恢复操作。如此一来，可利用空穴来中和或补偿被捕捉在阻障层106a与介电层110之间的界面的负电荷，进而解决电流崩塌的问题。
基于上述实施例可知，在高电子迁移率晶体管元件10及其制造方法中，P型氮化镓间隙壁108a位于阻障层106a的突出部P的侧壁上，且栅极112a位于突出部P与P型氮化镓间隙壁108a上。因此，可通过在恢复时段T3的恢复操作来产生空穴注入的效果。如此一来，可利用空穴来中和或补偿被捕捉在阻障层106a的表面上的负电荷，由此可解决电流崩塌的问题并且可提升高电子迁移率晶体管的跨导。
综上所述，在上述实施例的高电子迁移率晶体管元件及其制造方法中，由于P型氮化镓间隙壁位于阻障层的突出部的侧壁上，且栅极位于突出部与P型氮化镓间隙壁上，因此可利用恢复操作所产生的空穴来中和或补偿被捕捉在阻障层的表面上的负电荷，由此可解决电流崩塌的问题并且可提升高电子迁移率晶体管的跨导。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种高电子迁移率晶体管元件，包括：
基底；
沟道层，设置在所述基底上；
阻障层，设置在所述沟道层上，且具有突出部；
P型氮化镓间隙壁，设置在所述突出部的侧壁上；
栅极，设置在所述突出部与所述P型氮化镓间隙壁上；以及
源极与漏极，设置在所述栅极两侧。
2.如权利要求1所述的高电子迁移率晶体管元件，其中所述栅极直接接触所述突出部与所述P型氮化镓间隙壁。
3.如权利要求1所述的高电子迁移率晶体管元件，其中所述P型氮化镓间隙壁位于部分所述栅极与部分所述阻障层之间。
4.如权利要求1所述的高电子迁移率晶体管元件，其中所述沟道层的材料包括氮化镓。
5.如权利要求1所述的高电子迁移率晶体管元件，其中所述阻障层的材料包括氮化铝镓。
6.如权利要求1所述的高电子迁移率晶体管元件，其中所述栅极的材料不同于所述源极的材料与所述漏极的材料。
7.如权利要求1所述的高电子迁移率晶体管元件，其中所述栅极的功函数不同于所述源极的功函数与所述漏极的功函数。
8.如权利要求1所述的高电子迁移率晶体管元件，还包括：
缓冲层，设置在所述沟道层与所述基底之间。
9.如权利要求1所述的高电子迁移率晶体管元件，其中所述高电子迁移率晶体管元件包括耗尽型高电子迁移率晶体管元件。
10.一种高电子迁移率晶体管元件的制造方法，包括：
提供基底；
在所述基底上形成沟道层；
在所述沟道层上形成阻障层，其中所述阻障层具有突出部；
在所述突出部的侧壁上形成P型氮化镓间隙壁；
在所述突出部与所述P型氮化镓间隙壁上形成栅极；以及
在所述栅极两侧形成源极与漏极。
11.如权利要求10所述的高电子迁移率晶体管元件的制造方法，其中所述沟道层的形成方法包括外延成长法。
12.如权利要求10所述的高电子迁移率晶体管元件的制造方法，其中所述阻障层的形成方法包括：
在所述沟道层上形成阻障材料层；以及
对所述阻障材料层进行图案化，而形成所述阻障层。
13.如权利要求10所述的高电子迁移率晶体管元件的制造方法，其中所述阻障材料层的形成方法包括外延成长法。
14.如权利要求10所述的高电子迁移率晶体管元件的制造方法，其中所述P型氮化镓间隙壁的形成方法包括：
形成P型氮化镓材料层；以及
对所述P型氮化镓材料层进行回蚀刻制作工艺，而形成所述P型氮化镓间隙壁。
15.如权利要求14所述的高电子迁移率晶体管元件的制造方法，其中所述P型氮化镓材料层的形成方法包括外延成长法。
16.如权利要求14所述的高电子迁移率晶体管元件的制造方法，其中所述回蚀刻制作工艺包括干式蚀刻制作工艺。
17.如权利要求10所述的高电子迁移率晶体管元件的制造方法，其中所述栅极的形成方法包括：
在所述阻障层与所述P型氮化镓间隙壁上形成第一介电层；
在所述第一介电层中形成第一开口，其中所述第一开口暴露出所述突出部与所述P型氮化镓间隙壁；
在所述第一介电层上且在所述第一开口中形成第一导电层；以及
对所述第一导电层进行图案化，而形成所述栅极，其中所述栅极位于所述第一开口中。
18.如权利要求17所述的高电子迁移率晶体管元件的制造方法，其中所述源极与所述漏极的形成方法包括：
在所述第一介电层与所述栅极上形成第二介电层；
在所述第二介电层与所述第一介电层中形成第二开口与第三开口；
在所述第二介电层上且在所述第二开口与所述第三开口中形成第二导电层；以及
对所述第二导电层进行图案化，而形成所述源极与所述漏极，其中所述源极位于所述第二开口中，且所述漏极位于所述第三开口中。
19.如权利要求10所述的高电子迁移率晶体管元件的制造方法，还包括：
在形成所述沟道层之前，在所述基底上形成缓冲层。
20.如权利要求19所述的高电子迁移率晶体管元件的制造方法，其中所述缓冲层的形成方法包括外延成长法。
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