CN110754001A - 用以改善氮化镓间隔件厚度的均匀度的具有选择性和非选择性蚀刻层的增强型氮化镓晶体管 - Google Patents

用以改善氮化镓间隔件厚度的均匀度的具有选择性和非选择性蚀刻层的增强型氮化镓晶体管 Download PDF

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CN110754001A
CN110754001A CN201880039807.2A CN201880039807A CN110754001A CN 110754001 A CN110754001 A CN 110754001A CN 201880039807 A CN201880039807 A CN 201880039807A CN 110754001 A CN110754001 A CN 110754001A
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曹建军
R·比奇
赵广元
Y·萨里帕里
唐智凯
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Abstract

一种增强型晶体管栅极结构，其包括设置在障壁层上面的GaN间隔件层，在该间隔件层上面的第一pGaN层，设置在该第一p‑GaN层上面的p型含铝III‑V族材料(例如，pAlGaN或pAlInGaN)的蚀刻终止层，与设置在该蚀刻终止层上面厚度大于第一p‑GaN层的第二p‑GaN层。晶圆上源于蚀刻该蚀刻终止层和底下薄pGaN层的任何变化远小于由蚀刻厚pGaN层引起的变化。因此，本发明的方法在障壁层上面留下在晶圆上有最小变化的GaN薄层。

Description

用以改善氮化镓间隔件厚度的均匀度的具有选择性和非选择 性蚀刻层的增强型氮化镓晶体管
技术领域
本发明涉及增强型晶体管结构的领域，例如氮化镓(GaN)晶体管结构。更具体地，本发明涉及具有位于例如pGaN的至少一间隔件层上面的例如pAlGaN或pAlInGaN的蚀刻中止p型含铝III-V族材料层的GaN晶体管栅极结构。
背景技术
由于能够承载大电流和支持高电压，氮化镓(GaN)半导体装置用于功率半导体装置越来越合乎需要。开发这些装置的目标通常在于高功率/高频应用。制造用于这类应用的装置基于有高电子移动率的一般装置结构且不同地被称为异质接面场效晶体管(HFET)、高电子移动率晶体管(HEMT)、或调变掺杂场效晶体管(MODFET)。
GaN HEMT装置包括有至少两个氮化物层的氮化物半导体。形成于半导体或缓冲层上的不同材料造成该等层有不同的带隙。相邻氮化物层的不同材料也造成极化，这有助于形成在这两层的接面附近的导电二维电子气体(2DEG)区，特别是在有较窄带隙层中。
造成极化的氮化物层通常包括AlGaN的障壁层，其邻接GaN层以包括允许电荷流经装置的2DEG。可掺杂或不掺杂此障壁层。由于2DEG区存在于在零栅极偏压的栅极之下，大部分氮化物装置为常开或空乏型装置。如果空乏在零外加栅极偏压的栅极下面的2DEG区，亦即，被移除，则该装置可为增强型装置。增强型装置为常关且由于它们提供的加增安全性以及由于它们比较容易用简单低成本的驱动电路来控制而合乎需要。增强型装置需要施加于栅极的正偏压以便传导电流。
图1示出了惯常的场效晶体管(FET)100的横截面图，它在美国专利申请案公开号：2006/0273347中有更完整的描述。图1的FET 100包括基底101、形成于基底101上的AlN缓冲层102、形成于AlN缓冲层102上的GaN层103、形成于GaN层103上的AlGaN障壁层104。该栅极由形成于AlGaN层104的一部分上面的p型GaN层105与形成于p型GaN层105上的重度掺杂p型GaN层106形成。此装置/FET 100的缺点在于在蚀刻栅极(例如，p型GaN层105)时会部分去除障壁层(AlGaN层104)。需要不要损坏障壁层104，以便在装置上有均匀的障壁层。
图2示出了形成典型增强型GaN HEMT装置200a的惯常步骤的横截面示图，其在美国专利第8,404,508号中有更完整的描述。图2的装置200a包括硅基底11、过渡层12、GaN缓冲材料13、AlGaN障壁材料/层14、p型GaN栅极层15，以及栅极金属17。单一的光掩膜用来图案化并蚀刻栅极金属17和p型GaN栅极层15，而产生图2的结构/装置200a。栅极金属17与p型GaN栅极层15用任何已知技术蚀刻，例如等离子体蚀刻，接着是剥除光阻。可欠蚀刻(under-etch)p型GaN栅极层15而在栅极区外留下约0至约10纳米的栅极材料。也可过蚀刻(over-etch)栅极层15而移除在栅极区外约0至约3纳米的障壁层14。在过蚀刻的情形下，在栅极区外的障壁层14比在栅极区中的薄约0至约3纳米。装置200a有许多缺点：(i)栅极层15厚度有源于EPI成长的不均匀性；(ii)栅极层15在晶圆上的晶圆制造蚀刻速率在晶圆之间和批次之间有不均匀性；(iii)栅极层15厚度的不均匀性和蚀刻速率不均匀性要么导致残余层15材料留在障壁层14上面的数量不均匀，要么过蚀刻且损伤在晶圆上其他位置的障壁层14。再一次，需要有均匀的障壁层14。
图3示出了形成典型增强型氮化镓晶体管装置800的惯常步骤的横截面示图，其在美国专利第8,946,771号中有更完整的描述。图3的装置800包括GaN层202、位于GaN层202上面的AlGaN电子供给层204、位于AlGaN电子供给层204上面的AlN蚀刻终止层206、位于AlN蚀刻终止层206上面的p型GaN层208，以及位于p型GaN层208上面的钛栅极金属210。图案化光阻(P/R)层802形成在栅极金属210上面，以通过覆盖栅极区中的栅极金属210来屏蔽基底中界定GaN装置的栅极结构的区域。如上述，薄AlN层206设置在pGaN层208和AlGaN层204(前置障壁(front barrier))之间。AlN层206用作栅极pGaN蚀刻中止物。这使能pGaN的过蚀刻，以完全蚀刻去除在栅极区外的pGaN。装置800有下列缺点：(a)在pGaN层208下的AlN层206减少临界电压Vth，并且易使装置倾向空乏型(D-模式)；与(b)前置障壁(AlGaN层204)不被GaN帽盖层保护。需要有栅极蚀刻终止层而不减少Vth。在栅极区外的前置障壁上面也最好有GaN帽盖层。
图4示出了如S.Heikman等人在应用物理学杂志2003年第93卷第12期第10114至10118页描述的“AlGaN/GaN和GaN/AlGaN/GaN异构结构中的极化效应(Polarizationeffects in AlGaN/GaN and GaN/AlGaN/GaN heterostructures)”的惯常空乏型HEMT FET400的横截面示图。图4的装置400包括上覆GaN基极401的前置障壁AlGaN 402。薄GaN帽盖层403上叠加前置障壁AlGaN 402，但是只在栅极区中。此配置改善空乏型HEMT FET的性能。不过，装置/FET 400只可操作用于空乏型HEMT FET。需要有具有在栅极区外的GaN帽盖层的增强型晶体管装置。
因此，最好提供一种增强型晶体管结构，其在栅极蚀刻步骤期间最小化或排除底下障壁层之损伤，并且改善GaN间隔件的厚度均匀性。
发明内容
描述下文的本发明的各种具体实施例解决了上述问题及其他问题，其通过提供一种增强型晶体管栅极结构，其包括设置在前置障壁层附近的pAlGaN(或pAlInGaN)的蚀刻终止层，以及在该蚀刻终止层下面及上面有第一及第二层的pGaN(或pAlGaN或pAlInGaN)，与直接设置在该障壁层上面的GaN间隔件层。在该蚀刻终止层上面和下面的层有低于该蚀刻终止层的铝含量。晶圆上源于蚀刻该蚀刻终止层和底下薄pGaN层的任何变化远小于源于蚀刻厚pGaN层的变化。因此，本发明的方法在障壁层上面留下在晶圆上有最小变化的GaN薄层。
在制造晶体管结构期间，该蚀刻终止层在栅极蚀刻步骤期间最小化或消除对障壁层的损坏，并且改善GaN间隔件层厚度的均匀性。
以下描述了增强型晶体管栅极结构具体实施例的附加具体实施例及附加特征以及用于制造该增强型晶体管栅极结构的方法。
附图说明
由以下结合附图，从详细说明可更加明白本公开的特征、目标及优点，其中遍及本文类似的组件用相同的参考字符表示，并且其中：
图1示出了惯常的FET的横截面示图。
图2示出了形成典型的增强型GaN HEMT装置的惯常步骤的横截面示图。
图3示出了形成典型的增强型氮化镓晶体管装置的惯常步骤的横截面示图。
图4示出了惯常的空乏型HEMT FET的横截面示图。
图5示出了根据本发明的第一实施例的、增强型晶体管结构的横截面示图。
图6示出了在用于制造根据本发明的第一实施例的增强型晶体管结构的示例性过程流程中的起始栅极结构的横截面示图。
图7示出了在用于制造根据本发明的第一实施例的增强型晶体管结构的过程中的第一蚀刻的后的栅极结构的横截面示图。
图8示出了在用于制造根据本发明的第一实施例的增强型晶体管结构的过程中的第二蚀刻之后的栅极结构的横截面示图。
图9示出了根据本发明的第二实施例形成的增强型晶体管结构的横截面示图。
图10示出了根据本发明的第三实施例形成的增强型晶体管结构的横截面示图。
图11示出了根据本发明的第四实施例形成的增强型晶体管结构的横截面示图。
图12示出了根据本发明的第五实施例形成的增强型晶体管结构的横截面示图。
图13示出了根据本发明的第六实施例形成的增强型晶体管结构的横截面示图。
优选实施例的详细说明
以下详细说明会参考一些实施例。本详细说明旨在教导本领域技术人员用以实施本教导的优选方面的更多细节而非旨在限制权利要求的范围。因此，在最广义的意思来说，实施本教导并不必须要组合公开于以下详细说明中的特征，反而它只是用来描述本教导的具体代表性示例。应了解，可运用其他的实施例，并且可做出各种结构、逻辑及电气改变。
本发明涉及一种增强型晶体管栅极结构，其主要包括设置在障壁层上面的GaN栅极间隔件层，设置在该栅极间隔件层上面的第一pGaN层(或pAlGaN)，设置在该pGaN层上面的p型含铝III-V族材料(例如，pAlGaN或pAlInGaN)蚀刻终止层，以及设置在该蚀刻终止层上面的第二pGaN层(或pAlGaN)。该p型含铝III-V族材料层在制造晶体管结构期间用作蚀刻中止物，从而最小化或消除底下障壁层在栅极蚀刻步骤期间的损坏，并且改善GaN间隔件层厚度的均匀性。
图5示出了根据本发明的第一实施例形成的增强型晶体管结构500的横截面示图。
参考图5，在优选实施例中，本发明涉及一种增强型晶体管栅极结构500，其包括：AlGaN前置障壁层504；设置在该障壁层上面的GaN间隔件层505，设置在GaN层505上面的p-GaN层506；设置在p-GaN层506上面的pAlGaN蚀刻终止层507，以及设置在pAlGaN蚀刻终止层507上面的pGaN层508。障壁层504可包含一个或更多个障壁层。
在优选实施例中，pAlGaN蚀刻终止层507有0.5纳米至2纳米的厚度。PGaN层506有1纳米至30纳米的厚度，并且比具有20纳米至100纳米的厚度的pGaN层508薄。GaN栅极间隔件层505有1纳米至6纳米的厚度，并且在蚀刻终止层507下面的厚度大于在周围区域中的厚度。
尽管优选地由GaN形成，栅极间隔件层505可包括未掺杂或者是N型或轻度掺杂p型的任何III-V栅极材料。在蚀刻终止层507下面和上面的层506和508优选为pGaN，但是也可为AlGaN或AlInGaN(或任何p型或补偿III-V栅极材料)，并且其铝含量低于pAlGaN蚀刻终止层507(可由含铝的任何p型III-V材料形成)的铝含量。
蚀刻终止层507上文指示为pAlGaN，但是在第二优选实施例，它也可为pAlxInyGazN，在此x+y+z＝1。同样，障壁层504可为AlGaN或AlInGaN。
图6示出了在用于制造根据本发明的第一实施例的增强型晶体管结构500的过程中的起始结构600的横截面示图。如图6所示，该装置的栅极结构通过具有设置在pAlGaN层507上面的pGaN层508而形成，pAlGaN层507设置在pGaN 506上面，pGaN 506设置在GaN间隔件505上面，GaN间隔件505设置在AlGaN前置障壁层504上面。pGaN层506比pGaN层508薄。
图7示出了在用于制造根据本发明的第一实施例的增强型晶体管结构500的过程中的第一蚀刻步骤之后的栅极结构700的横截面示图。栅极屏蔽588位于pGaN层508上面，以及用对pAlGaN层507有选择性的蚀刻配方来执行pGaN层508的第一等离子体栅极蚀刻(即，在栅极/屏蔽区外)。在pGaN层508的过蚀刻期间，蚀刻在pAlGaN层507上中止。使用于此第一蚀刻的等离子体最好为Cl2+O2。
图8示出了在用于制造根据本发明的第一实施例的增强型晶体管结构500的过程中由第二蚀刻步骤800产生的栅极结构800的横截面示图。第二等离子体栅极pGaN蚀刻配方对于pAlGaN没有选择性，并且完全蚀刻在栅极/屏蔽区外的pAlGaN层507和pGaN层506，并且部分蚀刻在栅极/屏蔽区外的GaN间隔件505(即，蚀刻在GaN间隔件505内中止)。使用于第二蚀刻的等离子体是Cl2或SiCl4。本发明的双重蚀刻技术的优点是晶圆上源于蚀刻薄pAlGaN蚀刻终止层和底下薄pGaN层的任何变化远小于蚀刻厚pGaN层。因此，本发明的方法在障壁层504上面留下在晶圆上有最小变化的GaN薄层。
图9示出了根据本发明的第二实施例形成的增强型晶体管结构900的横截面示图。该实施例与第一实施例不同的地方在于，没有GaN间隔件505在栅极区外的细薄部分。可运用第三等离子体栅极蚀刻以选择性地蚀刻移除在栅极区外的GaN间隔件505。
图10示出了根据本发明的第三实施例形成的增强型晶体管结构1000的的横截面示图。该实施例与第一实施例不同的地方在于，没有GaN间隔件505。
图11示出了根据本发明的第四实施例形成的增强型晶体管结构1100的横截面示图。该实施例与第一实施例不同的地方在于，没有pGaN层506。
图12示出了根据本发明的第五实施例形成的增强型晶体管结构1200的横截面示图。该实施例与第一实施例不同的地方在于，pGaN层506和pAlGaN层507在栅极区外延伸，并且GaN间隔件505在栅极区内(即，在pAlGaN层507下面)和周围区域中有均匀的厚度。在此实施例中，没有发生通过p型含铝III-V族材料层507的蚀刻。
图13示出了根据本发明的第六实施例形成的增强型晶体管结构1300的横截面示图。在图13的实施例中，晶体管栅极结构1300包括附加pAlGaN(或pAlInGaN)蚀刻终止层527和547，以及设置在pAlGaN(或pAlInGaN)蚀刻终止层527和547之间的附加pGaN层510。栅极金属560设置在顶端pAlGaN(或pAlInGaN)蚀刻终止层547上面。图13也图示在障壁层504两侧并且与栅极区隔开的欧姆接触金属502、503。GaN通道层501位于障壁层504下面。
如同前面的实施例，pAlGaN(或pAlInGaN)蚀刻终止层507位于AlGaN障壁层附近，其中尺寸a<b，如图13所示。在蚀刻终止层507上面的材料508与在蚀刻终止层507下面的材料506可为pGaN、pAlGaN或pAlInGaN，并且其铝含量(如果存在的话)小于蚀刻终止层507中的铝含量。该栅极可包含一个以上的pAlGaN层。这些pAlGaN层可具有不同的铝含量且可具有不同的厚度。多个蚀刻终止层的优点是，该结构允许各蚀刻中止物有较低的铝含量以实现在蚀刻终止层内的中止。
尽管有图示于图7和图8的上述蚀刻步骤，然而使用经描述为可用于制造上述任何先前技术装置的已知过程或使用其他惯常的过程，(在蚀刻前)沉积或形成图示于图6或以下其他具体实施例及/或任何附图中的各种层(AlGaN障壁层504、GaN间隔件505、pGaN层506、pAlGaN层507及pGaN层508)。对于本文中公开的其他任何层(例如，图14及图15的AlInGaN前置障壁层514，图13的pAlGaN层527、547，图14及图15的pAlInGaN层517，与图15的pAlInGaN层537、557)，可运用类似惯常的沉积或形成过程(即，在蚀刻前)。
在描述于本文的任何实施例中的方法步骤不限于要以特定顺序来执行。再者，在方法实施例中的任一提及的结构可利用在装置实施例中的任一提及的结构。仅可关于装置实施例来详细描述此类结构，但是可应用于方法实施例中中的任一个。
本公开中描述的实施例中的任一特征可与描述于本文的其他实施例的特征结合起来利用，此类结合被视为在本发明的精神和范围内。
特别在本公开中提及的经构想的修改和变体被视为在本发明的精神和范围内。
以上说明及附图被视为仅供图解说明实现描述于本文的特征及优点的特定实施例。可做出特定于过程条件的修改和取代。因此，本发明的实施例不应被视为受限于前面的说明及附图。
更一般而言，即使以上用根据附图的实施例来描述本公开和示例性实施例，然而应当理解，其并不受限于此。而是，对本领域技术人员显而易见的是，可用许多方式来修改所公开的实施例而不脱离本公开的范围。此外，使用于本文的用语和描述只是举例说明的方式提出而没有限制的意思。本领域技术人员会认识到，在如下列权利要求所界定的本公开的精神和范围内可能有许多变体及其等同物，其中应以尽可能广义的意思来了解所有用语，除非另有明示。

Claims (11)

1.一种增强型晶体管栅极结构，包括：
障壁层；
间隔件层，所述间隔件层设置在所述障壁层上面，所述间隔件层包括III-V族材料；
第一层，所述第一层包括设置在所述间隔件层上面的p型或补偿III-V族材料；
蚀刻终止层，所述蚀刻终止层包括设置在所述间隔件层和包括p型或补偿III-V族材料的所述第一层上面的p型含铝III-V族材料；与
第二层，所述第二层包括位于所述蚀刻终止层上面的p型或补偿III-V族材料，包括p型或补偿III-V族材料的所述第二层比包括p型或补偿III-V族材料的所述第一层厚；
其中所述间隔件层在所述蚀刻终止层下面的厚度大于在周围区域的厚度，并且所述间隔件层在所述周围区域中有本质上均匀的厚度。
2.如权利要求1所述的晶体管结构，其中所述间隔件层包括GaN。
3.如权利要求1所述的晶体管结构，其中p型或补偿III-V族材料的所述第一层和所述第二层包括pGaN。
4.如权利要求1所述的晶体管结构，其中所述蚀刻终止层包括pAlGaN或pAlInGaN。
5.如权利要求4的晶体管结构，其中p型或补偿III-V族材料的所述第一层和所述第二层包括pAlGaN或pAlInGaN，并且所述第一层和所述第二层的铝含量小于所述蚀刻终止层的铝含量。
6.如权利要求1所述的晶体管结构，其中所述间隔件层有1纳米至6纳米的厚度，包括p型或补偿III-V族材料的所述第一层有1纳米至30纳米的厚度，所述蚀刻终止层有0.5纳米至2纳米的厚度，并且包括p型或补偿III-V族材料的所述第二层有20纳米至100纳米的厚度。
7.一种在包围晶体管栅极的区域中形成有均匀间隔件层的晶体管的方法，所述方法包括：
提供晶体管栅极结构，包括：
障壁层；
间隔件层，所述间隔件层设置在该障壁层上面，所述间隔件层包括III-V族材料；
第一层，所述第一层包括设置在所述间隔件层上面的p型或补偿III-V族材料；
蚀刻终止层，所述蚀刻终止层包括设置在所述间隔件层和包括p型或补偿III-V族材料的所述第一层上面的p型含铝III-V族材料；以及
第二层，所述第二层包括位于所述蚀刻终止层上面的p型或补偿III-V族材料，包括p型或补偿III-V族材料的所述第二层比包括p型或补偿III-V族材料的所述第一层厚；
在包括p型或补偿III-V族材料的所述第二层的栅极区上面安置屏蔽；
用对于所述蚀刻终止层的所述p型含铝III-V族材料有选择性的蚀刻配方，来执行包括p型或补偿III-V族材料的所述第二层在所述栅极区外的第一蚀刻，致使所述蚀刻在所述蚀刻终止层中止；用对于所述蚀刻终止层的是p型含铝III-V族材料无选择性的蚀刻配方，通过所述屏蔽来执行第二蚀刻，致使所述蚀刻终止层和包括p型或补偿III-V族材料的所述第一层被完全蚀刻在受所述屏蔽覆盖的所述栅极区之外，并且所述间隔件层被部分蚀刻在受所述屏蔽覆盖的所述栅极区之外，使得所述间隔件层在所述蚀刻终止层下面的厚度大于在周围区域的厚度，并且所述间隔件层在所述周围区域中有本质上均匀的厚度。
8.如权利要求7所述的方法，其中所述间隔件层包括GaN。
9.如权利要求8所述的方法，其中p型或补偿III-V族材料的所述第一层和所述第二层包括pGaN，并且所述蚀刻终止层包括pAlGaN或pAlInGaN。
10.如权利要求8所述的方法，其中p型或补偿III-V族材料的所述第一层和所述第二层包括pAlGaN或pAlInGaN，并且所述第一层和所述第二层的铝含量小于所述蚀刻终止层的铝含量。
11.如权利要求7所述的方法，进一步包括设置在包括p型或补偿III-V族材料的所述第二层上面的一附加蚀刻终止层，以及设置在所述附加蚀刻终止层上面的p型或补偿III-V族材料的附加层，其中所述结构在所述障壁层与所述蚀刻终止层之间的厚度小于所述结构在所述蚀刻终止层与所述附加蚀刻终止层之间的厚度，并且其中，对于所述附加蚀刻终止层执行附加蚀刻，导致蚀刻为渐变式。
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