US11081485B2 - Monolithic integrated circuit device having gate-sinking pHEMTs - Google Patents

Monolithic integrated circuit device having gate-sinking pHEMTs Download PDF

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US11081485B2
US11081485B2 US16/661,472 US201916661472A US11081485B2 US 11081485 B2 US11081485 B2 US 11081485B2 US 201916661472 A US201916661472 A US 201916661472A US 11081485 B2 US11081485 B2 US 11081485B2
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pinch
gate
layer
sinking
voltage
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US20210125985A1 (en
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Chia-Ming Chang
Jung-Tao CHUNG
Yan-Cheng Lin
Lung-Yi TSENG
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WIN Semiconductors Corp
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WIN Semiconductors Corp
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Priority to TW109113061A priority patent/TWI748416B/en
Priority to JP2020176638A priority patent/JP7185675B2/en
Priority to EP20203386.6A priority patent/EP3813112A1/en
Priority to CN202011143710.1A priority patent/CN112701118B/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/86—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of Schottky-barrier gate FETs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H01L27/095—
    • H01L29/7786—
    • H01L29/802—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6738—Schottky barrier electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/801—FETs having heterojunction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology

Definitions

  • the present invention relates to a monolithic integrated circuit device composed of more than one pseudomorphic high electron mobility transistors (pHEMTs). More specifically, the invention relates to monolithic integrated gate-sinking pHEMTs having inherently extremely uniform pinch-off or threshold voltage across a wafer and from wafer to wafer.
  • pHEMTs pseudomorphic high electron mobility transistors
  • Gate-sinking or buried-gate technique has been widely adopted to achieve enhancement-mode (E-mode) pseudomorphic high electron mobility transistors (pHEMTs) in which the pinch-off or threshold voltages (pinch-off voltage hereafter) exhibit positive values due to the reduction of the gate-to-channel distance.
  • E-mode enhancement-mode pseudomorphic high electron mobility transistors
  • the application of the gate-sinking technique should include, but not be limited to E-mode pHEMTs.
  • the gate-sinking technique requires careful control of the temperature and duration during the thermal treatment to ensure that the first deposited gate metal diffuses uniformly, consistently, and fully into the Schottky barrier layer. Accordingly, gate-sinking pHEMTs with highly uniform pinch-off voltage across a wafer and from wafer to wafer are mostly demanded in this field.
  • FIG. 1 discloses a conventional monolithic integrated circuit device composed of a depletion-mode (D-mode) pHEMT D 1 and an E-mode pHEMT E 1 .
  • the conventional monolithic integrated circuit device comprises a compound semiconductor substrate 100 and an epitaxial structure 110 .
  • the epitaxial structure 110 grown on the compound semiconductor substrate 100 sequentially comprises from bottom to top a buffer layer 111 , a channel layer 112 , a Schottky layer 113 , a Schottky contact layer 114 , a first etch stop layer 115 , a first conductive layer 116 , a second etch stop layer 117 , a second conductive layer 118 .
  • a source electrode 101 / 103 and a drain electrode 102 / 104 of the D-mode/E-mode pHEMT are formed on the second conductive layer 118 .
  • a gate recess 108 locates between the source electrode 101 and the drain electrode 102 of the D-mode pHEMT with a recess bottom defined by the Schottky contact layer 114 .
  • a gate recess 109 locates between the source electrode 103 and the drain electrode 104 of the E-mode pHEMT with a recess bottom defined by the Schottky layer 113 .
  • a gate electrode 120 of the D-mode pHEMT is deposited on the Schottky contact layer 114 within the gate recess 108 .
  • a gate electrode 130 of the E-mode pHEMT is deposited on the Schottky layer 113 within the gate recess 109 . As shown in FIG.
  • the gate electrodes of the D-mode and E-mode pHEMTs are formed on distinct different semiconductor layers. It indicates that extra photolithography and etch steps are required for both of the D-mode and E-mode pHEMTs in the conventional monolithic integrated circuit device.
  • FIG. 2 discloses another conventional monolithic integrated circuit device composed of a D-mode pHEMT D 1 and an E-mode pHEMT E 1 . As shown in FIG. 2 , both of the D-mode and the E-mode pHEMTs are fabricated using the gate-sinking technique.
  • the monolithic integrated circuit device comprises a compound semiconductor substrate 200 and an epitaxial structure 210 .
  • a gate recess 208 locates between the source electrode 201 and the drain electrode 202 of the D-mode pHEMT with a recess bottom defined by the second Schottky barrier layer 215 .
  • a gate recess 209 locates between the source electrode 203 and the drain electrode 204 of the E-mode pHEMT with a recess bottom defined by the first Schottky barrier layer 213 .
  • the gate electrode 220 of the D-mode pHEMT is deposited on the second Schottky barrier layer 215 within the gate recess 208 .
  • the gate electrode 230 of the E-mode pHEMT is deposited on the first Schottky barrier layer 213 within the gate recess 209 .
  • a gate-sinking region 221 / 231 is beneath the gate electrode 220 / 230 of the D-mode/E-mode pHEMT.
  • the respective gate electrodes of the D-mode pHEMT and the E-mode pHEMT are formed on distinct different Schottky layers. It indicates that extra photolithography and etch steps are required to form the D-mode and E-mode gate recesses 208 , 209 , leading to additional cost and complexity in the pHEMT fabrication process.
  • the etched surfaces of the Schottky barrier layers 213 , 215 may cause defects and surface states, which would degrade the transistor performance and alter the pHEMT pinch-off voltage from the target value.
  • the conventional monolithic integrated circuit device shown in FIG. 2 exhibits serious problem in controlling the respective pinch-off voltages of the D-mode pHEMT as well as the E-mode pHEMT. It is practically impossible to rule the bottom boundary of the gate-sinking region 221 / 231 of the D-mode/E-mode pHEMT perfectly at a specific narrow region within the Schottky barrier layer. This fact can be ascribed to the variations in the thickness of the gate electrodes, thermal treatment temperature, and thermal treatment duration across a wafer and from wafer to wafer. These undesirable effects cause a high degree of variability in transistor pinch-off voltage.
  • a composite Schottky layer structure made of stacked semiconductor layers is implemented.
  • the pinch-off voltage variation of the pHEMT across a wafer and from wafer to wafer can be significantly reduced.
  • the pinch-off voltage of each pHEMT in the monolithic integrated circuit device can be tuned to any (positive or negative) desired value.
  • the present invention provides a monolithic integrated circuit device which is composed of a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT in a multi-layer structure, wherein the multi-layer structure includes a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs, including a buffer layer overlaid by a channel layer overlaid by a Schottky layer overlaid by a first cap layer.
  • the Schottky layer comprises from bottom to top at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, and any two stacked region contact interfaces differ in distance from the semiconductor substrate.
  • Source and drain contacts of the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs are coupled to the first cap layer.
  • the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs each include a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary.
  • the respective gate contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the Schottky layer, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are in contact with the topmost stacked region of the Schottky layer.
  • the low-pinch-off-voltage pHEMT gate-sinking region and the high-pinch-off-voltage pHEMT gate-sinking region are beneath the first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT, respectively.
  • the respective gate-sinking bottom boundaries of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are located within the Schottky layer, wherein the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, and the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located within 10 ⁇ above or below one of the stacked region contact interfaces of the Schottky layer.
  • the present invention provides a monolithic integrated circuit device comprising a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT in a multi-layer structure, wherein the multi-layer structure includes a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs, including a buffer layer overlaid by a channel layer overlaid by a Schottky layer overlaid by a first contact layer overlaid by a first cap layer.
  • the Schottky layer comprises from bottom to top at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, and any two stacked region contact interfaces differ in distance from the semiconductor substrate.
  • the first contact layer is in contact with an upper surface of the topmost stacked region of the Schottky layer, and an uppermost contact interface is provided between the first contact layer and the topmost stacked region of the Schottky layer.
  • Source and drain contacts of the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs are coupled to the first cap layer.
  • the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs each include a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary.
  • the respective gate contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the Schottky layer, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are in contact with the first contact layer.
  • the low-pinch-off-voltage pHEMT gate-sinking region and the high-pinch-off-voltage pHEMT gate-sinking region are beneath the first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT, respectively.
  • the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located within the Schottky layer or within 10 ⁇ above or below the uppermost contact interface.
  • the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located within the Schottky layer and within 10 ⁇ above or below one of the stacked region contact interfaces of the Schottky layer.
  • the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT.
  • the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located within 10 ⁇ above or below one of the stacked region contact interfaces of the Schottky layer.
  • the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located at one of the stacked region contact interfaces of the Schottky layer.
  • the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located at one of the stacked region contact interfaces of the Schottky layer or at the uppermost contact interface.
  • the first contact layer includes at least one of GaAs, AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaPAs, and AlInGaP, and the first contact layer differs in material from the topmost stacked region of the Schottky layer.
  • one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material, wherein the AlGaAs-based semiconductor material includes at least one of AlGaAs, AlGaAsP, and InAlGaAs, and wherein the InGaP-based semiconductor material includes at least one of InGaP, InGaPAs, and AlInGaP.
  • the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT include at least one of molybdenum (Mo), tungsten (W), tungsten-silicide (WSi), titanium (Ti), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), and rhenium (Re).
  • Mo molybdenum
  • W tungsten
  • WSi tungsten-silicide
  • Ti titanium
  • Ir iridium
  • palladium Pd
  • platinum platinum
  • Ni nickel
  • Co cobalt
  • Co chromium
  • Cr ruthenium
  • Ru osmium
  • the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of different materials.
  • the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of the same material.
  • the first gate metal layer of the high-pinch-off-voltage pHEMT is greater in thickness than the first gate metal layer of the low-pinch-off-voltage pHEMT.
  • the plurality of epitaxial semiconductor layers further comprise an etch stop layer and a second cap layer, wherein the etch stop layer is formed on the first cap layer, the second cap layer is formed on the etch stop layer, and the respective source and drain contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the second cap layer.
  • the etch stop layer includes at least one of InGaP, InGaPAs, AlInGaP, and AlAs, wherein the second cap layer is GaAs.
  • the first cap layer is GaAs
  • the channel layer includes at least one of GaAs and InGaAs
  • the buffer layer includes at least one of GaAs and AlGaAs
  • the compound semiconductor substrate is GaAs.
  • FIG. 1 is a cross-sectional side view of a conventional embodiment of a monolithic integrated circuit device.
  • FIG. 2 is another cross-sectional side view of a conventional embodiment of a monolithic integrated circuit device having gate-sinking pHEMTs.
  • FIGS. 3A-3G are cross-sectional side views of embodiments of a monolithic integrated circuit device having gate-sinking pHEMTs according to the present invention.
  • FIGS. 4A-4C are cross-sectional side views of embodiments of a monolithic integrated circuit device having gate-sinking pHEMTs according to the present invention.
  • FIGS. 5-7 are cross-sectional side views of embodiments of a monolithic integrated circuit device having gate-sinking pHEMTs according to the present invention.
  • FIG. 3A is a cross-sectional side view of an embodiment of a monolithic integrated circuit device having gate-sinking pHEMTs.
  • the monolithic integrated circuit device having gate-sinking pHEMTs 1 comprises a low-pinch-off-voltage pHEMT L 1 and a high-pinch-off-voltage pHEMT H 1 in a multi-layer structure 2 .
  • the multi-layer structure 2 includes a semiconductor substrate 10 overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs.
  • the plurality of epitaxial semiconductor layers include a buffer layer 20 overlaid by a channel layer 30 overlaid by a Schottky layer 40 overlaid by a first cap layer 50 .
  • the Schottky layer 40 comprises three stacked regions 42 , 44 , and 46 of semiconductor material from bottom to top, in which each of the two adjacent stacked regions differs in material.
  • a stacked region contact interface 43 is provided between the adjacent stacked regions 42 and 44 .
  • a stacked region contact interface 45 is provided between the adjacent stacked regions 44 and 46 .
  • the stacked region contact interfaces 43 and 45 differ in distance from the semiconductor substrate.
  • the plurality of epitaxial semiconductor layers 2 comprises an isolation region 5 locating between the low-pinch-off-voltage pHEMT L 1 and the high-pinch-off-voltage pHEMT H 1 .
  • Each of the pHEMTs L 1 , H 1 is electrically isolated by the isolation region 5 .
  • the source and drain contacts s 1 and d 1 of the low-pinch-off-voltage pHEMT L 1 are coupled to the first cap layer 50 .
  • the source and drain contacts s 2 , d 2 of the high-pinch-off-voltage pHEMT H 1 are coupled to the first cap layer 50 .
  • the low-pinch-off-voltage pHEMT L 1 contains a gate contact g 1 .
  • the gate contact g 1 comprises a first gate metal layer g 11 .
  • the gate contact g 1 may further comprise a second gate metal layer deposited on the first gate metal layer g 11 .
  • a gate-sinking region g 12 is beneath the first gate metal layer g 11 .
  • the gate-sinking region g 12 has a gate-sinking bottom boundary g 13 .
  • the high-pinch-off-voltage pHEMT H 1 contains a gate contact g 2 .
  • the gate contact g 2 comprises a first gate metal layer g 21 .
  • the gate contact g 2 may further comprise a second gate metal layer deposited on the first gate metal layer g 21 .
  • a gate-sinking region g 22 is beneath the first gate metal layer g 21 .
  • the gate-sinking region g 22 has a gate-sinking bottom boundary g 23 .
  • a gate recess 91 of the low-pinch-off-voltage pHEMT L 1 locates between the source contact s 1 and the drain contact d 1 .
  • a gate recess 92 of the high-pinch-off-voltage pHEMT H 1 locates between the source contact s 2 and the drain contact s 2 .
  • the gate contact g 1 of the low-pinch-off-voltage pHEMT L 1 locates within the gate recess 91 .
  • the gate contact g 1 is coupled to the Schottky layer 40 .
  • the gate contact g 2 of the high-pinch-off-voltage pHEMT H 1 locates within the gate recess 92 .
  • the gate contact g 2 is coupled to the Schottky layer 40 .
  • the respective first gate metal layers g 11 and g 21 of the low-pinch-off-voltage pHEMT L 1 and the high-pinch-off-voltage pHEMT H 1 are in contact with the topmost stacked region 46 of the Schottky layer 40 .
  • the low-pinch-off-voltage pHEMT gate-sinking region g 12 is beneath the low-pinch-off-voltage pHEMT first gate metal layer g 11 .
  • the high-pinch-off-voltage pHEMT gate-sinking region g 22 is beneath the high-pinch-off-voltage pHEMT first gate metal layer g 21 .
  • the gate-sinking bottom boundaries g 13 and g 23 are located within the Schottky layer 40 .
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is closer to the semiconductor substrate 10 than the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 .
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located between an upper limit g 24 and a lower limit g 25 .
  • the upper limit g 24 is 10 ⁇ above one of the stacked region contact interfaces of the Schottky layer 40 .
  • the lower limit g 25 is 10 ⁇ below the same stacked region contact interface.
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 may be located at one of the stacked region contact interfaces of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located between an upper limit g 14 and a lower limit g 15 .
  • the upper limit g 24 is 10 ⁇ above one of the stacked region contact interfaces of the Schottky layer 40 .
  • the lower limit g 15 is 10 ⁇ below the same stacked region contact interface.
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at one of the stacked region contact interfaces of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the stacked region contact interface 45 of the Schottky layer 40
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located at the stacked region contact interface 43 of the Schottky layer 40 .
  • 3B-3E show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention.
  • the upper limit g 14 and the lower limit g 15 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 45 , respectively.
  • the upper limit g 24 and the lower limit g 25 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 43 , respectively.
  • FIG. 3B-3E show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention.
  • the upper limit g 14 and the lower limit g 15 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 45 , respectively.
  • the upper limit g 24 and the lower limit g 25 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 43 , respectively.
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the stacked region contact interface 45 of the Schottky layer 40
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located between the upper limit g 24 and the stacked region contact interface 43 of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the stacked region contact interface 45 of the Schottky layer 40
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located between the lower limit g 25 and the stacked region contact interface 43 of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located between the lower limit g 15 and the stacked region contact interface 45 of the Schottky layer 40
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located between the lower limit g 25 and the stacked region contact interface 43 of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located between the upper limit g 14 and the stacked region contact interface 45 of the Schottky layer 40
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located between the lower limit g 25 and the stacked region contact interface 43 of the Schottky layer 40 .
  • one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material, wherein the AlGaAs-based semiconductor material includes at least one of AlGaAs, AlGaAsP, and InAlGaAs, and wherein the InGaP-based semiconductor material includes at least one of InGaP, InGaPAs, and AlInGaP.
  • the Schottky layer may comprise more than three stacked regions of semiconductor material, in which each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, and any two stacked region contact interfaces differ in distance from the semiconductor substrate.
  • FIGS. 3F and 3G show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention, in which the Schottky layer 40 comprises from bottom to top four stacked regions 42 , 44 , 46 , and 48 of semiconductor material. Stacked region contact interfaces 43 , 45 , and 47 are provided between the stacked regions. As shown in FIG.
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the stacked region contact interface 47 of the Schottky layer 40
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located at the stacked region contact interface 43 of the Schottky layer 40
  • the upper limit g 14 and the lower limit g 15 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 45 , respectively.
  • the upper limit g 24 and the lower limit g 25 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 43 , respectively.
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located between the lower limit g 15 and the stacked region contact interface 45 of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located between the lower limit g 25 and the stacked region contact interface 43 of the Schottky layer 40 .
  • FIGS. 4A-4C show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention.
  • the Schottky layer 40 comprises from bottom to top three stacked regions 42 , 44 , and 46 of semiconductor material, and the stacked region contact interfaces 43 and 45 are provided between the stacked regions.
  • the Schottky layer may comprise more than three stacked regions of semiconductor material.
  • the Schottky layer 40 comprises from bottom to top four stacked regions 42 , 44 , 46 , and 48 of semiconductor material, and the stacked region contact interfaces 43 , 45 , and 47 are provided between the stacked regions.
  • FIGS. 4A-4C show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention.
  • the Schottky layer 40 comprises from bottom to top three stacked regions 42 , 44 , and 46 of semiconductor material, and the stacked region contact interfaces 43 and 45 are provided between the stacked regions.
  • the plurality of epitaxial semiconductor layers 2 further comprise a first contact layer 60 which is in contact with an upper surface of the topmost stacked region of the Schottky layer 46 .
  • An uppermost contact interface 49 is provided between the first contact layer 60 and the topmost stacked region of the Schottky layer 40 .
  • the first cap layer 50 is formed on the first contact layer 60 .
  • the respective first gate metal layers g 11 and g 21 of the low-pinch-off-voltage pHEMT L 1 and the high-pinch-off-voltage pHEMT H 1 are in contact with the first contact layer 60 .
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located between an upper limit g 14 and a lower limit g 15 .
  • the upper limit g 14 is 10 ⁇ above the uppermost contact interface 49 or 10 ⁇ above one of the stacked region contact interfaces of the Schottky layer 40 .
  • the lower limit g 15 is 10 ⁇ below the same contact interface.
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located between an upper limit g 24 and a lower limit g 25 .
  • the upper limit g 24 is 10 ⁇ above one of the stacked region contact interfaces of the Schottky layer 40 .
  • the lower limit g 25 is 10 ⁇ below the same stacked region contact interface.
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the stacked region contact interface 45 of the Schottky layer 40
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located at the stacked region contact interface 43 of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the uppermost contact interface 49
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located at the stacked region contact interface 43 of the Schottky layer 40
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the uppermost contact interface 49
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located at the stacked region contact interface 43 of the Schottky layer 40 .
  • the first contact layer 60 includes at least one of GaAs, AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaPAs, and AlInGaP, wherein the first contact layer 60 differs in material from the topmost stacked region of the Schottky layer 40 .
  • the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT include at least one of molybdenum (Mo), tungsten (W), tungsten-silicide (WSi), titanium (Ti), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), and rhenium (Re).
  • Mo molybdenum
  • W tungsten
  • WSi tungsten-silicide
  • Ti titanium
  • Ir iridium
  • palladium Pd
  • platinum platinum
  • Ni nickel
  • Co cobalt
  • Co chromium
  • Cr ruthenium
  • Ru osmium
  • the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of different materials. In some embodiments, the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of the same material. In some embodiments, the first gate metal layer of the high-pinch-off-voltage pHEMT is greater in thickness than the first gate metal layer of the low-pinch-off-voltage pHEMT.
  • FIG. 5 shows another embodiment of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention.
  • the plurality of epitaxial semiconductor layers 2 further comprise an etch stop layer 70 and a second cap layer 52 .
  • the etch stop layer 70 is coupled to the first cap layer 50 .
  • the second cap layer 52 is formed on the etch stop layer 70 .
  • the respective source and drain contacts s 1 , s 2 , d 1 , and d 2 of the low-pinch-off-voltage pHEMT L 1 and the high-pinch-off-voltage pHEMT H 1 are coupled to the second cap layer.
  • the etch stop layer 70 includes at least one of InGaP, InGaPAs, AlInGaP, and AlAs
  • the second cap layer 52 is GaAs.
  • the first cap layer 50 is GaAs.
  • the channel layer 30 includes at least one of GaAs and InGaAs.
  • the buffer layer 20 includes at least one of GaAs and AlGaAs.
  • the compound semiconductor substrate 10 is GaAs.
  • FIG. 6 shows another embodiment of the monolithic integrated circuit device having gate-sinking pHEMTs provided by the present invention.
  • the plurality of epitaxial semiconductor layers further comprise a carrier supply layer 35 .
  • the carrier supply layer is formed on the channel layer 30
  • the Schottky layer 40 is formed on the carrier supply layer 35 .
  • the carrier supply layer 35 includes at least one of AlGaAs, AlGaAsP, and InAlGaAs.
  • FIG. 7 shows another embodiment of the monolithic integrated circuit device having gate-sinking pHEMTs provided by the present invention.
  • the Schottky layer 40 comprises from bottom to top four stacked regions 42 , 44 , 46 , and 48 of semiconductor material, and the stacked region contact interfaces 43 , 45 , and 47 are provided between the stacked regions.
  • the low-pinch-off-voltage pHEMT L 1 and the high-pinch-off-voltage pHEMT H 1 share a pair of source s 1 and drain d 1 contacts.
  • the low-pinch-off-voltage pHEMT includes a gate contact g 1 .
  • the gate contact g 1 comprises a first gate metal layer g 11 , a gate-sinking region g 12 , and a gate-sinking bottom boundary g 13 .
  • the high-pinch-off-voltage pHEMT H 1 includes a gate contact g 2 .
  • the gate contact g 2 comprises a first gate metal layer g 21 , a gate-sinking region g 22 , and a gate-sinking bottom boundary g 23 .
  • the respective gate recesses 91 and 92 of the low-pinch-off-voltage pHEMT L 1 and the high-pinch-off-voltage pHEMT H 1 are located between the source contact s 1 and the drain contact d 1 .
  • the gate contact g 1 of the low-pinch-off-voltage pHEMT L 1 which is coupled to the Schottky layer 40 locates within the gate recess 91 .
  • the gate contact g 2 of the high-pinch-off-voltage pHEMT H 1 which is coupled to the Schottky layer 40 locates within the gate recess 92 .
  • the respective first gate metal layers g 11 and g 21 of the low-pinch-off-voltage pHEMT L 1 and the high-pinch-off-voltage pHEMT H 1 are in contact with the topmost stacked region 46 of the Schottky layer 40 .
  • the low-pinch-off-voltage pHEMT gate-sinking region g 12 is beneath the low-pinch-off-voltage pHEMT first gate metal layer g 11 .
  • the high-pinch-off-voltage pHEMT gate-sinking region g 22 is beneath the high-pinch-off-voltage pHEMT first gate metal layer g 21 .
  • the upper limit g 14 and the lower limit g 15 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 47 , respectively.
  • the upper limit g 24 and the lower limit g 25 are 10 ⁇ above and 10 ⁇ below the stacked region contact interface 43 , respectively.
  • the gate-sinking bottom boundary g 13 of the low-pinch-off-voltage pHEMT L 1 is located at the stacked region contact interface 47 of the Schottky layer 40 .
  • the gate-sinking bottom boundary g 23 of the high-pinch-off-voltage pHEMT H 1 is located at the stacked region contact interface 43 of the Schottky layer 40 .
  • the uniformity of the pinch-off voltage and the gate-to-channel distance of each pHEMT in the monolithic integrated circuit device are markedly improved.
  • the pinch-off voltage of each pHEMT in the monolithic integrated circuit device can be designed to any (positive or negative) desired value. Also, the fabrication process is simplified, and the economic benefit is improved.

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Abstract

A monolithic integrated circuit device formed in a multi-layer structure comprises a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT. A Schottky layer in the multi-layer structure contains at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween. The gate-sinking pHEMTs each includes a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The first gate metal layers are in contact with the topmost stacked region of the Schottky layer. The gate-sinking regions are beneath the first gate metal layers. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT, which is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, locates within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.

Description

FIELD OF THE INVENTION
The present invention relates to a monolithic integrated circuit device composed of more than one pseudomorphic high electron mobility transistors (pHEMTs). More specifically, the invention relates to monolithic integrated gate-sinking pHEMTs having inherently extremely uniform pinch-off or threshold voltage across a wafer and from wafer to wafer.
BACKGROUND OF THE INVENTION
Gate-sinking or buried-gate technique has been widely adopted to achieve enhancement-mode (E-mode) pseudomorphic high electron mobility transistors (pHEMTs) in which the pinch-off or threshold voltages (pinch-off voltage hereafter) exhibit positive values due to the reduction of the gate-to-channel distance. As the transistor epitaxial structure and fabrication process are properly designed, the application of the gate-sinking technique should include, but not be limited to E-mode pHEMTs. The gate-sinking technique requires careful control of the temperature and duration during the thermal treatment to ensure that the first deposited gate metal diffuses uniformly, consistently, and fully into the Schottky barrier layer. Accordingly, gate-sinking pHEMTs with highly uniform pinch-off voltage across a wafer and from wafer to wafer are mostly demanded in this field.
In certain applications, such as digital and bias circuits, a plurality of pHEMTs with various pinch-off voltages are desirable. For example, a normally-off (positive pinch-off voltage) pHEMT and a normally-on (negative pinch-off voltage) pHEMT are monolithically integrated on the same semiconductor substrate. FIG. 1 discloses a conventional monolithic integrated circuit device composed of a depletion-mode (D-mode) pHEMT D1 and an E-mode pHEMT E1. The conventional monolithic integrated circuit device comprises a compound semiconductor substrate 100 and an epitaxial structure 110. The epitaxial structure 110 grown on the compound semiconductor substrate 100 sequentially comprises from bottom to top a buffer layer 111, a channel layer 112, a Schottky layer 113, a Schottky contact layer 114, a first etch stop layer 115, a first conductive layer 116, a second etch stop layer 117, a second conductive layer 118. A source electrode 101/103 and a drain electrode 102/104 of the D-mode/E-mode pHEMT are formed on the second conductive layer 118. A gate recess 108 locates between the source electrode 101 and the drain electrode 102 of the D-mode pHEMT with a recess bottom defined by the Schottky contact layer 114. A gate recess 109 locates between the source electrode 103 and the drain electrode 104 of the E-mode pHEMT with a recess bottom defined by the Schottky layer 113. A gate electrode 120 of the D-mode pHEMT is deposited on the Schottky contact layer 114 within the gate recess 108. A gate electrode 130 of the E-mode pHEMT is deposited on the Schottky layer 113 within the gate recess 109. As shown in FIG. 1, the gate electrodes of the D-mode and E-mode pHEMTs are formed on distinct different semiconductor layers. It indicates that extra photolithography and etch steps are required for both of the D-mode and E-mode pHEMTs in the conventional monolithic integrated circuit device.
FIG. 2 discloses another conventional monolithic integrated circuit device composed of a D-mode pHEMT D1 and an E-mode pHEMT E1. As shown in FIG. 2, both of the D-mode and the E-mode pHEMTs are fabricated using the gate-sinking technique. The monolithic integrated circuit device comprises a compound semiconductor substrate 200 and an epitaxial structure 210. The epitaxial structure 210 grown on the compound semiconductor substrate 200 sequentially comprises from bottom to top a buffer layer 211, a channel layer 212, a first Schottky barrier layer 213, a first etch stop layer 214, a second Schottky barrier layer 215, a second etch stop layer 216, and an ohmic contact layer 217. A source electrode 201/203 and a drain electrode 202/204 of the D-mode/E-mode pHEMT are formed on the ohmic contact layer 217. A gate recess 208 locates between the source electrode 201 and the drain electrode 202 of the D-mode pHEMT with a recess bottom defined by the second Schottky barrier layer 215. A gate recess 209 locates between the source electrode 203 and the drain electrode 204 of the E-mode pHEMT with a recess bottom defined by the first Schottky barrier layer 213. The gate electrode 220 of the D-mode pHEMT is deposited on the second Schottky barrier layer 215 within the gate recess 208. The gate electrode 230 of the E-mode pHEMT is deposited on the first Schottky barrier layer 213 within the gate recess 209. A gate-sinking region 221/231 is beneath the gate electrode 220/230 of the D-mode/E-mode pHEMT. In the conventional monolithic integrated circuit device shown in FIG. 2, the respective gate electrodes of the D-mode pHEMT and the E-mode pHEMT are formed on distinct different Schottky layers. It indicates that extra photolithography and etch steps are required to form the D-mode and E-mode gate recesses 208, 209, leading to additional cost and complexity in the pHEMT fabrication process. Most importantly, the etched surfaces of the Schottky barrier layers 213, 215 may cause defects and surface states, which would degrade the transistor performance and alter the pHEMT pinch-off voltage from the target value.
Additionally, the conventional monolithic integrated circuit device shown in FIG. 2 exhibits serious problem in controlling the respective pinch-off voltages of the D-mode pHEMT as well as the E-mode pHEMT. It is practically impossible to rule the bottom boundary of the gate-sinking region 221/231 of the D-mode/E-mode pHEMT perfectly at a specific narrow region within the Schottky barrier layer. This fact can be ascribed to the variations in the thickness of the gate electrodes, thermal treatment temperature, and thermal treatment duration across a wafer and from wafer to wafer. These undesirable effects cause a high degree of variability in transistor pinch-off voltage.
Accordingly, a new design to achieve monolithic integrated gate-sinking pHEMTs having inherently extremely uniform pinch-off voltages across a wafer and from wafer to wafer is very much desirable.
SUMMARY OF THE INVENTION
In order to achieve the expected pinch-off voltage uniformity in a monolithic integrated circuit device having more than one gate-sinking pHEMTs, a composite Schottky layer structure made of stacked semiconductor layers is implemented. By controlling the sinking depth of the gate metal to a specific interface in the stacked semiconductor layers of the Schottky layer, the pinch-off voltage variation of the pHEMT across a wafer and from wafer to wafer can be significantly reduced. Moreover, the pinch-off voltage of each pHEMT in the monolithic integrated circuit device can be tuned to any (positive or negative) desired value. Accordingly, the present invention provides a monolithic integrated circuit device which is composed of a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT in a multi-layer structure, wherein the multi-layer structure includes a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs, including a buffer layer overlaid by a channel layer overlaid by a Schottky layer overlaid by a first cap layer. The Schottky layer comprises from bottom to top at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, and any two stacked region contact interfaces differ in distance from the semiconductor substrate. Source and drain contacts of the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs are coupled to the first cap layer. The low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs each include a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The respective gate contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the Schottky layer, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are in contact with the topmost stacked region of the Schottky layer. The low-pinch-off-voltage pHEMT gate-sinking region and the high-pinch-off-voltage pHEMT gate-sinking region are beneath the first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT, respectively. The respective gate-sinking bottom boundaries of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are located within the Schottky layer, wherein the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, and the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.
Moreover, the present invention provides a monolithic integrated circuit device comprising a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT in a multi-layer structure, wherein the multi-layer structure includes a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs, including a buffer layer overlaid by a channel layer overlaid by a Schottky layer overlaid by a first contact layer overlaid by a first cap layer. The Schottky layer comprises from bottom to top at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, and any two stacked region contact interfaces differ in distance from the semiconductor substrate. The first contact layer is in contact with an upper surface of the topmost stacked region of the Schottky layer, and an uppermost contact interface is provided between the first contact layer and the topmost stacked region of the Schottky layer. Source and drain contacts of the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs are coupled to the first cap layer. The low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs each include a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The respective gate contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the Schottky layer, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are in contact with the first contact layer. The low-pinch-off-voltage pHEMT gate-sinking region and the high-pinch-off-voltage pHEMT gate-sinking region are beneath the first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT, respectively. The gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located within the Schottky layer or within 10 Å above or below the uppermost contact interface. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located within the Schottky layer and within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer. And the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT.
In some embodiments, the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.
In some embodiments, the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located at one of the stacked region contact interfaces of the Schottky layer.
In some embodiments, the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located at one of the stacked region contact interfaces of the Schottky layer or at the uppermost contact interface.
In some embodiments, the first contact layer includes at least one of GaAs, AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaPAs, and AlInGaP, and the first contact layer differs in material from the topmost stacked region of the Schottky layer.
In some embodiments, in any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material, wherein the AlGaAs-based semiconductor material includes at least one of AlGaAs, AlGaAsP, and InAlGaAs, and wherein the InGaP-based semiconductor material includes at least one of InGaP, InGaPAs, and AlInGaP.
In some embodiments, the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT include at least one of molybdenum (Mo), tungsten (W), tungsten-silicide (WSi), titanium (Ti), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), and rhenium (Re).
In some embodiments, the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of different materials.
In some embodiments, the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of the same material.
In some embodiments, the first gate metal layer of the high-pinch-off-voltage pHEMT is greater in thickness than the first gate metal layer of the low-pinch-off-voltage pHEMT.
In some embodiments, the plurality of epitaxial semiconductor layers further comprise an etch stop layer and a second cap layer, wherein the etch stop layer is formed on the first cap layer, the second cap layer is formed on the etch stop layer, and the respective source and drain contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the second cap layer.
In some embodiments, the etch stop layer includes at least one of InGaP, InGaPAs, AlInGaP, and AlAs, wherein the second cap layer is GaAs.
In some embodiments, the first cap layer is GaAs, wherein the channel layer includes at least one of GaAs and InGaAs, the buffer layer includes at least one of GaAs and AlGaAs, and the compound semiconductor substrate is GaAs.
For further understanding the characteristics and effects of the present invention, some preferred embodiments referred to drawings are in detail described as follows.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a cross-sectional side view of a conventional embodiment of a monolithic integrated circuit device.
FIG. 2 is another cross-sectional side view of a conventional embodiment of a monolithic integrated circuit device having gate-sinking pHEMTs.
FIGS. 3A-3G are cross-sectional side views of embodiments of a monolithic integrated circuit device having gate-sinking pHEMTs according to the present invention.
FIGS. 4A-4C are cross-sectional side views of embodiments of a monolithic integrated circuit device having gate-sinking pHEMTs according to the present invention.
FIGS. 5-7 are cross-sectional side views of embodiments of a monolithic integrated circuit device having gate-sinking pHEMTs according to the present invention.
 DETAILED DESCRIPTIONS OF PREFERRED EMBODIMENTS
FIG. 3A is a cross-sectional side view of an embodiment of a monolithic integrated circuit device having gate-sinking pHEMTs. The monolithic integrated circuit device having gate-sinking pHEMTs 1 comprises a low-pinch-off-voltage pHEMT L1 and a high-pinch-off-voltage pHEMT H1 in a multi-layer structure 2. The multi-layer structure 2 includes a semiconductor substrate 10 overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs. The plurality of epitaxial semiconductor layers include a buffer layer 20 overlaid by a channel layer 30 overlaid by a Schottky layer 40 overlaid by a first cap layer 50. The Schottky layer 40 comprises three stacked regions 42, 44, and 46 of semiconductor material from bottom to top, in which each of the two adjacent stacked regions differs in material. A stacked region contact interface 43 is provided between the adjacent stacked regions 42 and 44. A stacked region contact interface 45 is provided between the adjacent stacked regions 44 and 46. The stacked region contact interfaces 43 and 45 differ in distance from the semiconductor substrate. The plurality of epitaxial semiconductor layers 2 comprises an isolation region 5 locating between the low-pinch-off-voltage pHEMT L1 and the high-pinch-off-voltage pHEMT H1. Each of the pHEMTs L1, H1 is electrically isolated by the isolation region 5. The source and drain contacts s1 and d1 of the low-pinch-off-voltage pHEMT L1 are coupled to the first cap layer 50. The source and drain contacts s2, d2 of the high-pinch-off-voltage pHEMT H1 are coupled to the first cap layer 50. The low-pinch-off-voltage pHEMT L1 contains a gate contact g1. The gate contact g1 comprises a first gate metal layer g11. The gate contact g1 may further comprise a second gate metal layer deposited on the first gate metal layer g11. A gate-sinking region g12 is beneath the first gate metal layer g11. The gate-sinking region g12 has a gate-sinking bottom boundary g13. The high-pinch-off-voltage pHEMT H1 contains a gate contact g2. The gate contact g2 comprises a first gate metal layer g21. The gate contact g2 may further comprise a second gate metal layer deposited on the first gate metal layer g21. A gate-sinking region g22 is beneath the first gate metal layer g21. The gate-sinking region g22 has a gate-sinking bottom boundary g23. A gate recess 91 of the low-pinch-off-voltage pHEMT L1 locates between the source contact s1 and the drain contact d1. A gate recess 92 of the high-pinch-off-voltage pHEMT H1 locates between the source contact s2 and the drain contact s2. The gate contact g1 of the low-pinch-off-voltage pHEMT L1 locates within the gate recess 91. The gate contact g1 is coupled to the Schottky layer 40. The gate contact g2 of the high-pinch-off-voltage pHEMT H1 locates within the gate recess 92. The gate contact g2 is coupled to the Schottky layer 40. The respective first gate metal layers g11 and g21 of the low-pinch-off-voltage pHEMT L1 and the high-pinch-off-voltage pHEMT H1 are in contact with the topmost stacked region 46 of the Schottky layer 40. The low-pinch-off-voltage pHEMT gate-sinking region g12 is beneath the low-pinch-off-voltage pHEMT first gate metal layer g11. The high-pinch-off-voltage pHEMT gate-sinking region g22 is beneath the high-pinch-off-voltage pHEMT first gate metal layer g21.
The gate-sinking bottom boundaries g13 and g23 are located within the Schottky layer 40. The gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is closer to the semiconductor substrate 10 than the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1. The gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located between an upper limit g24 and a lower limit g25. The upper limit g24 is 10 Å above one of the stacked region contact interfaces of the Schottky layer 40. The lower limit g25 is 10 Å below the same stacked region contact interface. In some embodiments, the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 may be located at one of the stacked region contact interfaces of the Schottky layer 40. In some embodiments, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located between an upper limit g14 and a lower limit g15. The upper limit g24 is 10 Å above one of the stacked region contact interfaces of the Schottky layer 40. The lower limit g15 is 10 Å below the same stacked region contact interface. In some embodiments, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at one of the stacked region contact interfaces of the Schottky layer 40. In the embodiment shown in FIG. 3A, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the stacked region contact interface 45 of the Schottky layer 40, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located at the stacked region contact interface 43 of the Schottky layer 40. FIGS. 3B-3E show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention. In FIGS. 3B-3E, the upper limit g14 and the lower limit g15 are 10 Å above and 10 Å below the stacked region contact interface 45, respectively. The upper limit g24 and the lower limit g25 are 10 Å above and 10 Å below the stacked region contact interface 43, respectively. In FIG. 3B, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the stacked region contact interface 45 of the Schottky layer 40, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located between the upper limit g24 and the stacked region contact interface 43 of the Schottky layer 40. In FIG. 3C, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the stacked region contact interface 45 of the Schottky layer 40, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located between the lower limit g25 and the stacked region contact interface 43 of the Schottky layer 40. In FIG. 3D, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located between the lower limit g15 and the stacked region contact interface 45 of the Schottky layer 40, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located between the lower limit g25 and the stacked region contact interface 43 of the Schottky layer 40. In FIG. 3E, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located between the upper limit g14 and the stacked region contact interface 45 of the Schottky layer 40, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located between the lower limit g25 and the stacked region contact interface 43 of the Schottky layer 40.
In some embodiments, in any two adjacent stacked regions of the Schottky layer 40, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material, wherein the AlGaAs-based semiconductor material includes at least one of AlGaAs, AlGaAsP, and InAlGaAs, and wherein the InGaP-based semiconductor material includes at least one of InGaP, InGaPAs, and AlInGaP.
In the present invention, the Schottky layer may comprise more than three stacked regions of semiconductor material, in which each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, and any two stacked region contact interfaces differ in distance from the semiconductor substrate. FIGS. 3F and 3G show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention, in which the Schottky layer 40 comprises from bottom to top four stacked regions 42, 44, 46, and 48 of semiconductor material. Stacked region contact interfaces 43, 45, and 47 are provided between the stacked regions. As shown in FIG. 3F, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the stacked region contact interface 47 of the Schottky layer 40, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located at the stacked region contact interface 43 of the Schottky layer 40. In FIG. 3G, the upper limit g14 and the lower limit g15 are 10 Å above and 10 Å below the stacked region contact interface 45, respectively. The upper limit g24 and the lower limit g25 are 10 Å above and 10 Å below the stacked region contact interface 43, respectively. The gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located between the lower limit g15 and the stacked region contact interface 45 of the Schottky layer 40. The gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located between the lower limit g25 and the stacked region contact interface 43 of the Schottky layer 40.
FIGS. 4A-4C show other embodiments of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention. In FIGS. 4A and 4B, the Schottky layer 40 comprises from bottom to top three stacked regions 42, 44, and 46 of semiconductor material, and the stacked region contact interfaces 43 and 45 are provided between the stacked regions. As described previously, the Schottky layer may comprise more than three stacked regions of semiconductor material. In FIG. 4C, the Schottky layer 40 comprises from bottom to top four stacked regions 42, 44, 46, and 48 of semiconductor material, and the stacked region contact interfaces 43, 45, and 47 are provided between the stacked regions. In FIGS. 4A-4C, the plurality of epitaxial semiconductor layers 2 further comprise a first contact layer 60 which is in contact with an upper surface of the topmost stacked region of the Schottky layer 46. An uppermost contact interface 49 is provided between the first contact layer 60 and the topmost stacked region of the Schottky layer 40. The first cap layer 50 is formed on the first contact layer 60. The respective first gate metal layers g11 and g21 of the low-pinch-off-voltage pHEMT L1 and the high-pinch-off-voltage pHEMT H1 are in contact with the first contact layer 60. The gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located between an upper limit g14 and a lower limit g15. The upper limit g14 is 10 Å above the uppermost contact interface 49 or 10 Å above one of the stacked region contact interfaces of the Schottky layer 40. The lower limit g15 is 10 Å below the same contact interface. The gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located between an upper limit g24 and a lower limit g25. The upper limit g24 is 10 Å above one of the stacked region contact interfaces of the Schottky layer 40. The lower limit g25 is 10 Å below the same stacked region contact interface. As shown in FIG. 4A, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the stacked region contact interface 45 of the Schottky layer 40, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located at the stacked region contact interface 43 of the Schottky layer 40. In FIG. 4B, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the uppermost contact interface 49, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located at the stacked region contact interface 43 of the Schottky layer 40. In FIG. 4C, the gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the uppermost contact interface 49, and the gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located at the stacked region contact interface 43 of the Schottky layer 40.
In some embodiments, the first contact layer 60 includes at least one of GaAs, AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaPAs, and AlInGaP, wherein the first contact layer 60 differs in material from the topmost stacked region of the Schottky layer 40.
In some embodiments, the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT include at least one of molybdenum (Mo), tungsten (W), tungsten-silicide (WSi), titanium (Ti), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), and rhenium (Re). In some embodiments, the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of different materials. In some embodiments, the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of the same material. In some embodiments, the first gate metal layer of the high-pinch-off-voltage pHEMT is greater in thickness than the first gate metal layer of the low-pinch-off-voltage pHEMT.
FIG. 5 shows another embodiment of the monolithic integrated circuit device having gate-sinking pHEMTs of the present invention. In the present embodiment, the plurality of epitaxial semiconductor layers 2 further comprise an etch stop layer 70 and a second cap layer 52. The etch stop layer 70 is coupled to the first cap layer 50. The second cap layer 52 is formed on the etch stop layer 70. The respective source and drain contacts s1, s2, d1, and d2 of the low-pinch-off-voltage pHEMT L1 and the high-pinch-off-voltage pHEMT H1 are coupled to the second cap layer.
In some embodiments, the etch stop layer 70 includes at least one of InGaP, InGaPAs, AlInGaP, and AlAs, and the second cap layer 52 is GaAs. In some embodiments, the first cap layer 50 is GaAs. In some embodiments, the channel layer 30 includes at least one of GaAs and InGaAs. In some embodiments, the buffer layer 20 includes at least one of GaAs and AlGaAs. In some embodiments, the compound semiconductor substrate 10 is GaAs.
FIG. 6 shows another embodiment of the monolithic integrated circuit device having gate-sinking pHEMTs provided by the present invention. In the present embodiment, the plurality of epitaxial semiconductor layers further comprise a carrier supply layer 35. The carrier supply layer is formed on the channel layer 30, and the Schottky layer 40 is formed on the carrier supply layer 35. In some embodiments, the carrier supply layer 35 includes at least one of AlGaAs, AlGaAsP, and InAlGaAs.
FIG. 7 shows another embodiment of the monolithic integrated circuit device having gate-sinking pHEMTs provided by the present invention. In the present embodiment, the Schottky layer 40 comprises from bottom to top four stacked regions 42, 44, 46, and 48 of semiconductor material, and the stacked region contact interfaces 43, 45, and 47 are provided between the stacked regions. The low-pinch-off-voltage pHEMT L1 and the high-pinch-off-voltage pHEMT H1 share a pair of source s1 and drain d1 contacts. The low-pinch-off-voltage pHEMT includes a gate contact g1. The gate contact g1 comprises a first gate metal layer g11, a gate-sinking region g12, and a gate-sinking bottom boundary g13. The high-pinch-off-voltage pHEMT H1 includes a gate contact g2. The gate contact g2 comprises a first gate metal layer g21, a gate-sinking region g22, and a gate-sinking bottom boundary g23. The respective gate recesses 91 and 92 of the low-pinch-off-voltage pHEMT L1 and the high-pinch-off-voltage pHEMT H1 are located between the source contact s1 and the drain contact d1. The gate contact g1 of the low-pinch-off-voltage pHEMT L1 which is coupled to the Schottky layer 40 locates within the gate recess 91. The gate contact g2 of the high-pinch-off-voltage pHEMT H1 which is coupled to the Schottky layer 40 locates within the gate recess 92. The respective first gate metal layers g11 and g21 of the low-pinch-off-voltage pHEMT L1 and the high-pinch-off-voltage pHEMT H1 are in contact with the topmost stacked region 46 of the Schottky layer 40. The low-pinch-off-voltage pHEMT gate-sinking region g12 is beneath the low-pinch-off-voltage pHEMT first gate metal layer g11. The high-pinch-off-voltage pHEMT gate-sinking region g22 is beneath the high-pinch-off-voltage pHEMT first gate metal layer g21. In FIG. 7, the upper limit g14 and the lower limit g15 are 10 Å above and 10 Å below the stacked region contact interface 47, respectively. The upper limit g24 and the lower limit g25 are 10 Å above and 10 Å below the stacked region contact interface 43, respectively. The gate-sinking bottom boundary g13 of the low-pinch-off-voltage pHEMT L1 is located at the stacked region contact interface 47 of the Schottky layer 40. The gate-sinking bottom boundary g23 of the high-pinch-off-voltage pHEMT H1 is located at the stacked region contact interface 43 of the Schottky layer 40.
Accordingly, the uniformity of the pinch-off voltage and the gate-to-channel distance of each pHEMT in the monolithic integrated circuit device are markedly improved. Moreover, the pinch-off voltage of each pHEMT in the monolithic integrated circuit device can be designed to any (positive or negative) desired value. Also, the fabrication process is simplified, and the economic benefit is improved.
Although the embodiments of the present invention have been described in detail, many modifications and variations may be made by those skilled in the art from the teachings disclosed hereinabove. Therefore, it should be understood that any modification and variation equivalent to the spirit of the present invention be regarded to fall into the scope defined by the appended claims.

Claims (19)

What is claimed is:
1. A monolithic integrated circuit device having gate-sinking pHEMTs, comprising:
a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT in a multi-layer structure,
wherein the multi-layer structure includes a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs, including a buffer layer overlaid by a channel layer overlaid by a Schottky layer overlaid by a first cap layer,
wherein the Schottky layer comprises from bottom to top at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, wherein any two stacked region contact interfaces differ in distance from the semiconductor substrate,
wherein source and drain contacts of the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs are coupled to the first cap layer,
wherein the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs each include a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary,
wherein the respective gate contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the Schottky layer, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are in contact with the topmost stacked region of the Schottky layer,
wherein the low-pinch-off-voltage pHEMT gate-sinking region and the high-pinch-off-voltage pHEMT gate-sinking region are beneath the first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT, respectively,
wherein the respective gate-sinking bottom boundaries of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are located within the Schottky layer, wherein the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, and the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.
2. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.
3. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located at one of the stacked region contact interfaces of the Schottky layer.
4. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located at one of the stacked region contact interfaces of the Schottky layer.
5. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein in any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material, wherein the AlGaAs-based semiconductor material includes at least one of AlGaAs, AlGaAsP, and InAlGaAs, and wherein the InGaP-based semiconductor material includes at least one of InGaP, InGaPAs, and AlInGaP.
6. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the plurality of epitaxial semiconductor layers further comprise a first contact layer, wherein the first contact layer is in contact with an upper surface of the topmost stacked region of the Schottky layer, wherein an uppermost contact interface is provided between the first contact layer and the topmost stacked region of the Schottky layer, wherein the first cap layer is formed on the first contact layer, wherein the first contact layer includes at least one of GaAs, AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaPAs, and AlInGaP, wherein the first contact layer differs in material from the topmost stacked region of the Schottky layer.
7. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 6, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are in contact with the first contact layer.
8. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT include at least one of molybdenum (Mo), tungsten (W), tungsten-silicide (WSi), titanium (Ti), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), and rhenium (Re).
9. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 8, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of different materials.
10. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 8, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are made of the same material.
11. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 10, wherein the first gate metal layer of the high-pinch-off-voltage pHEMT is greater in thickness than the first gate metal layer of the low-pinch-off-voltage pHEMT.
12. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the plurality of epitaxial semiconductor layers further comprise an etch stop layer and a second cap layer, wherein the etch stop layer is coupled to the first cap layer, wherein the second cap layer is formed on the etch stop layer, wherein the respective source and drain contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the second cap layer.
13. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 12, wherein the etch stop layer includes at least one of InGaP, InGaPAs, AlInGaP, and AlAs, wherein the second cap layer is GaAs.
14. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the first cap layer is GaAs, wherein the channel layer includes at least one of GaAs and InGaAs, wherein the buffer layer includes at least one of GaAs and AlGaAs, wherein the compound semiconductor substrate is GaAs.
15. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 1, wherein the plurality of epitaxial semiconductor layers further comprise a carrier supply layer, wherein the carrier supply layer is formed on the channel layer, wherein the Schottky layer is formed on the carrier supply layer, wherein the carrier supply layer includes at least one of AlGaAs, AlGaAsP, and InAlGaAs.
16. A monolithic integrated circuit device having gate-sinking pHEMTs, comprising:
a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT in a multi-layer structure,
wherein the multi-layer structure includes a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers common to the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs, including a buffer layer overlaid by a channel layer overlaid by a Schottky layer overlaid by a first contact layer overlaid by a first cap layer,
wherein the Schottky layer comprises from bottom to top at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween, wherein any two stacked region contact interfaces differ in distance from the semiconductor substrate,
wherein the first contact layer is in contact with an upper surface of the topmost stacked region of the Schottky layer, and an uppermost contact interface is provided between the first contact layer and the topmost stacked region of the Schottky layer,
wherein source and drain contacts of the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs are coupled to the first cap layer,
wherein the low-pinch-off-voltage and the high-pinch-off-voltage pHEMTs each include a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary,
wherein the respective gate contacts of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are coupled to the Schottky layer, wherein the respective first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT are in contact with the first contact layer,
wherein the low-pinch-off-voltage pHEMT gate-sinking region and the high-pinch-off-voltage pHEMT gate-sinking region are beneath the first gate metal layers of the low-pinch-off-voltage pHEMT and the high-pinch-off-voltage pHEMT, respectively,
wherein the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located within 10 Å above or below the uppermost contact interface, and
wherein the gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT is located within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.
17. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 16, wherein the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT is located at the uppermost contact interface.
18. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 16, wherein in any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material, wherein the AlGaAs-based semiconductor material includes at least one of AlGaAs, AlGaAsP, and InAlGaAs, and the InGaP-based semiconductor material includes at least one of InGaP, InGaPAs, and AlInGaP.
19. The monolithic integrated circuit device having gate-sinking pHEMTs of claim 18, wherein the first contact layer includes at least one of GaAs, AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaAsP, and InAlGaP, and the first contact layer differs in material from the topmost stacked region of the Schottky layer.
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