JP2007324424A - Integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that different pinch off voltages are achieved by forming respective gate electrodes of a D-type FET and an E-type FET at different depths in integrating both FETs on the same substrates, which results in lower yield because of the necessity of precision in semiconductor etching in the order of several nanometers, and in higher cost because of selective etching of a plurality of semiconductor layers. <P>SOLUTION: The gate electrodes of the D-type FET and the E-type FET are deposited on the same plane on the same semiconductor layer. The lowermost layer of the deposited metal is made of platinum, and part of the lowermost layer is buried in the semiconductor layer so that the depths in burying the D-type FET and the E-type FET become different from each other. The gate electrode of the E-type FET has the platinum deposit film of 100 to 110 Å in thickness, of which the buried portion has a bottom close to a barrier layer in a second electron supply layer. The gate electrode of the D-type FET has the platinum deposit film of 40 to 60 Å in thickness. In this configuration, both FETs can sufficiently reduce the irregularity of prescribed pinch off voltages. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device in which a depletion type HEMT and an enhancement type HEMT are integrated on the same substrate.

  HEMT (High Electron Mobility Transistor) is a depletion type (hereinafter referred to as D type) depending on whether or not a channel is formed when the gate voltage is 0 V, as in MESFET (Metal Semiconductor FET). There is an enhancement type (hereinafter referred to as E type), and these are integrated on one chip.

  The D-type HEMT and the E-type HEMT have different pinch-off voltages Vp. That is, when these are integrated on the same substrate, it is necessary to form the respective gate electrodes at different depths.

  As a method of forming gate electrodes at different depths, for example, a technique is known in which, for example, in one semiconductor layer, recess etching depths for forming E-type HEMT and D-type HEMT gate electrodes are made different (for example, Patent Document 1).

Alternatively, a technique of forming gate electrodes of E-type HEMT and D-type HEMT on different epitaxial layer surfaces by repeatedly laminating a plurality of semiconductor layers (epitaxial layers) having a high etching selectivity and selectively etching them. Is also known (see Non-Patent Document 1, for example).
Japanese Patent Laid-Open No. 7-142585 Kazuhiro Tahara and three others, “Development of Single Control SPDT Switch IC”, NEC Technical Report Vol. 55 No. 4/2002

  In the HEMT, the variation in the pinch-off voltage Vp is the variation in the gate electrode formation position, that is, the height of the bottom of the gate electrode. Specifically, when the height of the bottom of the gate electrode varies by about 5 to 20 inches, the HEMT pinch-off voltage Vp varies by 0.1V. In general, it is desirable that variations in the HEMT pinch-off voltage Vp be kept within about ± 0.1 V at the maximum for both the D-type HEMT and the E-type HEMT. Therefore, in order to keep the variation in the pinch-off voltage Vp within the range of ± 0.1 V at the maximum, it is necessary to suppress the variation in the height of the bottom of the gate electrode to about ± 5 to 20 mm at the maximum.

  However, in general, it is extremely difficult to suppress the variation in etching (the variation in the height of the bottom of the gate electrode) to about ± 5 to 20 mm at the maximum. That is, as in the above-mentioned Patent Document 1, in the method of forming gate electrodes at different depths by recess etching, the biggest problem is that the variation in pinch-off voltage Vp is too large and the yield is poor.

  Further, in the method of obtaining a predetermined pinch-off voltage for each of the D-type HEMT and the E-type HEMT by selectively etching a plurality of stacked semiconductor layers as in Non-Patent Document 1, the required pinch-off voltage is obtained. Accordingly, it is necessary to perform etching so as to expose a predetermined semiconductor layer. However, in order to cope with only two types of pinch-off voltages, enhancement and depletion, a semiconductor layer (epitaxial layer) having a large etching selectivity must be repeatedly stacked and etched. For this reason, there existed a problem that man-hours were many and cost became high.

  The present invention has been made in view of the various circumstances described above, and includes a substrate in which a semiconductor layer to be a buffer layer, a channel layer, an electron supply layer, a barrier layer, and a cap layer are sequentially stacked on a compound semiconductor substrate, and the substrate. A first FET having a first gate electrode and set to a first pinch-off voltage; and a first FET integrated on the same substrate as the first FET and having a second gate electrode and set to a second pinch-off voltage. 2FET, and the first gate electrode is provided on the surface of the barrier layer by metal deposition, and a part of the first gate electrode is embedded in the barrier layer, and the second gate electrode is formed by deposition of the metal. Provided on the surface of the barrier layer in the same plane as the first gate electrode and partially embedded in the barrier layer, the deposited film thickness of the first gate electrode is within the semiconductor layer against the increase in the deposited film thickness of the metal Buried in The ratio of increase in the write depth, solves With more than thickness decrease of the correlation coefficient begins in correlation of the deposition thickness Prefecture.

  According to the present invention, first, in the integrated circuit device in which the D-type HEMT and the E-type HEMT are integrated on the same substrate, the variation in the pinch-off voltage Vp can be reduced for both the D-type HEMT and the E-type HEMT. Yield can be improved.

  Second, since the number of stacked epitaxial layers on the buffer layer can be minimized, the wafer cost can be reduced, and the number of recess etchings can be minimized, thereby reducing the process cost.

  Third, since the gate electrode can be provided in the AlGaAs layer, abnormal diffusion of Pt on the surface of the InGaP layer can be avoided and the breakdown voltage can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a cross-sectional view illustrating an integrated circuit device according to the first embodiment.

  In the integrated circuit device according to the first embodiment, the first FET 10 and the second FET 20 are integrated on the same substrate 30. As an example, a switch integrated circuit (MMIC) incorporating a logic circuit, the switching element is constituted by the first FET 10, and the logic circuit for controlling the switching element is constituted by the first FET 10 and the second FET 20, which are the same substrate (chip). 30 is integrated.

  The first FET 10 is an E-type HEMT (E-FET), and the second FET 20 is a D-type HEMT (D-FET). In FIG. 1, the first FET 10 and the second FET 20 are shown adjacent to each other. However, these may be integrated on the same substrate, and need not be adjacent.

  The substrate 30 includes a semiconductor layer to be a buffer layer 32, a channel layer 35, an electron supply layer (a first electron supply layer 33 and a second electron supply layer 36), a barrier layer 37, and a cap layer 38 on the compound semiconductor substrate 31, respectively. Laminated.

  Specifically, the substrate 30 includes a non-doped buffer layer 32, a first electron supply layer 33, a spacer layer 34a, a channel (electron travel) layer 35, a spacer layer 34b, and second electrons on a semi-insulating GaAs substrate 31. A supply layer 36, a barrier layer 37, an etching stop layer 39, and a cap layer 38 are laminated in this order.

  The buffer layer 32 is a high-resistance layer to which no impurity is added, and its film thickness is about several thousand Å.

The first electron supply layer 33 is made of a material having a larger band gap than the channel layer 35. Further, the impurity concentration of the n-type impurity (for example, Si) in the n + -type AlGaAs layer of the first electron supply layer 33 is related to the pinch-off voltage Vp, the on-resistance Ron, and the breakdown voltage. The impurity concentration of the first electron supply layer 33 is desirably 1.0 × 10 ¹⁸ cm ^{−3 to} 5.0 × 10 ¹⁸ cm ⁻³ .

  The channel layer 35 is a non-doped InGaAs layer, and spacer layers 34a and 34b of a non-doped AlGaAs layer are disposed above and below the channel layer 35.

Similarly to the first electron supply layer 33, the second electron supply layer 36 is an n + type AlGaAs layer having a band gap larger than that of the channel layer 35. The impurity concentration of the n-type impurity (for example, Si) in the second electron supply layer 36 is related to the pinch-off voltage Vp, the on-resistance Ron, and the breakdown voltage. The impurity concentration is 1.0 × 10 ¹⁸ cm ^{−3 to} 5.0 × 10 ¹⁸ cm ⁻³ . As an example, in the first embodiment, the impurity concentration is 2.6 × 10 ¹⁸ cm ⁻³ and the thickness is 120 mm. And

  As described above, by adopting a double heterojunction structure in which the first electron supply layer 33 and the second electron supply layer 36 are respectively disposed above and below the channel layer 35, the carrier density is increased and the on-resistance Ron is extremely reduced. it can.

  The barrier layer 37 is a non-doped AlGaAs layer, and is disposed between the etching stop layer 39 and the second electron supply layer 36 to ensure a predetermined breakdown voltage and pinch-off voltage. The thickness of the barrier layer 37 is 250 mm or more. In the first embodiment, the thickness is 260 mm.

  The etching stop layer 39 is an n + -type InGaP layer that is resistant to oxidation and resistant to chemical stress from the outside and is stable in reliability, and has a thickness of about 100 mm.

Further, an n + type GaAs layer to be the cap layer 38 is laminated on the uppermost layer. The cap layer 38 has a thickness of 600 mm or more and an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ or more, preferably a film thickness of about 1000 mm and an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more.

  The cap layer 38 is patterned into a desired shape, and becomes the source region 38ES and the drain region 38ED of the first FET 10, and the source region 38DS and the drain region 38DD of the second FET 20, respectively.

  In addition, the etching stop layer 39 of the first embodiment is etched in the same pattern as the upper cap layer 38. In the first embodiment, by providing the etching stop layer 39, side etching of the cap layer 38 can be performed by wet etching as selective etching.

  A source electrode 12 and a drain electrode 13 formed of ohmic metal layers (AuGe / Ni / Au) are provided on the source region 38ES and the drain region 38ED of the first FET 10, respectively.

  The first gate electrode 11 of the first FET 10 is provided on the surface of the barrier layer 37 exposed between the source region 38ES and the drain region 38ED. The first gate electrode 11 is formed of a first gate metal layer whose lowermost layer is Pt (platinum). In the first embodiment, the first gate metal layer is a deposited metal layer of Pt / Mo, and the deposited film thickness Tpa1 of Pt is 100 mm or more, and is 117 mm as an example. The deposited film thickness of Mo is 50 mm.

  A part of Pt is diffused into the semiconductor layer by the heat treatment, and a part of the first gate electrode 11 is embedded in the barrier layer 37. The portion where the first gate electrode 11 is embedded also functions as a part of the first gate electrode 11. Hereinafter, the portion where the first gate electrode 11 is embedded is referred to as a first embedded portion 11b. The depth Tpb1 of the first embedded portion 11b from the surface of the barrier layer 37 is 274 mm. Since the thickness of the barrier layer 37 is 260 mm, the bottom of the first embedded portion 11 b penetrates the barrier layer 37 and reaches the second electron supply layer 36. That is, the first gate electrode 11 forms a barrier layer 37 and a second electron supply layer 36 Schottky junction.

  The first FET 10 is an E-type HEMT (E-FET), and the pinch-off voltage Vp1 is, for example, 0.25V. The HEMT pinch-off voltage Vp is determined by the distance (depth) from the bottom of the gate electrode to the surface of the second electron supply layer. That is, in the first embodiment, the pinch-off voltage Vp1 of the first FET 10 is determined by the distance d1 from the bottom of the first embedded portion 11b to the surface of the second electron supply layer 36. That is, the first FET 10 is set to a pinch-off voltage Vp1 of 0.25 V by setting the distance d1 to −14 mm. In this case, since the bottom of the first embedded portion 11b reaches the second electron supply layer 36, the distance d1 has a negative value.

  A source electrode 22 and a drain electrode 23 each formed of an ohmic metal layer (AuGe / Ni / Au) are also provided on the source region 38DS and the drain region 38DD of the second FET 20.

  The second gate electrode 21 of the second FET 20 is provided on the surface of the barrier layer 37 exposed between the source region 38DS and the drain region 38DD.

  The second gate electrode 21 of the second FET 20 is formed of a second gate metal layer having a lowermost layer of Pt (platinum). In the first embodiment, the second gate metal layer is a deposited metal layer of Pt / Mo, and the deposited film thickness Tpa2 of Pt is 40 to 60 mm, and here is 51 mm. The deposited film thickness of Mo is 50 mm.

  A part of Pt is diffused into the semiconductor layer by the heat treatment, and a part of the second gate electrode 21 is embedded in the barrier layer 37. The portion where the second gate electrode 21 is embedded also functions as a part of the second gate electrode 21. Hereinafter, the portion where the second gate electrode 21 is embedded is referred to as a second embedded portion 21b. The depth Tpb2 from the surface of the barrier layer 37 of the second embedded portion 21b is 122 mm.

  Since the thickness of the barrier layer 37 is 260 mm, the bottom of the second embedded portion 21 b is located in the barrier layer 37. That is, the second gate electrode 21 forms a Schottky junction with the barrier layer 37.

  The second FET 20 is a D-type HEMT (D-FET), and the pinch-off voltage Vp2 is, for example, -0.8V. The pinch-off voltage Vp2 of the second FET 20 is determined by the distance d2 from the bottom of the second embedded portion 21b to the surface of the second electron supply layer 36. That is, the second FET 20 is set to the pinch-off voltage Vp2 of −0.8 V by setting the distance d2 to 138 mm.

  The first gate electrode 11 and the second gate electrode 21 are both provided on the same plane of the same barrier layer 37. The first FET (E-type HEMT) 10 and the second FET (D-type HEMT) 20 of the first embodiment are integrated on the same substrate 30 and have different pinch-off voltages Vp1 and Vp2. However, the first gate electrode 11 and the second gate electrode 21 are provided on the same plane of the same barrier layer without repeating recess etching or selective etching of the semiconductor layer when forming them.

  The first gate electrode 11 and the second gate electrode 21 are provided by depositing a gate metal layer on the barrier layer 37 and diffusing Pt. As described above, the HEMT characteristics can be improved by using a buried gate structure in which a part of the lowermost layer metal of the first gate electrode 11 (same as the second gate electrode 21) is buried in the substrate surface. This is because the bottom end of the first embedded portion 11b (second embedded portion 21b) is round as shown in the figure. Accordingly, the electric field strength is dispersed when a reverse bias is applied to the gate electrode, as compared with a gate electrode (for example, Ti / Pt / Au) that does not have a buried gate structure with a sharp bottom end. That is, the buried gate structure is because the maximum electric field strength is weakened and the breakdown voltage is significantly increased.

  Here, when Pt is embedded in the surface of the InGaP layer, there is a problem that Pt is abnormally diffused laterally (in the horizontal direction of the substrate 30) on the surface of the InGaP layer and the gate breakdown voltage is deteriorated. However, since the barrier layer of the first embodiment is an AlGaAs layer, an abnormal diffusion of Pt does not occur even when heat treatment for embedding Pt is performed, and a good gate breakdown voltage is obtained.

  In the HEMT, it is most important how to suppress the production variation in the values of the pinch-off voltages Vp1 and Vp2 for both the E-type HEMT (E-FET) and the D-type HEMT (D-FET). The integrated circuit device of the first embodiment shown in FIG. 1 has a structure that suppresses these production variations.

  Hereinafter, this will be described, but parts common to the first FET (E-type HEMT) 10 and the second FET (D-type HEMT) 20 will be described generically.

  As described above, the pinch-off voltage Vp is determined by the distance d from the bottom of the embedded Pt (embedded portion b) to the surface of the second electron supply layer 37. The depth of the buried portion b (Pt buried depth) Tpb is determined by the deposited film thickness Tpa of Pt. That is, the deposition film thickness Tpa of Pt and the embedding depth Tpb of Pt have a certain correlation.

  FIG. 2 is a diagram showing the correlation between the deposited film thickness Tpa of Pt and the buried depth Tpb of Pt when a predetermined heat treatment is performed, and the Pt film thickness when the deposited film thickness Tpa of Pt is 40 to 150 mm. It is an experimental result which measured embedding depth Tpb. The horizontal axis represents the deposition film thickness Tpa (Å) of Pt, and the vertical axis represents the embedding depth Tpb (Å) of Pt.

  From this figure, in the Li region where the Pt vapor deposition film thickness Tpa is about 100 to 110 mm or less, the embedding depth Tpb is always 2.4 times the vapor deposition film thickness Tpa and shows linear characteristics. On the other hand, in the Sa region where the Pt vapor deposition film thickness Tpa is about 100 to 110 mm or more, the Pt embedding depth Tpb is shallower than 2.4 times the Pt vapor deposition film thickness Tpa, and the Pt vapor deposition film thickness Tpa is increased. As a result of experiments, it was found that the embedding depth Tpb of Pt was saturated. That is, when the Pt vapor deposition film thickness Tpa = 150 mm (Pt embedding depth Tpb = 317 mm), the Pt vapor deposition film thickness Tpa was increased further, and the Pt embedding depth Tpb did not increase. .

  FIG. 3 shows the correlation coefficient R1 in the correlation between the increase in the Pt vapor deposition film thickness Tpa and the increase in the Pt embedding depth Tpb (inclination of the correlation line in FIG. 2: Pt against the increase in the Pt vapor deposition film thickness Tpa. It is a figure which shows the relationship between the increase ratio of the embedding depth Tpb) and the vapor deposition film thickness Tpa of Pt.

  The correlation coefficient R1 is a constant value of 2.4 in the Li region, but starts to decrease from 2.4 in the Sa region and becomes 0 in the vicinity of Tpa = 150Å.

  On the other hand, Pt vapor deposition requires considerably large power in vapor deposition with an EB vapor deposition machine. This means that vapor deposition of Pt that is too thin has poor film thickness controllability. That is, when the Pt vapor deposition film thickness is made thinner than 40 mm, the vapor deposition itself is completed in a few seconds, for example. Immediately after the start of vapor deposition, the rate of vapor deposition film thickness (film thickness deposited in 1 second) is unstable, and the variation in the vapor deposition film thickness is increased.

  On the other hand, the production variation (hereinafter referred to as ΔTpa) of the vapor deposition film thickness Tpa of Pt by the vapor deposition machine is ± 10% of the vapor deposition film thickness Tpa. That is, the following formula 1 is established.

ΔTpa = 0.1 × Tpa (Formula 1)
That is, ΔTpa increases as the deposited film thickness Tpa of Pt increases.

  2 and FIG. 3 does not depend on the semiconductor layer (epitaxial layer) structure of the substrate 30.

  The correlation coefficient R1 affects the variation (hereinafter referred to as ΔTpb) in the Pt embedding depth Tpb. That is, the relationship of the following formula 2 is established.

ΔTpb = ΔTpa × R1 (Formula 2)
Then, substituting equation 1 into equation 2, the following equation 3 is obtained.

ΔTpb = 0.1 × Tpa × R1 (Formula 3)
The pinch-off voltage Vp is determined by the distance d from the bottom of the gate electrode to the second electron supply layer surface 37. That is, the variation (hereinafter referred to as ΔVp) of the pinch-off voltage Vp increases as the variation (hereinafter referred to as Δd) of the distance d from the bottom of the buried portion b to the surface of the second electron supply layer 36 increases. Δd increases as ΔTpb increases.

  FIG. 4 is a diagram showing the correlation between the Pt vapor deposition film thickness Tpa and ΔTpb. FIG. 4 shows the relationship obtained from FIG.

  As shown in FIG. 4, since the correlation coefficient R1 is constant (2.4) and large in the Li region (see FIG. 3), ΔTpb increases rapidly as the Pt deposition film thickness Tpa increases.

  On the other hand, when entering the Sa region, the correlation coefficient R1 becomes smaller rapidly than 2.4 (see FIG. 3), so that the effect of increasing ΔTpb due to the increase in the Pt vapor deposition film thickness Tpa is completely negated. That is, in the Sa region, ΔTpb decreases rapidly as the Pt vapor deposition film thickness Tpa increases, and becomes 0 near the Pt vapor deposition film thickness Tpa = 150 mm.

  Also, the correlation of FIG. 4 does not depend on the epitaxial structure.

  When the production variation of the Pt vapor deposition film thickness is ± 10%, the upper limit of the Pt vapor deposition film thickness is 170 mm. Even if the Pt vapor deposition film thickness is 170 mm and the film thickness is reduced by 10% due to production variations, the vapor deposition film thickness is 153 mm. This is because the embedding depth Tpb at that time is the maximum value of 317 mm, and has not changed since the Pt vapor deposition film thickness is 170 mm.

  That is, according to FIG. 4, in the Sa region, since the Pt vapor deposition film thickness Tpa is thick, the variation ΔTpa is large, but since the correlation coefficient R1 can be reduced, ΔTpb can be reduced. Further, in the Li region, although the correlation coefficient R1 is large, it can be seen that ΔTpa can be reduced because ΔTpa can be reduced by sufficiently reducing the Pt vapor deposition film thickness Tpa.

  In the first embodiment, the pinch-off voltage Vp1 of the first FET 10 is a positive potential, for example, 0.25V, and the pinch-off voltage Vp2 of the second FET 20 is a negative potential, for example, -0.8V. Therefore, it is necessary to form the bottom of the first gate electrode 11 (first buried portion 11b) of the first FET 10 in a portion deeper than the bottom of the second gate electrode 21 (second buried portion 21b) of the second FET 20.

  For this purpose, the depth of the first embedded portion 11b (Pt embedded depth Tpb1) needs to be deeper than the depth of the second embedded portion 21b (Pt embedded depth Tpb2). Furthermore, in the first embodiment, the metal vapor deposition surfaces of the first gate electrode 11 and the second gate electrode 21 are on the same plane of the same barrier layer 37. Therefore, the Pt vapor deposition film thickness Tpa1 of the first gate electrode 11 is made larger than the Pt vapor deposition film thickness Tpa2 of the second gate electrode 21. As a result, the position of the bottom portion of the embedded portion b is varied to realize different pinch-off voltages Vp.

  In the present embodiment, it is possible to provide an integrated circuit device in which the first FET 10 and the second FET 20 are designed based on the relationship between the Pt vapor deposition film thickness Tpa and the pinch-off voltage Vp, and ΔVp is both reduced.

  At this time, the Pt vapor deposition film thickness Tpa1 of the first gate electrode 11 is a correlation between the ratio of the increase in the Pt deposition depth Tpb into the semiconductor layer with respect to the increase in the Pt vapor deposition film thickness Tpa and the Pt vapor deposition film thickness Tpa. The thickness at which the correlation coefficient R1 begins to decrease is greater than or equal to the thickness.

  Specifically, a structure is adopted in which the Pt vapor deposition film thickness Tpa1 of the first gate electrode 11 is increased to about 100 to 110 mm or more and the Pt vapor deposition film thickness Tpa2 of the second gate electrode 21 is thinned (100 mm or less).

  Hereinafter, the relationship between the Pt vapor deposition film thickness Tpa and the pinch-off voltage Vp will be described in detail, and a specific Pt vapor deposition film thickness Tpa capable of reducing ΔVp in the epitaxial structure shown in FIG. 1 will be described.

  First, FIGS. 5 and 6 show the correlation between the distance d from the surface of the second electron supply layer 37 to the bottom of the buried portion b and the pinch-off voltage Vp. FIG. 6 is an enlarged view of a region where the distance d is negative in FIG.

  5 and 6 show the results of estimating the pinch-off voltage Vp when the Pt vapor deposition film thickness Tpa is changed in the design of the epitaxial structure substrate 30 shown in FIG. The horizontal axis is the distance d (Å) from the surface of the second electron supply layer 37 to the bottom of the buried portion b, and the vertical axis is the pinch-off voltage Vp (V).

  This correlation is obtained in the structure as shown in FIG. That is, it can be obtained by optimally designing the semiconductor layer (epitaxial structure). By designing this correlation, a desired pinch-off voltage Vp can be obtained with an appropriate Pt vapor deposition film thickness Tpa.

In other words, FIG. 1 shows characteristics that do not depend on the structure of the epitaxial layer of the substrate 30, while FIG. 5 shows characteristics that depend on the structure of the epitaxial layer (the barrier layer 37 and the semiconductor layer below the barrier layer 37). That is, here, the thickness of the barrier layer 37 is 260 mm, the impurity concentration of the second electron supply layer 36 is 2.6 × 10 ¹⁸ cm ⁻³ , and the thickness is 120 mm.

  In FIG. 5, when the distance d from the surface of the second electron supply layer 36 to the bottom of the buried portion b is positive, the bottom of the buried portion b is located in the barrier layer 37. On the other hand, when the distance d is negative, the bottom of the buried part b is located inside the second electron supply layer 36.

  The pinch-off voltage Vp1 required for the first FET 10 (E-type HEMT) and the pinch-off voltage Vp2 required for the second FET 20 (D-type HEMT) are, for example, 0.25 V and −0.8 V, respectively, and are indicated by broken lines. . That is, a desired pinch-off voltage Vp can be obtained by selecting the distance d between the intersections of the broken line and the correlation line.

  The distance d from the surface of the second electron supply layer 37 to the bottom of the buried portion b and the pinch-off voltage Vp have a correlation. The correlation coefficient R2 of the correlation between the ratio of the increase in the pinch-off voltage Vp to the increase in the distance d from the surface of the second electron supply layer 37 to the bottom of the buried portion b and the distance d (the slope of the correlation line in FIG. 6: distance) The ratio of the increase in the pinch-off voltage Vp to the increase in d) varies with the distance d.

  When the bottom of the buried portion b is located in the barrier layer 37, that is, in a region where the distance d is positive, the pinch-off voltage Vp changes linearly with respect to the change of the distance d.

  On the other hand, when the bottom of the buried portion b is in the second electron supply layer 36, that is, in a region where the distance d is negative, the change in the pinch-off voltage Vp with respect to the change in the distance d is nonlinear. In that case, the value of the distance d can be divided into three regions, an a region, a b region, and a c region.

  Referring to the enlarged view of FIG. 6, region a is a region where the absolute value of distance d is the smallest, and the absolute value of correlation coefficient R2 is smaller than the absolute value of correlation coefficient R2 in a linear region where d is positive. .

  The b region has a larger absolute value of the distance d than the a region and is adjacent to the a region. In the region b, the absolute value of the correlation coefficient R2 is very large, and the distance d is larger than the absolute value of the correlation coefficient R2 in the positive linear region. Further, the absolute value of the correlation coefficient R2 in the b region is twice or more the absolute value of the correlation coefficient R2 in the a region.

  The area c is an area where the absolute value of d is larger than that of the area b and is adjacent to the area b. In the area c, the absolute value of the correlation coefficient R2 is small, and the distance d is smaller than the absolute value of the correlation coefficient in the positive linear area.

  The tendency of this correlation line (the tendency that the distance d changes linearly in a positive region and the regions a to c exist in a region where the distance d is negative) is a universal tendency that holds for the entire HEMT. That is, specific numerical values are not limited to those shown in FIG. 5, but vary depending on the epitaxial structure.

  That is, here, the epitaxial structure is designed so that the correlation line equation becomes Vp = −0.0073d + 0.215 in the region where the distance d is positive. That is, the correlation coefficient R2 was determined to be −0.0073 by the optimum design of the epitaxial structure as shown in FIG. Further, the Vp intercept of the correlation equation was determined to be 0.215 V based on the relationship with the thickness of the barrier layer 37.

  Specifically, the region a is a region where the distance d is 0 to −38 °, and the correlation coefficient R2 is smaller than the absolute value (0.073) of the correlation coefficient R2 in the linear region where the distance d is positive. 0.0044.

  The region b is a region where the distance d is from −38 to −62 inches, and the correlation coefficient R2 is −0.0104.

  The region c is a region where the distance d has an absolute value larger than −62 mm, and the correlation coefficient R2 is −0.0055.

  FIG. 7 is a table in which the absolute value of the correlation coefficient R2 is read from FIGS. 5 and 6 and compared for each region of the distance d.

  ΔVp (variation in pinch-off voltage Vp) increases as the absolute value of correlation coefficient R2 increases. Therefore, in FIG. 7, as the direction in which ΔVp decreases, the case where the absolute value of the correlation coefficient R2 is small is indicated by ◯, and the case where it is large is indicated by ×.

  That is, ΔVp increases in the case where the bottom portion of the buried portion b is in the barrier layer 37 and in the b region in the second electron supply layer 36. On the other hand, when the position of the bottom of the buried portion b is in the a region and the c region in the second electron supply layer 36, ΔVp can be reduced.

  Since the correlation coefficient R2 is negative from FIGS. 5 and 6, the following equation 4 is established when the variation of the distance d is Δd.

ΔVp = Δd × | R2 | (Formula 4)
Here, the relationship between the distance d and the embedding depth Tpb of Pt is as shown in the following Expression 5 with reference to FIG.

d = thickness of the barrier layer 37−Tpb (Formula 5)
Then, the following formula 6 is established from the formula 5.

Δd = ΔTpb (Formula 6)
Next, ΔVp will be described.

  First, when the relationship between ΔVp and ΔTpb is obtained from Equation 4 and Equation 6, the following Equation 7 is obtained.

ΔVp = ΔTpb × | R2 | (Formula 7)
Then, from Equation 3 and Equation 7, the relationship between ΔVp and the Pt vapor deposition film thickness Tpa is as in Equation 8 below.

ΔVp = 0.1 × Tpa × R1 × | R2 | (Formula 8)
That is, it can be seen from Equation 8 that any one of Tpa, R1 and | R2 | can be reduced in order to reduce ΔVp.

  The pinch-off voltage Vp is determined by the distance d and the epitaxial structure below the barrier layer 37. The distance d is determined by the Pt embedding depth Tpb and the barrier layer 37 thickness, and the embedding depth Tpb is determined by the Pt vapor deposition film thickness Tpa. That is, the necessary Pt vapor deposition film thickness Tpa can be obtained by selecting the distance d at which a desired pinch-off voltage Vp is obtained in FIG. Parameters for associating the above-described characteristics of the first FET 10 and the second FET 20 so that the respective pinch-off voltages Vp1 and Vp2 of the first FET 10 and the second FET 20 and their variations ΔVp1 and ΔVp2 become predetermined values. The correlation coefficient R2 is determined.

  In this way, by using the correlation of FIG. 5, the distance d that can reduce ΔVp in the epitaxial structure shown in FIG. 1 is obtained, and the Pt vapor deposition film thickness Tpa corresponding to the distance d is taken into account the variation ΔTpa. Can be obtained.

  A method for designing the structure shown in FIG. 1 will be specifically described.

  Here, ΔVp (hereinafter referred to as ΔVp1) of the first FET 10 (E-FET) and ΔVp (hereinafter referred to as ΔVp2) of the second FET 20 (D-FET) need to be within ± 0.1V.

  First, the design of ΔVp2 of the second FET 20 will be described. As described above, the pinch-off voltage Vp2 of the second FET 20 is, for example, -0.8V.

  From FIG. 5, the distance d2 (139Å) at which the pinch-off voltage Vp2 of the second FET 20 (D-FET) can be obtained is in the linear region in correlation with the pinch-off voltage Vp2. That is, the absolute value of the correlation coefficient R2 is constant and large (FIG. 7). Thus, in order to reduce the pinch-off voltage variation ΔVp2 of the second FET 20 when the correlation coefficient R2 is constant, ΔTpb needs to be reduced from Equation 7.

  5, the distance d2 at which the pinch-off voltage Vp2 of the second FET 20 can be obtained is larger than the distance d1 (−14 （) at which the pinch-off voltage Vp1 of the first FET 10 can be obtained. That is, since the gate electrodes 11 and 21 of the first FET 10 and the second FET 20 are formed on the same barrier layer 37 surface, the Pt burying depth Tpb2 of the second FET 20 is equal to the Pt burying depth of the first FET 10 from Equation 5. It is necessary to make it smaller than Tpb. From FIG. 2, it is necessary to make the Pt vapor deposition film thickness Tpa2 of the second FET 20 smaller than the vapor deposition film thickness Tpa1 of the first FET 10.

  Further, as shown in FIG. 4, for the FET having a small Pt vapor deposition film thickness Tpa, ΔTpb can be reduced as the Pt vapor deposition film thickness Tpa is small.

  Therefore, the Pt vapor deposition film thickness Tpa2 of the gate electrode 21 of the second FET 20 is set as small as possible.

  That is, the Pt vapor deposition film thickness Tpa2 of the second FET 20 is desirably about 40 to 60 mm. In the first embodiment, for example, Vp2 = −0.8 V is realized by setting the distance d1 = 139 mm. Since the Pt embedding depth Tpb1 is obtained from the distance d1 by Expression 5, the corresponding Pt vapor deposition film thickness Tpa1 can be obtained from FIG. Specifically, the Pt vapor deposition film thickness Tpa2 in the case of the distance d1 = 139 mm is 51 mm, which is a value within the range (40 mm to 60 mm) of the Pt vapor deposition film thickness Tpa2 where ΔVp2 becomes small.

  Next, the design of ΔVp1 of the first FET 10 will be described. As described above, the pinch-off voltage Vp1 of the first FET 10 is, for example, 0.25V, and the difference from the pinch-off voltage Vp2 (−0.8V) of the second FET 20 is 1.05V.

  Thus, in order to obtain the difference between the pinch-off voltages Vp1 and Vp2 of 1.05V, it is necessary to take the difference between the Pt embedding depths Tpb1 and Tpb2 of the first FET 10 and the second FET 20 by 1.05V. For this purpose, it is necessary to take 1.05 V of the difference between the Pt vapor deposition film thicknesses Tpa1 and Tpa2 of the first FET 10 and the second FET 20, respectively.

  That is, the Pt vapor deposition film thickness Tpa1 of the first FET 10 is made larger than the Pt vapor deposition film thickness Tpa2 of the second FET 20.

  In order to reduce ΔVp1, the absolute value of the correlation coefficient R1 or the correlation coefficient R2 is desirably reduced from the equation 8 because the Pt vapor deposition film thickness Tpa1 is increased by the above amount.

  In the first embodiment, both the absolute values of the correlation coefficient R1 and the correlation coefficient R2 are reduced. That is, in FIG. 1, the Pt vapor deposition film thickness Tpa1 is set in the range of the Sa region, and the distance d1 in FIGS. 5 and 6 is set in the range of the region a.

  Here, as described above, in order to obtain a desired pinch-off voltage Vp from the correlation shown in FIG. 5, the epitaxial structure needs to be adjusted appropriately.

  That is, the epitaxial structure is such that the position of the boundary between the second electron supply layer 36 and the barrier layer 37 in FIG. 5 substantially coincides with the position of the Pt burying depth Tpb where the Sa region starts in FIG. By doing in this way, Sa area | region of Pt vapor deposition film thickness Tpa and a area | region of distance d can be piled up reliably. As a result, a distance d that achieves a desired pinch-off voltage Vp is obtained on the condition that ΔVp can be reduced based on the correlation shown in FIG. Therefore, since the embedding depth Tpb is obtained from the distance d, the corresponding Pt vapor deposition film thickness Tpa can be obtained.

  Specifically, the position of Tpb = 260Å (Tpa = 108Å) in FIG. 2 is set to the distance d = 0 in FIG. That is, the thickness of the barrier layer 37 was 260 mm. Since each of the Sa region and the a region has a width, when the Sa region and the a region are overlapped, the thickness of the barrier layer 37 is not necessarily matched to 260 mm.

  Then, the Pt buried depth Tpb1 for obtaining the pinch-off voltage Vp1 = 0.25V of the first FET 10 is located in the Sa region, and the Pt vapor deposition film thickness Tpa2 of the second FET 20 is 40 to 60 mm, as described above. The impurity concentration and thickness of the second electron supply layer 36 are set so that the pinch-off voltage Vp2 = −0.8 V is obtained when the Pt buried depth Tpb2 is 96 to 144 Å (Tpb = 2.4 Tpa from the Li region in FIG. 2). Set.

Specifically, the impurity concentration of the second electron supply layer 36 was 2.6 × 10 ¹⁸ cm ⁻³ and the thickness was 120 mm. Since the Sa region has a width and the Pt buried depth Tpb2 (96 to 144 mm) has a width of 48 mm, the impurity concentration and thickness of the second electron supply layer 36 are set to 2.6 × 10 ¹⁸ cm ⁻³ and 120 mm. It is not necessary to set the value to exactly match.

  In this way, the pinch-off voltage Vp1 = 0.25V is secured in the region a where the distance d is negative, and the condition that the pinch-off voltage Vp2 = −0.8V is secured at Tpb2 = 96 to 144１４ (distance d2 = 116 to 164Å). There are several correlation lines having different slopes (correlation coefficient R2) and intercepts. That is, as described above, the correlation line in FIG. 5 is not limited to that shown in the figure, and the slope of the correlation line (correlation coefficient R2) and the intercept depending on the impurity concentration and thickness of the second electron supply layer 36 according to device design requirements. Adjust.

  In the first embodiment, as shown in FIG. 5, the correlation coefficient R2 is set to −0.0073, the intercept is set to 0.215, and the correlation formula of Vp = −0.0073d + 0.215 is used as the correlation line formula. It was determined.

  When the value of the intercept is changed, the correlation equation moves in parallel (the positional relationship between the distance d and the correlation line as a shape moves). Therefore, the value of the intercept is determined by the relationship between the distance d and the thickness of the barrier layer 37 that is directly related to the distance d.

  The parameters that determine the correlation coefficient R2 include the impurity concentration and thickness of the second electron supply layer 36. Since the values of the a region and the appropriate distance d have different widths, it is not necessary to set the correlation coefficient R2 to a value that completely matches -0.0073. Further, if the product and concentration of the impurities of the second electron supply layer 36 are the same, the same correlation coefficient R2 can be obtained, so that the range of each setting further increases.

  Further, the value of the pinch-off voltage Vp2 is not limited to -0.8 V, and may be other values, which are the impurity concentration and thickness of the second electron supply layer 36 according to the setting of each pinch-off voltage. The pinch-off voltage Vp1 is not limited to 0.25 V, and may be other values. The impurity concentration and thickness of the second electron supply layer 36 are set in consideration of the set value of the pinch-off voltage Vp2.

  By setting the parameters of the epitaxial layer as described above and finely adjusting the Pt vapor deposition film thicknesses Tpa1 and Tpa2, the desired pinch-off voltages Vp1 and Vp2 can be reliably obtained.

  In the first embodiment, the epitaxial structure is adjusted as described above so that the pinch-off voltage Vp1 = 0.25 V is realized at a distance d1 = −14 mm, for example, as a condition for reducing ΔVp1. And Pt vapor deposition film thickness Tpa1 = 117? Was obtained from the distance d1.

  The parameters that determine the correlation coefficient R2 are not only the impurity concentration and thickness of the second electron supply layer 36, but actually the impurity concentration and thickness of the first electron supply layer 33, the thickness of the channel layer 35, and In (indium). ) The composition can also be used as a parameter for determining the correlation coefficient R2. That is, all the components of the epitaxial structure below the barrier layer 37 can be used as parameters for determining the correlation coefficient R2.

  Here, in FIG. 5, the absolute value of the correlation coefficient R <b> 2 is also small when the bottom of the buried part b is in the c region of the second electron supply layer 36.

  However, the c region is the deepest part of the second electron supply layer 36. In the case of the first embodiment, as shown in FIGS. 5 and 6, when the position of the bottom of the buried portion b is the c region, the pinch-off voltage Vp is 0.6 V or more. The pinch-off voltage Vp of an E-type HEMT (E-FET) used for GaAs MMIC is often set to about 0 to 0.3V. When the pinch-off voltage Vp is set to 0.3 V or more, the current that flows at the time of ON becomes very small. In other words, it is necessary to increase the gate width accordingly, and the area of the FET becomes large, which increases the chip cost. Therefore, it is rare to set the position of the bottom of the embedded portion b in the region c.

  When the position of the bottom of the buried part b is in the barrier layer 37, the correlation between the distance d from the bottom of the buried part b to the surface of the second electron supply layer 36 and the pinch-off voltage Vp is linear. However, in detail, when the bottom of the buried portion b is located in a portion very close to the surface of the second electron supply layer 36 in the barrier layer 37, the alignment may not be maintained. That is, the correlation coefficient R2 of the correlation between the distance d and the pinch-off voltage Vp is smaller in absolute value than the correlation coefficient R2 in the linear region where the distance d is positive, and the position of the bottom of the embedded portion b is the second electron supply layer. In some cases, the correlation coefficient R2 is almost the same as that in the region 36.

  That is, in FIG. 5, the correlation coefficient R2 of the correlation between the distance d and the pinch-off voltage Vp in the region where the distance d is 0 to 10 mm is substantially the same as the correlation coefficient R2 in the region a. Therefore, specifically, the region where the correlation between the distance d and the pinch-off voltage Vp is linear is the region where d ≧ 10Å in FIG.

  8 and 9 are diagrams showing the correlation between the Pt vapor deposition film thickness Tpa and the pinch-off voltage Vp of the first embodiment designed as described above, and FIG. 9 is a partially enlarged view of FIG.

  The horizontal axis is the Pt vapor deposition film thickness Tpa (Å), and the vertical axis is the pinch-off voltage Vp (V). The Li region and Sa region in FIG. 2 are also shown.

  8 and 9 reflect FIGS. 5 and 6 as they are. That is, in the correlation between the Pt vapor deposition film thickness Tpa and the pinch-off voltage Vp, the correlation coefficient R3 varies depending on the Pt vapor deposition film thickness Tpa.

  In the structure of the barrier layer 37 and the semiconductor layer (epitaxial layer) below the barrier layer 37 shown in FIG. 1, the boundary value indicating whether the bottom of the buried portion b is located in the barrier layer 37 or the second electron supply layer 36. Varies depending on the Pt vapor deposition film thickness Tpa. In the present embodiment, the boundary value Pt vapor deposition film thickness Tpa is 108 mm. That is, the bottom of the buried portion b is located in the second electron supply layer 36 when the Pt vapor deposition film thickness Tpa = 108 mm or more, and the bottom of the buried portion b is located in the barrier layer 37 when the thickness is 108 mm or less. And this boundary value was made to correspond substantially with the boundary value (Tpa = 100 to 110 ＝) between the Li region and the Sa region in the correlation (FIG. 2) between the Pt vapor deposition film thickness Tpa and the buried portion b depth Tpb.

  That is, when the Pt vapor deposition film thickness Tpa is in the Li region, since the bottom of the buried portion b is simultaneously in the barrier layer 37, not only the correlation of the Pt vapor deposition film thickness Tpa-Pt buried depth Tpb but also the distance d- The correlation between the pinch-off voltage Vp is also linear, and as a result, the correlation between the Pt deposition film thickness Tpa and the pinch-off voltage Vp is linear.

  The pinch-off voltage Vp1 (0.25V) required for the first FET 10 (E-FET) and the pinch-off voltage Vp2 (-0.8V) required for the second FET 20 (D-FET) are indicated by broken lines. That is, a desired pinch-off voltage Vp can be obtained by selecting the Pt vapor deposition film thickness Tpa at the intersection of the broken line and the correlation line.

  The expression of the correlation of the linear part of Pt vapor deposition film thickness Tpa-pinch-off voltage Vp can be expressed as Vp = 0.0175 Tpa-1.68. That is, the correlation coefficient R3 of Pt vapor deposition film thickness Tpa-pinch-off voltage Vp in the linear region is 0.0175. With this correlation coefficient R3, the relationship between the variation ΔVp in the pinch-off voltage Vp and the variation ΔTpa in the Pt vapor deposition film thickness Tpa is expressed by the following equation (9).

ΔVp = ΔTpa × R3 (Formula 9)
Further, from Expression 2, Expression 4, and Expression 6, the relationship between ΔVp and ΔTpa is as in Expression 10 below.

ΔVp = ΔTpa × R1 × | R2 | (Formula 10)
Therefore, the following Expression 11 is established from Expression 9 and Expression 10.

R3 = R1 × | R2 | (Formula 11)
On the other hand, when the bottom of the buried portion b is in the second electron supply layer 36 and the Pt vapor deposition film thickness Tpa is in the Sa region, not only the correlation of the Pt vapor deposition film thickness Tpa-Pt buried depth Tpb, The distance d-pinch-off voltage Vp correlation is also non-linear, and the change in the pinch-off voltage Vp with respect to the change in the Pt deposition film thickness Tpa is non-linear. As in FIG. 5, the value of the Pt vapor deposition film thickness Tpa can be divided into three regions: a region, b region, and c region.

  Referring to the enlarged view of FIG. 9, a region is a region where the Pt vapor deposition film thickness Tpa is the smallest when the bottom of the buried portion b is in the second electron supply layer 36, and the correlation coefficient R3 is the bottom of the buried portion b. Is much smaller than the correlation coefficient R3 (0.0175) in the case of the barrier layer 37. This is because when the Pt vapor deposition film thickness Tpa is in the a region in the first embodiment, the Pt vapor deposition film thickness Tpa is simultaneously in the Sa region, and therefore both the absolute value of the correlation coefficient R2 and the correlation coefficient R1 are small. As a result, the correlation coefficient R3 has become extremely small from Equation 11. Specifically, the a region is a region where the Pt vapor deposition film thickness Tpa is from 108 to 130 mm, and the correlation coefficient R3 is 0.0075.

  The b region has a larger Pt vapor deposition film thickness Tpa than the a region and is adjacent to the a region. The b area has a very large correlation coefficient R3, and the correlation coefficient R3 of the b area is more than twice the correlation coefficient R3 of the a area. Specifically, the b region is a region where the Pt vapor deposition film thickness Tpa is 130 to 140 mm and the correlation coefficient R3 is 0.015.

  The c region has a Pt vapor deposition film thickness Tpa larger than that of the b region and is adjacent to the b region. The region c has a small correlation coefficient R3 and is smaller than the correlation coefficient R3 when the Pt vapor deposition film thickness Tpa is in the linear region. Specifically, the region c is a region having a Pt vapor deposition film thickness Tpa of 140 Å or more, and the correlation coefficient is 0.005.

  Here, also in FIG. 8, when the pinch-off voltage Vp of the first FET 10 is Vp = 0.25V, the Pt vapor deposition film thickness Tpa1 is 117 mm in the Sa region and the a region. That is, it shows that the target value of the design method using the correlation of FIG. 5 matches the value of the design result shown in FIGS. Further, ΔVp1 (variation of pinch-off voltage Vp) in this Pt vapor deposition film thickness Tpa1 was ± 0.088V, and the target ± 0.1V or less was achieved.

  In addition, the Pt vapor deposition film thickness Tpa2 when the pinch-off voltage Vp of the second FET 20 is −0.8 V is 51 mm in the Li region. Further, ΔVp2 in the Pt vapor deposition film thickness Tpa2 is ± 0.089V, and the target ± 0.1V or less is achieved.

  Thus, the structure of the semiconductor layer is the structure of the barrier layer 37 and the semiconductor layer below the barrier layer 37 shown in FIG. 1, and the Pt vapor deposition film thickness Tpa1 of the first FET 10 is Pt in the range of the Sa region and the a region. The vapor deposition film thickness Tpa is set, and the Pt vapor deposition film thickness Tpa2 of the second FET 20 is set as small as possible. Thereby, the first FET 10 and the second FET 20 can be formed on the same substrate, and both ΔVp can be set to the target ± 0.1 V or less.

  From the above, the relationship between the first FET 10 and the second FET 20 and ΔVp will be described.

  First, since the first FET 10 is an E-type HEMT (E-FET), the pinch-off voltage Vp1 generally needs about 0 to 0.3V. In that case, the Pt vapor deposition film thickness Tpa1 is made larger than the Pt vapor deposition film thickness Tpa2 so that the pinch-off voltage Vp1 is, for example, 1.05 V larger than the pinch-off voltage Vp2 (see FIG. 8).

  Since ΔVp becomes larger when the Pt vapor deposition film thickness Tpa is larger from Expression 8, not only the correlation coefficient R1 is reduced by using the Pt vapor deposition film thickness Tpa1 in the Sa region, but also the first embedded portion 11b is formed. By positioning in the region a, the absolute value of the correlation coefficient R2 can be reduced to reduce ΔVp.

  In other words, in the first FET 10, the Pt vapor deposition film thickness Tpa 1 at which a predetermined pinch-off voltage Vp 1 = 0.25 V is obtained is in the range of the Sa region, and the distance d 1 is a value in the range of the a region of the second electron supply layer 36. The structure below the barrier layer 37 and the barrier layer 37 is designed so that

  Thus, even if the Pt vapor deposition thickness Tpa1 is increased, the range of the Sa region is reached, so that the correlation coefficient R1 is reduced, and the increase ratio of the pinch-off voltage Vp1 with respect to the increase in the Pt vapor deposition film thickness Tpa1 having a constant width (correlation) The number R3) becomes smaller. Further, since the Pt vapor deposition thickness Tpa1 falls within the range of the region a, the absolute value of the correlation coefficient R2 becomes small. This also increases the ratio of the increase in the pinch-off voltage Vp1 to the increase in the Pt vapor deposition film thickness Tpa1 with a certain width (correlation) The number R3) is reduced, and the variation ΔVp1 of the pinch-off voltage Vp1 can be significantly suppressed.

  On the other hand, the second FET 20 has a large value because the absolute values of the first correlation coefficient R1 and the second correlation coefficient R2 are in a linear region. However, ΔVp2 can be reduced by sufficiently reducing the value of the Pt vapor deposition film thickness Tpa2 that achieves the pinch-off voltage Vp2 = −0.8V.

  That is, the first gate electrode 11 of the first FET 10 has a correlation coefficient R1 in the correlation between the ratio of the increase in the embedding depth in the semiconductor layer with respect to the increase in the deposition film thickness Tpa1 of Pt and the Pt deposition film thickness Tpa1. The Pt vapor deposition thickness Tpa is defined as the Sa region where the thickness starts to decrease (Pt vapor deposition film thickness Tpa1 is 110 mm or more) and the a region has a small correlation coefficient R3. Specifically, Pt vapor deposition film thickness Tpa1 = 117 mm, and Pt vapor deposition film thickness Tpa2 = 51 mm of the second gate electrode 21 of the second FET 20. As a result, ΔVp of the first FET 10 becomes ± 0.088V, ΔVp of the second FET 20 becomes ± 0.089V, and any ΔVp can be set to a small value of ± 0.1V or less.

  As a point to be noted here, for example, a point of Pt vapor deposition film thickness Tpa = 80 mm is considered as a substantially intermediate point between the Pt vapor deposition film thicknesses Tpa1 and Tpa2. Since the point of the Pt vapor deposition film thickness Tpa = 80Å is a linear region, the pinch-off voltage Vp at that point is −0.28 V by calculation of the pinch-off voltage Vp = 0.175 Tpa−1.68. The ΔTpa at the point of Pt vapor deposition film thickness Tpa = 80 mm is 8%, which is 10% of the Pt vapor deposition film thickness Tpa. Since the correlation coefficient R3 is a linear region, it is 0.0175, which is the same as that for the Pt vapor deposition film thickness Tpa2. And by calculation of 8 × 0.0175 = 0.14, ΔVp at the point of Pt vapor deposition film thickness Tpa = 80 mm is 0.14V. That is, ΔVp at the point of Pt vapor deposition film thickness Tpa = 80 mm is about 1.6 times ΔVp1 and ΔVp2, and does not achieve the target ± 0.1 V or less.

  The reason for this is that the point of Pt vapor deposition film thickness Tpa = 80 mm has a large ΔTpb in FIG. 4, and further the correlation coefficient R2 in the correlation between distance d and pinch-off voltage Vp (FIG. 5) is d = 69 mm in the linear region. This is because ΔVp is increased according to Equation (7).

  In this embodiment, ΔVp of the E-type HEMT (first FET 10) and the D-type HEMT (second FET 20) each having a predetermined pinch-off voltage Vp is set to ± 0.1 V or less. Therefore, for example, ΔVp of an FET having a value of an intermediate pinch-off voltage Vp that is not a predetermined pinch-off voltage Vp may not necessarily achieve the target.

  FIG. 10 is a diagram showing a second embodiment of the present invention.

  The second embodiment is a case where no etching stop layer is provided in the structure of the substrate 30 of the first embodiment. Since the other configuration is the same as that of the first embodiment, the description thereof is omitted.

  When the cap layer 38 is patterned, if the cap layer 38 and the barrier layer 37 (AlGaAs layer) are selectively etched by dry etching, the etching stop layer 39 of the first embodiment is unnecessary.

  Also in this case, the first gate electrode 11 of the first FET 10 has a Pt vapor deposition film thickness Tpa in the region a that is equal to or larger than the thickness at which the correlation coefficient R1 starts to decrease and has a small correlation coefficient R3. Specifically, Pt vapor deposition film thickness Tpa1 = 117 mm, and Pt vapor deposition film thickness Tpa2 = 51 mm of the second gate electrode 21 of the second FET 20. As a result, ΔVp of the first FET 10 becomes ± 0.088 V, ΔVp of the second FET 20 becomes ± 0.089 V, and any ΔVp can be set to a small value.

  FIG. 11 is a diagram illustrating a third embodiment.

  In the third embodiment, the bottom of the first embedded portion 11 b of the first FET 10 does not reach the second electron supply layer 36.

The impurity concentration of the n-type impurity (for example, Si) in the second electron supply layer 36 is, for example, 1.5 × 10 ¹⁸ cm ⁻³ and the thickness is 120 mm.

  The barrier layer 37 is a non-doped AlGaAs layer and has a thickness of 335 mm.

  The gate metal layer constituting the first gate electrode 11 of the first FET 10 is a Pt / Mo vapor deposition metal layer, the Pt vapor deposition film thickness Tpa1 is 131 mm, and the Mo vapor deposition film thickness is 50 mm. The depth Tpb1 of the first embedded portion 11b is 303 mm, and the distance d1 between the bottom of the first embedded portion 11b and the surface of the second electron supply layer 36 is 32 mm. That is, the bottom of the first embedded portion 11 b is located in the barrier layer 37.

  The gate metal layer constituting the second gate electrode 21 of the second FET 20 is a Pt / Mo vapor deposition metal layer, the Pt vapor deposition film thickness Tpa2 is 52 mm, and the Mo vapor deposition film thickness is 50 mm. The depth Tpb2 of the second embedded portion 21b is 125 mm, and the distance d2 between the bottom of the second embedded portion 21b and the surface of the second electron supply layer 36 is 210 mm. That is, the bottom of the first embedded portion 11 b is located in the barrier layer 37.

  Since the other configuration is the same as that of the first embodiment, the description thereof is omitted.

  FIG. 12 is a diagram showing the correlation between the distance d from the surface of the second electron supply layer 36 to the bottom of the embedded portion b and the pinch-off voltage Vp in the third embodiment.

  The correlation between the distance d and the pinch-off voltage Vp is determined by the structure of the barrier layer 37 and the epitaxial layer below the barrier layer 37.

  When the first FET 10 and the second FET 20 are set to a predetermined pinch-off voltage Vp1 (= 0.25V) and a pinch-off voltage Vp2 (= −0.8V), respectively, the distance d1 = 32Å in the first FET 10 and the distance d2 = 210 で は in the second FET 20 .

  As shown in FIG. 12, the correlation is set to the correlation equation Vp = −0.0059d + 0.44. That is, the correlation coefficient R2 is set to -0.0059 constantly.

  Although not shown in FIG. 12, the a region, the b region, and the c region actually exist also in the epitaxial structure of the third embodiment. However, since the thickness of the barrier layer 37 is set to be larger than 317 mm which is the maximum depth Tpb of the buried portion b, the bottom of the buried portion b is not located in the a region, the b region, and the c region. The display of the a region, the b region, and the c region is omitted.

  As in the third embodiment, when both the bottom of the first embedded portion 11b and the bottom of the second embedded portion 21b do not reach the second electron supply layer 36 and are located in the barrier layer 37, the first FET 10 A design in which both pinch-off variations ΔVp1 and ΔVp2 of the second FET 20 are within ± 0.1V will be described.

  In Equation 7, since | R2 | is a constant value as described above, ΔVp1 and ΔVp2 of the first FET 10 and the second FET 20 both depend only on ΔTpb. Here, the correlation of the Pt vapor deposition film thickness Tpa−ΔTpb shown in FIG. 4 does not depend on the epitaxial structure.

  The pinch-off voltage Vp1 of the first FET 10 is 0.25V, for example, and the pinch-off voltage Vp2 of the second FET 20 is −0.8V, for example. Thus, in order to obtain the difference between the pinch-off voltages Vp1 and Vp2 of 1.05V, it is necessary to take the difference between the Pt embedding depths Tpb1 and Tpb2 of the first FET 10 and the second FET 20 by 1.05V. For this purpose, it is necessary to take 1.05 V of the difference between the Pt vapor deposition film thicknesses Tpa1 and Tpa2 of the first FET 10 and the second FET 20, respectively.

  First, the design of ΔVp2 of the second FET 20 will be described.

  From FIG. 4, ΔTpb can be reduced as the Pt vapor deposition film thickness Tpa2 of the second FET 20 having a small Pt vapor deposition film thickness Tpa is small. Therefore, the Pt vapor deposition film thickness Tpa2 of the gate electrode of the second FET 20 is set as small as possible.

  That is, the Pt vapor deposition film thickness Tpa2 of the second FET 20 is desirably about 40 to 60 mm. In the third embodiment, for example, the semiconductor layer (epitaxial structure) is adjusted so that Vp2 = −0.8 V at a distance d2 = 210Å and a Pt vapor deposition film thickness Tpa2 = 52Å.

  Next, the design of ΔVp1 of the first FET 10 will be described.

As described above, the Pt vapor deposition film thickness Tpa1 of the first FET 10 is set larger than the Pt vapor deposition film thickness Tpa2 of the second FET 20 so that the pinch-off voltage Vp1 is, for example, 1.05 V larger than the pinch-off voltage Vp2. As shown in FIG. 4, ΔTpb can be reduced by setting the Pt vapor deposition film thickness Tpa1 of the first FET 10 having the larger Pt vapor deposition film thickness Tpa to a thickness close to 150 mm in the Sa region exceeding 110 mm. Recognize.
In the third embodiment, for example, the semiconductor layer (epitaxial structure) is adjusted so that Vp1 = 0.25 V at a distance d1 = 32 mm and a Pt vapor deposition film thickness Tpa1 = 131 mm.

  FIG. 13 is a diagram illustrating a correlation between the Pt vapor deposition film thickness Tpa and the pinch-off voltage Vp according to the third embodiment.

  Since the bottom of the embedded portion b is not located in the a region, b region, and c region omitted in FIG. 12, the a region, b region, and c region are not displayed in FIG. That is, in the case of the third embodiment, the bottom of the buried portion b in FIG. 13 is located in the barrier layer 37 in the entire range shown in the graph.

  The correlation shown in FIG. 2 is established regardless of the structure of the epitaxial layer of the substrate 30, and the saturation point is (Tpa, Tpb) = (150, 317). That is, even when the Pt vapor deposition film thickness Tpa is set to 150 mm or more, the Pt embedding depth Tpb does not exceed 317 mm, and the maximum value is 317 mm.

  Therefore, when the thickness of the barrier layer 37 is 317 mm or more (here, 335 mm), even if the Pt vapor deposition film thickness Tpa is increased to, for example, 1000 mm, the Pt embedding depth Tpb is increased only to 317 mm. Never reach the territory. Therefore, as shown in FIG. 8, the a region exists in the correlation between the Pt deposition thickness Tpa and the pinch-off voltage Vp only when the thickness of the barrier layer 37 is less than 317 mm.

  Also in the third embodiment, the Pt vapor deposition film thickness Tpa has a Sa region and a Li region with the Pt vapor deposition film thickness Tpa = about 100 to 110 mm as a boundary.

  As a result of designing the correlation equation of the distance d-pinch-off voltage Vp in FIG. 12, the correlation of the Li region is Vp = 0.142 Tpa−1.54. On the other hand, the slope of the point (correlation coefficient R3) at which the pinch-off voltage Vp1 = 0.25V is achieved in the Sa region is 0.0065. This will be described.

  If the thickness of the barrier layer 37 shown in FIG. 11 (335 mm) is present, the Pt vapor deposition film thickness Tpa1 (= 131 cm) at which the first FET 10 can obtain a predetermined pinch-off voltage Vp1 is located in the Sa region, and the Pt vapor deposition film thickness Tpa1 The increase ratio (correlation coefficient R3) of the pinch-off voltage Vp1 with respect to the increase decreases.

  FIG. 14 shows the relationship between the Pt vapor deposition film thickness Tpa and the correlation coefficient R3. As shown in FIG. 14, when the Pt vapor deposition film thickness Tpa1 is 131 mm, the correlation coefficient R3 is sufficiently small as 0.0065.

  FIG. 15 shows the correlation between the Pt deposition film thickness Tpa and the pinch-off voltage variation ΔVp, which is the result of FIG.

  According to FIG. 15, by setting the Pt vapor deposition film thickness Tpa1 to 131 mm, the variation ΔVp of the pinch-off voltage Vp1 becomes ± 0.085V. That is, even if the Pt vapor deposition film thickness Tpa1 is thick, ΔVp can be significantly suppressed.

  On the other hand, the second FET 20 has a Pt vapor deposition film thickness Tpa2 = 52 to obtain a predetermined pinch-off voltage Vp2. However, since the value of the Pt vapor deposition film thickness Tpa2 is small, ΔVp becomes ± 0.074V as shown in FIG.

  The upper limit of the thickness of the barrier layer 37 is 400 mm. This is because the maximum value of the Pt embedding depth Tpb is 317 mm, and 400−317 = 83 is calculated, and an enhancement FET cannot be obtained when d = 83 mm or more.

  That is, also in the third embodiment, the first FET 10 and the second FET 20 can be integrated on the same substrate, and the Pt vapor deposition film thickness Tpa of the first gate electrode 11 of the first FET 10 can be in the range of the Sa region. Both ΔVp of the 1FET 10 and the second FET 20 can be significantly suppressed.

  Similarly to the first embodiment, in the third embodiment, the points of the Pt vapor deposition film thickness Tpa and the pinch-off voltage Vp ((Tpa1, Vp1)) of the first FET 10 and the second FET 20 in FIG. The correlation coefficient R2 that realizes the correlation coefficient R3 between the points Tpa2 and Vp2) is designed. Further, the predetermined pinch-off voltage Vp2 is not limited to -0.8V, and cases of -1.0V or -0.5V are also conceivable. The correlation coefficient R3 required in each case is different, and it is necessary to design the correlation coefficient R2 corresponding to each case. For this purpose, it is necessary to design an epitaxial structure below the barrier layer 37, such as the thickness of the barrier layer 37 that realizes the predetermined correlation coefficient R2, the impurity concentration, and the thickness of the second electron supply layer. However, a certain range is allowed for the setting of each parameter.

  Note that the etching stop layer 39 may not be provided as in the second embodiment.

  FIGS. 16 and 17 show an E-type HEMT (E-FET) and a D-type HEMT (D-FET) having a structure not corresponding to the present embodiment for comparison. FIG. 16 shows an E-type HEMT (E-FET), and FIG. 17 shows a D-type HEMT (D-FET).

FIG. 16 is the same as the first embodiment except that the barrier layer 37 ′ is 130 mm. In FIG. 17, the barrier layer 37 ′ is 350 、, and the impurity concentration of the second electron supply layer 36 ′ is 2.0 × 10 ¹⁸ cm ⁻³ . The rest is the same as in the first embodiment.

  FIG. 18 is a diagram comparing the correlation between the Pt vapor deposition film thickness Tpa and the pinch-off voltage Vp according to the first to third embodiments and the structures of FIGS. 16 and 17.

  The first and second embodiments are a solid line α, the third embodiment is a solid line β, the structure of FIG. 16 is a solid line γ, and the structure of FIG. 17 is a solid line δ.

Here, the correlation coefficient R3 (0.0142) of the correlation of the linear region of the third embodiment is the correlation coefficient R3 (0.0175) of the correlation of the linear region of the first and second embodiments. Smaller than. This is because the thickness of the second electron supply layer 36 is the same as 120 mm in the first to third embodiments, but the impurity concentration of the second electron supply layer 36 is 2.6 in the first and second embodiments. × to ¹⁰ 18 to ^{cm -3,} in the third embodiment is because small as 1.5 × ¹⁰ 18 ^{cm -3.}

  Since the correlation between the first embodiment and the second embodiment is the same as that shown in FIGS. 8 and 9 and the correlation between the third embodiment is the same as that shown in FIG.

  In the structure of FIG. 16 (E-type HEMT), there is a Pt vapor deposition film thickness Tpa where the bottom portion of the buried portion b is located in the barrier layer 37 'and a Tpa located in the second electron supply layer 36'. And there exist a area | region, b area | region, and c area | region. However, since there is substantially no Pt vapor deposition film thickness Tpa for obtaining the pinch-off voltage Vp2 = −0.8 V required for the D-type HEMT (D-FET), the E-type HEMT (E-FET) and D-type HEMT (D-FET) cannot be integrated.

  On the other hand, in the structure of FIG. 17 (D-type HEMT), the bottom portion of the buried portion b is located in the barrier layer 37 'over the entire graph. In addition, the Pt vapor deposition film thickness Tpa includes a Sa region and a La region.

  In the structure of FIG. 17, the thickness of the barrier layer 37 ′ is set to be larger than 317 mm, which is the maximum depth Tpb of the buried portion b, so that the bottom of the buried portion b is actually located in the a region, the b region, and the c region. In FIG. 18, there are no a region, b region, and c region. That is, in this structure, since there is no Pt vapor deposition film thickness Tpa that can obtain a pinch-off voltage Vp = 0.25 V, E-type HEMT (E-FET) and D-type HEMT (D-FET) are integrated on the same substrate. I can't do it.

The present embodiment can be applied to any circuit as long as it is an integrated circuit in which an E-FET and a D-FET are integrated on the same substrate.

It is sectional drawing for demonstrating the 1st Embodiment of this invention. It is a characteristic view for demonstrating embodiment of this invention. It is a characteristic view for demonstrating embodiment of this invention. It is a characteristic view for demonstrating embodiment of this invention. It is a correlation diagram for demonstrating the 1st Embodiment of this invention. It is a correlation diagram for demonstrating the 1st Embodiment of this invention. It is a correlation diagram for demonstrating the 1st Embodiment of this invention. It is a correlation diagram for demonstrating the 1st Embodiment of this invention. It is a correlation diagram for demonstrating the 1st Embodiment of this invention. It is sectional drawing for demonstrating the 2nd Embodiment of this invention. It is sectional drawing for demonstrating the 3rd Embodiment of this invention. It is a correlation diagram for demonstrating the 3rd Embodiment of this invention. It is a correlation diagram for demonstrating the 3rd Embodiment of this invention. It is a correlation diagram for demonstrating the 3rd Embodiment of this invention. It is a correlation diagram for demonstrating the 3rd Embodiment of this invention. It is sectional drawing which shows the other FET for comparing with embodiment of this invention. It is sectional drawing which shows the other FET for comparing with embodiment of this invention. It is a correlation diagram for demonstrating embodiment of this invention.

Explanation of symbols

10 First FET
11 First gate electrode 11b First buried portion 12 Source electrode 13 Drain electrode 20 Second FET
21 Second gate electrode 21b Second buried portion 22 Source electrode 23 Drain electrode 30 Substrate 31 GaAs substrate 32 Buffer layer 33 First electron supply layer 34a, 34b Spacer layer 35 Channel layer 36 Second electron supply layer 37 Barrier layer 38 Cap layer 39 Etching stop layer 38ES, 38DS Source region 38ED, 38DD Drain region b Buried portion Tpa, Tpa1, Tpa2 Pt deposition thickness Tpb, Tpb1, Tpb2 Pt embedding depth Vp, Vp1, Vp2 Pinch off voltage ΔTpa Pt deposition thickness variation ΔTpb Pt embedding depth variation ΔVp Pinch-off voltage variation

Claims (12)

A substrate in which a semiconductor layer to be a buffer layer, a channel layer, an electron supply layer, a barrier layer, and a cap layer are sequentially stacked on a compound semiconductor substrate;
A first FET provided on the substrate and having a first gate electrode and set to a first pinch-off voltage;
A second FET integrated on the same substrate as the first FET and having a second gate electrode and set to a second pinch-off voltage,
The first gate electrode is provided on the surface of the barrier layer by vapor deposition of metal, and a part thereof is embedded in the barrier layer,
The second gate electrode is provided on the surface of the barrier layer in the same plane as the first gate electrode by vapor deposition of the metal, and a part thereof is embedded in the barrier layer,
The deposition thickness of the first gate electrode starts to decrease the correlation coefficient in the correlation between the ratio of the increase in the embedded depth in the semiconductor layer with respect to the increase in the deposition thickness of the metal and the deposition thickness. An integrated circuit device having a thickness equal to or greater than a thickness.   2. The integrated circuit device according to claim 1, wherein a bottom portion of the buried first gate electrode is located in the electron supply layer.   In the correlation between the ratio of the increase in the first pinch-off voltage to the increase in the distance from the surface of the electron supply layer to the bottom of the buried first gate electrode, and the distance, the electron supply layer has the correlation 3. The first region having a small absolute value of the correlation coefficient of the relationship and a second region having a correlation coefficient larger than the first region, wherein the bottom is located in the first region. The integrated circuit device described.   2. The integrated circuit device according to claim 1, wherein another electron supply layer is provided between the channel layer and the buffer layer.   2. The integrated circuit device according to claim 1, wherein the buried bottom portion of the second gate electrode is located in the barrier layer.   The integrated circuit device according to claim 1, wherein an etching stop layer is provided on the barrier layer.   2. The integrated circuit device according to claim 1, wherein each of the first gate electrode and the second gate electrode is a metal layer including Pt in a lowermost layer, and a part of the Pt is embedded in the semiconductor layer.   The integrated circuit device according to claim 1, wherein the barrier layer is an AlGaAs layer.   8. The integrated circuit device according to claim 7, wherein the Pt deposition film thickness of the first gate electrode is not less than 110 mm and not more than 170 mm.   8. The integrated circuit device according to claim 7, wherein the Pt vapor deposition film thickness of the second gate electrode is 40 to 100 mm.   The integrated circuit device according to claim 1, wherein the barrier layer has a thickness of 250 to 400 mm. 2. The integrated circuit device according to claim 1, wherein an impurity concentration of the electron supply layer is 1.0 × 10 ¹⁸ cm ^{−3 to} 5.0 × 10 ¹⁸ cm ⁻³ .

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