JP2004158772A - Fet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a FET having a satisfactory Schottky characteristics as well as AlGaAs with InGaP used as a surface protection layer and, while supperessing the surface level density with respect to the AlGaAs. <P>SOLUTION: An FET is formed with an undoped InGaAs channel layer 4, an Al<SB>0.25</SB>Ga<SB>0.75</SB>As spacer layer 5, a carrier supply layer 6, a first semiconductor layer 7 of Al<SB>X</SB>Ga<SB>1-X</SB>As, a second semiconductor layer 8 of an InGaP, and an n<SP>+</SP>type GaAs cap layer 9 formed sequentially in this order. This enables Schottky junction in contacting the first semiconductor layer through the second semiconductor layer of the InGaP to be obtained an opposite direction leakage current equivalent to a PHEMT having only an AlGaAs Schottky layer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field effect transistor using a compound semiconductor.
[0002]
[Prior art]
2. Description of the Related Art In recent years, field effect transistors (FETs) using compound semiconductors such as GaAs have been widely used for wireless communication, particularly for power amplifiers and switches of mobile phone terminals. In this GaAs FET, a FET using AlGaAs as a Schottky junction, which is called a PHEMT (pseudomorphic high mobility transistor), is generally used. However, since the AlGaAs layer is exposed by recess etching on both sides of the gate electrode, the PHEMT has a high surface state density even if it is protected by a protective insulating film. However, there is a problem that power cannot be sufficiently extracted due to the frequency dispersion. Therefore, an FET using a semiconductor layer such as InGaP having a smaller surface state density than AlGaAs on the side surface of the gate has been developed (for example, see Patent Document 1).
[0003]
FIG. 5 is a cross-sectional view of a field-effect transistor having a conventional InGaP surface protective layer. In FIG. 5, a 1 μm thick buffer layer 52 of undoped GaAs is formed on a substrate 51 made of semi-insulating GaAs to reduce lattice mismatch between an epitaxial layer to be grown later and the substrate 51. A buffer layer 53 composed of AlGaAs, a channel layer 54 composed of undoped In _0.2 Ga _0.8 As and having a thickness of 20 nm through which carriers travel, a spacer layer 55 composed of undoped InGaP having a thickness of 5 nm, and an n-type A carrier supply layer 56 in which only one atomic layer of impurity ion Si is planar-doped, a Schottky layer 57 made of undoped InGaP having a thickness of 30 nm, and a cap layer made of n ⁺ -type GaAs having a thickness of 100 nm 58 are sequentially laminated. Further, ohmic electrodes 60 serving as a source electrode and a drain electrode are formed at two places on the cap layer 58. Further, a gate electrode 62 is formed on the Schottky layer 57. An element isolation region 61 is formed near the ohmic electrode 60. Further, an insulating film 63 made of SiN or SiO is formed near the gate electrode 62.
[0004]
[Patent Document 1]
JP-A-8-340012 (pages 3-4, FIG. 1)
[0005]
[Problems to be solved by the invention]
However, a conventional FET having an InGaP surface protective layer has the following problems.
[0006]
When a gate electrode made of, for example, Ti or the like is formed on InGaP, heat (usually about 300 ° C.) during the manufacturing process of the FET causes diffusion at the Schottky interface between Ti and the InGaP layer, and the Schottky characteristics Deteriorates. In particular, the amount of reverse leakage current of the Schottky junction between the gate and the drain is larger than that of a conventional PHEMT using AlGaAs as a Schottky layer. As a result, degradation of device distortion and the like is observed in the RF characteristics.
[0007]
The present invention overcomes the above problems and provides a field effect transistor having good Schottky characteristics comparable to AlGaAs while suppressing surface state density with respect to AlGaAs by using InGaP as a surface protective layer.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a field effect transistor according to the present invention includes a channel layer formed on an insulating substrate, a first semiconductor layer formed on the channel layer, and a first semiconductor layer formed on the channel layer. A field effect transistor comprising: a formed second semiconductor layer; a gate electrode formed on the second semiconductor layer; and source and drain electrodes formed on both sides of the gate electrode. It is characterized in that a material constituting the electrode is diffused from inside the second semiconductor layer to inside the first semiconductor layer. According to this configuration, since the Schottky junction is obtained by contacting the first semiconductor layer through the second semiconductor layer, a reverse leakage current equivalent to the Schottky electrode used in the PHEMT can be obtained.
[0009]
Further comprising a first semiconductor layer is _{Al X Ga 1-X As (} 0 <X <1), the second semiconductor layer is made of InGaP or InP or InAlGaP. Especially improved Al X _Ga 1-X barrier height of the Schottky characteristics when the Al composition X increase in _As phi _B, improves the forward withstand voltage of the gate electrode, the voltage that can be applied to the gate direction of the FET characteristics And the maximum drain current can be increased. This is especially effective when an enhancement type FET is to be realized. The first semiconductor layer has the same effect even _{In X Al 1-X As (} 0 <X <1).
[0010]
Also features a stepwise or continuously increased so structure particularly Al composition of _Al X _{Ga 1-X} As from the substrate side. As a result, the gate material diffused from the gate electrode and a high Al composition Al _x Ga _{1 -x} As (for example, Al _0.75 Ga _0.25 As) form a Schottky junction having a high forward breakdown voltage, An increase in resistance can be suppressed.
[0011]
Further, the semiconductor device is characterized in that the thickness of the second semiconductor layer is 10 nm or less. As the thickness of the second semiconductor layer is smaller, it is possible to suppress an increase in the gate length due to diffusion in the horizontal direction.
[0012]
Further, a structure is added in which the lowermost layer of the gate electrode material is made of Pt or Ti or Al or Pd or Ni. These materials are particularly good Schottky junctions with AlGaAs by diffusing in a material containing InGaP. Can be obtained.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional configuration of a semiconductor device according to the first embodiment of the present invention.
[0014]
On a substrate 1 made of semi-insulating GaAs, a buffer layer 2 of 1 μm thick made of undoped GaAs and an undoped AlGaAs for relaxing lattice mismatch between an epitaxial layer grown later and the substrate 1. A buffer layer 3 having a thickness of 100 nm, an undoped In _0.2 Ga _0.8 As layer having a thickness of 20 nm, a channel layer 4 in which carriers travel, and an undoped Al _0.25 Ga _0.75 As layer having a thickness of 5 nm. The formed spacer layer 5, a carrier supply layer 6 in which only one atomic layer is planar-doped with Si as an n-type impurity ion at a dose of 5 × 10 ¹² cm ^−2, and a composition ratio of Al with a thickness of 20 nm With undoped Al _X Ga _1-X As stepwise or continuously increased from substrate side X = 0.25 to surface side X = 0.75 The first semiconductor layer 7 constituted, the second semiconductor layer 8 constituted by undoped In _0.48 Ga _0.52 P having a thickness of 10 nm, and the cap constituted by n ⁺ type GaAs having a thickness of 100 nm The layers 9 are sequentially stacked. Further, ohmic electrodes 11 serving as a source electrode and a drain electrode are formed at two places on the cap layer 9. Further, a gate electrode 13 is formed on the second semiconductor layer 8. The gate electrode material passes through the second semiconductor layer 8 made of undoped In _0.48 Ga _0.52 P with a thickness of 10 nm by applying heat, and the composition ratio of the surface is Al _0.75 Ga _0.25 As. And is diffused to the surface of the first semiconductor layer 7 made of, forming a diffusion layer 14.
[0015]
An element isolation region 12 is formed near the ohmic electrode 11. Further, the vicinity of the gate electrode 12 is protected by an insulating film 15 of SiN or SiO.
[0016]
Next, a method for manufacturing the semiconductor device configured as described above will be described with reference to the drawings. First, as shown in FIG. 2A, a GaAs buffer layer 2, an AlGaAs buffer layer 3, a channel layer 4, a GaAs buffer layer 2 are formed on a substrate 1 made of semi-insulating GaAs by MO-CVD or MBE. A spacer layer 5, a carrier supply layer 6, a first semiconductor layer 7 made of AlGaAs, a second semiconductor layer 8 made of InGaP, and a cap layer 9 are sequentially epitaxially grown. The first semiconductor layer 7 gradually increases or continuously increases the composition ratio X of Al from Al _0.25 Ga _0.75 As, which is the spacer layer 5 composition ratio of 0.25, so that the surface composition is Al _{0. The} surface is epitaxially grown to have a high Al composition so as to have a _{thickness of 0.75} Ga _0.25 As.
[0017]
Next, a pattern is formed at a predetermined position by a photoresist 16, a desired position is protected, and ion implantation is performed to form an element isolation region 12. Note that element isolation can also be performed by mesa etching a predetermined position of the epitaxial layer 10 from the buffer layer 2 epitaxially grown to the cap layer 9.
[0018]
Next, a photoresist pattern is formed, an ohmic metal made of a Ni / Au / Ge alloy is vapor-deposited on the entire surface (not shown), and lift-off is performed to form an ohmic electrode 11 as shown in FIG. I do.
[0019]
Next, as shown in FIG. 2C, an opening 9a is obtained by performing recess etching at a predetermined position between the ohmic electrodes of the cap layer 9 using the photoresist 17 as a mask. In this recess etching, for example, by using a mixed solution of phosphoric acid, aqueous hydrogen peroxide, and water, the etching selectivity between the cap layer 9 and the second semiconductor layer made of InGaP is large. Removal is possible, and stable recess etching is possible.
[0020]
Next, a gate metal is deposited on the entire surface and lifted off to form a gate electrode 13 made of Pt as shown in FIG. Further, heat treatment is performed to diffuse the gate metal in the undoped In _0.48 Ga _0.52 P second semiconductor layer having a thickness of 10 nm and reach the first semiconductor layer. This heat treatment is performed by a hot plate annealing apparatus at 300 ° C. so as not to impair device characteristics such as an epi structure. By this heat, as shown in FIG. 3B, the gate metal 14 of Pt diffuses to the first semiconductor layer of Al _X Ga _1-X As having a high Al composition (X = 0.75) on the surface, Good Schottky connection with the first semiconductor layer can be obtained. That is, since the Al composition X is high, the barrier height φ _B of the Schottky characteristic is improved, the withstand voltage of the gate electrode in the forward direction is improved, the voltage that can be applied in the gate direction of the FET characteristic is improved, and the maximum drain current is increased. Can be increased.
[0021]
The opening 9a for forming the gate electrode is 1 μm, and when the thickness of the second semiconductor layer of In _0.48 Ga _0.52 P exceeds 10 nm, heat treatment for Schottky connection causes Since some Pt also diffuses in the second semiconductor layer in the horizontal direction, the gate length increases and the device characteristics of the FET deteriorate. As the thickness of the second semiconductor layer is smaller, it is possible to suppress an increase in the gate length due to diffusion in the horizontal direction.
[0022]
When Ti is used as a gate electrode material, Ti diffuses in the second semiconductor layer, InGaP, but stops contacting the AlGaAs under the InGaP, and stops diffusing to the substrate side. Key characteristics can be obtained. Note that similarly good Schottky characteristics can be obtained even when Al, Pd, or Ni is used as a gate electrode material.
[0023]
FIG. 4 shows the effect of reducing the reverse leakage current in the FET according to the above embodiment and the FET having the conventional InGaP surface protective layer. This result is a result of measurement of an actual device. Thus, the leakage current can be reduced by about one digit as compared with the conventional example.
[0024]
In addition, although InGaP is used for the second semiconductor layer in the FET in the above embodiment, it may be InP or InAlGaP. These depend on the structure below the channel. For example, In a HEMT matched to an InP substrate, InP is optimal as the second semiconductor layer, and InAlAs is used as the second semiconductor layer.
[0025]
In the FET of the above embodiment, the first semiconductor layer is made of AlGaAs. However, even if InAlAs is used, the same effect can be obtained by increasing the Al composition ratio on the surface side. Not even.
[0026]
【The invention's effect】
In the present invention, while forming a gate electrode on InGaP (second semiconductor layer), it is difficult to obtain a good Schottky junction, by diffusing the gate electrode material into InGaP, AlGaAs (lower layer) of InGaP is formed. Schottky junction with the first semiconductor) can be obtained. This makes it possible to obtain a favorable field-effect transistor in which the reverse leakage current between the gate and the drain is reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a field-effect transistor of the present invention. FIG. 2 is a cross-sectional view illustrating a method of manufacturing a field-effect transistor of the present invention. FIG. 3 is a cross-sectional view illustrating a method of manufacturing a field-effect transistor of the present invention. 4 is a characteristic diagram showing the amount of reverse leakage current between the gate and the drain in the field effect transistor of the present invention. FIG. 5 is a sectional view showing a conventional field effect transistor.
1, 51 semi-insulating semiconductor substrate 2, 52 GaAs buffer layer 3, 53 AlGaAs buffer layer 4, 54 channel layer 5, 55 spacer layer 6, 56 Si-doped layer 7, first semiconductor layer 8, second semiconductor layer 9, 58 n ⁺ type GaAs cap layer 10, 59 epitaxial layer 11, 60 ohmic electrode 12, 61 element isolation region 13, 62 gate electrode 14 metal diffusion layer 15, 63 interlayer film layer 16 resist 17 resist 57 Schottky layer (InGaP)

Claims (6)

A channel layer formed on a semi-insulating substrate; a first semiconductor layer formed on the channel layer; a second semiconductor layer formed on the first semiconductor layer; In a field-effect transistor including a gate electrode formed on a semiconductor layer, and source and drain electrodes formed on both sides of the gate electrode, a material forming the gate electrode is formed from within the second semiconductor layer. A field-effect transistor, wherein the field-effect transistor reaches and diffuses into the first semiconductor layer. A first semiconductor layer composed of _{Al X Ga 1-X As (} 0 <X <1), the field effect transistor of claim 1, wherein the second semiconductor layer is characterized in that it consists of InGaP or InP or InAlGaP. An Al composition ratio _{X of} AlxGa1 _- xAs (0 <X <1), which is a first semiconductor layer, is increased stepwise or continuously from the substrate side toward the surface. Item 3. The field effect transistor according to Item 2. A first semiconductor layer composed of _{In X Al 1-X As (} 0 <X <1), the field effect transistor of claim 1, wherein the second semiconductor layer is characterized in that it consists of InGaP or InP or InAlGaP. 5. The field effect transistor according to claim 1, wherein the thickness of the second semiconductor layer is 10 nm or less. 6. The field effect transistor according to claim 1, wherein the lowermost layer of the gate electrode is made of Pt, Ti, Al, Pd, or Ni.

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