JP2010267817A - Field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor which has improved characteristics by reducing an influence of depletion from a buffer layer doped with a p-type impurity. <P>SOLUTION: The field-effect transistor 10 having a double-hetero HEMT (High Electron Mobility Transistor) structure includes: a semi-insulating GaAs substrate 11; a p-type buffer layer 101 formed on the semi-insulating GaAs substrate 11 and doped with the p-type impurity; a lower carrier supply layer 103 formed above the p-type buffer layer 101 and doped with an n-type impurity; an undoped channel layer 105 formed above the lower carrier supply layer 103; an upper carrier supply layer 107 formed above the channel layer 105 and doped with the n-type impurity; and an n-type buffer layer 102B formed between the p-type buffer layer 101 and lower carrier supply layer 103 and doped with the n-type impurity. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a field effect transistor, and more particularly to a double heterostructure HEMT (High Electron Mobility Transistor).

  A field effect transistor (hereinafter referred to as a GaAsFET (Field Effect Transistor)) formed on a semi-insulating substrate made of GaAs is used in communication devices, particularly power amplifiers and switches of mobile phone terminals, etc. due to its excellent performance. It's being used. In recent years, with the improvement in performance of mobile phone terminals and the like, further improvement in performance has been strongly demanded for GaAsFET.

  By the way, in order to improve the characteristics of the GaAsFET, it is important how to suppress the influence (parasitic effect) from the substrate side and the FET surface side and not deteriorate the characteristics (extract the original capability of the device). Thus, for example, a field effect transistor described in Patent Document 1 is known as a conventional GaAsFET.

In the field effect transistor described in Patent Document 1, a region in contact with a semi-insulating substrate of an epitaxial layer formed by epitaxial growth on a semi-insulating compound semiconductor substrate is formed of a semiconductor layer having a conductivity type opposite to that of the active layer. The field effect transistor is characterized in that the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more and the thickness is completely depleted.

  The structure and function of the conventional field effect transistor described in Patent Document 1 will be briefly described below.

  FIG. 5 is a structural cross-sectional view of a conventional field effect transistor 20 described in Patent Document 1. In FIG. The conventional field effect transistor 20 in FIG. 1 includes a semiconductor layer 200, a source electrode 206 and a drain electrode 207, and a gate electrode 208.

  The semiconductor layer 200 includes a semi-insulating GaAs substrate 201, a p-type buffer layer 202 made of GaAs doped with a p-type impurity by molecular beam epitaxy or metal organic vapor phase epitaxy, and undoped GaAs. A channel layer 203 configured, an AlGaAs doped with an n-type impurity, and also serving as a Schottky layer; an ohmic contact layer 205 composed of GaAs doped with an n-type impurity; Are sequentially formed.

  Furthermore, a source electrode 206 and a drain electrode 207 made of AuGa / Ni / Au are formed on the surface of the ohmic contact layer 205. The gate electrode 208 is disposed between the source electrode 206 and the drain electrode 207 and is formed on the surface of the carrier supply layer 204.

  As described above, the conventional field effect transistor 20 shown in FIG. 5 includes the p-type buffer layer 202 doped with the p-type impurity so as to be in contact with the semi-insulating GaAs substrate 201. The reason is as follows.

  It is known that the interface portion between the semi-insulating GaAs substrate 201 and the epitaxial layer is contaminated with oxygen or carbon. Thus, for example, when contaminated with oxygen, deep levels are formed in the semiconductor, which causes device parasitic effects such as frequency dispersion of drain conductance and drain lag. That is, the characteristics of the FET are deteriorated. As one means for suppressing this phenomenon, the p-type buffer layer 202 is provided in contact with the semi-insulating GaAs substrate. Thereby, it becomes possible to suppress the characteristic deterioration of FET.

JP-A-8-88353

However, the conventional techniques have the following problems.
For example, as shown in Patent Document 1, when a p-type buffer layer 202 doped with a p-type impurity exists on a semi-insulating GaAs substrate 201 and a double hetero HEMT structure is used, Due to depletion from the p-type buffer layer 202, electrons that should originally be supplied to the channel from the lower carrier supply layer are lost, leading to a reduction in the electron concentration of the channel.

  As a result, the on-resistance of the transistor increases and the driving (current) capability decreases. In addition, an increase in parasitic capacitance is caused, and the original characteristics (capacity) of the FET cannot be extracted.

  As described above, due to depletion from the p-type buffer layer 202 doped with the p-type impurity, the conventional field effect transistor cannot bring out the characteristics (capability) of the original GaAsFET.

  In view of the above problems, an object of the present invention is to provide a field effect transistor with improved characteristics by reducing the influence of depletion from a buffer layer doped with a p-type impurity.

  In order to achieve the above object, a field effect transistor according to the present invention is a field effect transistor having a double hetero HEMT structure, which is formed on a substrate and is doped with a p-type impurity. A buffer layer; a first carrier supply layer formed above the p-type buffer layer and doped with an n-type impurity; an undoped channel layer formed above the first carrier supply layer; and the channel layer Is formed between the second carrier supply layer doped with n-type impurities and the p-type buffer layer and the first carrier supply layer, and is doped with n-type impurities. A mold buffer layer.

  Thereby, since at least one n-type buffer layer is formed between the p-type buffer layer and the first carrier supply layer, the depletion from the p-type buffer layer affects the first carrier supply layer. And the electron concentration of the channel can be increased. As a result, the drive (current) capability of the FET can be improved, the on-resistance can be reduced, and the parasitic capacitance can be reduced, and the original FET characteristics (capability) can be extracted.

  The p-type buffer layer and the n-type buffer layer may be made of GaAs or AlGaAs.

  Thereby, it is possible to alleviate lattice mismatch with a compound semiconductor substrate such as a semi-insulating GaAs substrate.

The n-type buffer layer may be uniformly doped with n-type impurities.
Thereby, n-type impurity doping is uniformly performed in the layer, so that depletion from the p-type buffer layer can be stably suppressed.

The n-type buffer layer may be delta-doped with n-type impurities.
As a result, n-type doping is localized for each atomic layer surface, and electrons exist steeply at a distance close to the p-type buffer layer, so that the influence of depletion can be efficiently reduced.

  The doping concentration of the n-type buffer layer may be equal to or lower than the doping concentration of the p-type buffer layer.

  Thereby, the influence of depletion from the p-type buffer layer can be reduced. Further, according to this configuration, all the electrons doped in the n-type buffer layer act for the purpose of eliminating depletion. As a result, since it does not remain as an excessive electron layer, it does not become a leak source of the FET.

  The doping concentration of the n-type buffer layer may be lower than the doping concentration of the first carrier supply layer.

  Thereby, since the doping concentration of the n-type buffer layer is lower than the doping concentration of the first carrier supply layer, the n-type buffer layer does not serve as an electron supply layer and does not serve as a leakage source for the FET.

The channel layer may be made of InGaAs.
Thereby, high mobility and high electron concentration can be realized, and the characteristics of the FET can be improved.

  The field effect transistor further includes an undoped first buffer layer formed on the p-type buffer layer and an undoped second buffer layer formed on the one or more n-type buffer layers. The first carrier supply layer may be formed on the second buffer layer.

  The field effect transistor further includes an undoped first spacer layer formed on the first carrier supply layer, and an undoped second spacer layer formed on the channel layer. The carrier supply layer may be formed on the second spacer layer.

  According to the field effect transistor of the present invention, the FET characteristics can be improved by reducing the influence of depletion from the buffer layer doped with the p-type impurity.

It is sectional drawing which shows an example of the structure of the field effect transistor of this Embodiment. An example of the comparison figure of the conduction band (Ec) of the field effect transistor of this Embodiment and the conventional field effect transistor is shown. It is an enlarged view of the channel layer part in the comparison figure of the conduction band (Ec) of the field effect transistor of this Embodiment, and the conventional field effect transistor. It is an enlarged view of the channel layer part in the comparison figure of the electron concentration of the field effect transistor of this Embodiment, and the conventional field effect transistor. It is sectional drawing which shows the structure of the conventional field effect transistor.

  Below, the field effect transistor concerning the present invention is explained in detail using a drawing based on an embodiment.

  The field effect transistor in the present embodiment is a field effect transistor having a double hetero HEMT structure, and includes at least one or more n-type layers between a p-type buffer layer and a lower carrier supply layer formed on a substrate. Includes a buffer layer. Thereby, the influence on the lower carrier supply layer due to depletion from the p-type buffer layer is suppressed, and the electron concentration of the channel is increased, so that the FET characteristics are improved. The double hetero HEMT structure is a structure in which carrier supply layers are formed above and below a channel layer.

  FIG. 1 is a cross-sectional view showing an example of the structure of the field effect transistor 10 according to the present embodiment. The field effect transistor 10 in the figure includes a semi-insulating GaAs substrate 11, an epitaxial layer 12, a gate electrode 13, and an ohmic electrode 14.

  The epitaxial layer 12 is sequentially stacked on the semi-insulating GaAs substrate 11 and includes a p-type buffer layer 101, a stacked buffer layer 102, a lower carrier supply layer 103, a first spacer layer 104, a channel layer 105, A second spacer layer 106, an upper carrier supply layer 107, a threshold adjustment layer 108, and an ohmic contact layer 109 are provided.

The p-type buffer layer 101 is made of, for example, AlGaAs having a thickness of 20 nm and doped with p-type impurities, and the doping concentration is 5 × 10 ¹⁷ / cm ³ . The p-type buffer layer 101 has a function of relaxing lattice mismatch between the epitaxial layer 12 and the semi-insulating GaAs substrate 11.

  The laminated buffer layer 102 is a layer that relaxes lattice mismatch between the epitaxial layer 12 and the semi-insulating GaAs substrate 11, and includes a buffer layer 102A, an n-type buffer layer 102B, and a buffer layer 102C.

The buffer layer 102A is made of undoped AlGaAs with a thickness of 100 nm, for example. The n-type buffer layer 102B is composed of, for example, an n-type AlGaAs layer having a thickness of 20 nm and uniformly doped with an n-type impurity made of silicon (Si). For example, the doping concentration is 1E17 / cm ³ . The buffer layer 102C is made of undoped AlGaAs with a thickness of 100 nm, for example. Note that a layer in which impurities are uniformly doped indicates that the doping concentration is almost equal in an arbitrary region of the layer, for example, an upper portion, a middle portion, a lower portion, or a different region in the horizontal direction of the layer.

  Thus, by performing n-type impurity doping uniformly in the layer of the n-type buffer layer 102B, depletion from the p-type buffer layer 101 can be stably suppressed. As a method for forming the uniform n-type doping region, for example, a gas containing Si is mixed during the epitaxial growth of the n-type buffer layer 102B.

  The n-type doping may be delta (δ) doping. Here, delta doping is to introduce an impurity atomic layer localized only on one atomic layer surface in a semiconductor crystal. This delta doping uses, for example, a thin film forming technique having an atomic level film thickness control property such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). This is realized by supplying impurity atoms to the surface where the crystal growth is temporarily suspended. This delta doping is also called sheet doping.

  By using this delta doping for the n-type buffer layer 102B, since the n-type doping is localized for each atomic layer surface, electrons are rapidly present at a distance close to the p-type buffer layer 101, so that depletion is efficiently performed. It becomes possible to reduce the influence of. The n-type delta doping to the n-type buffer layer 102B is realized, for example, by temporarily interrupting the epitaxial growth of the n-type buffer layer 102B and filling a gas containing Si.

  The doping concentration of the n-type buffer layer 102B is preferably equal to or lower than the doping concentration of the p-type buffer layer 101 and lower than the doping concentration of the lower carrier supply layer 103. According to this configuration, all the electrons doped into the n-type buffer layer 102B act for the purpose of eliminating depletion. As a result, it does not remain as a surplus electron layer, so that it does not become a leak source of the FET.

  In addition, when a situation in which surplus electrons exist is formed, electrons flow in other than the channel layer 105 with high mobility, and so-called parallel conductance is generated. In this case, the influence of depletion is suppressed, but the controllability of the drain current by the gate voltage is reduced.

The lower carrier supply layer 103 is a layer that supplies electrons as carriers to the channel layer 105, and is made of, for example, AlGaAs doped with Si that is n-type impurity ions, and has a thickness of 7 nm. For example, the doping concentration is 3E18 / cm ³ .

  The first spacer layer 104 is made of undoped AlGaAs with a thickness of 2 nm, for example.

The channel layer 105 is a layer in which carriers travel and is made of, for example, undoped In _0.2 Ga _0.8 As having a thickness of 5 nm.

  The second spacer layer 106 is made of undoped AlGaAs with a thickness of 2 nm, for example.

The upper carrier supply layer 107 is a layer that supplies electrons as carriers to the channel layer 105, and is made of, for example, AlGaAs doped with Si that is n-type impurity ions, and has a thickness of 7 nm. For example, the doping concentration is 3E18 / cm ³ .

  The threshold adjustment layer 108 is a layer for adjusting the threshold voltage of the gate of the FET, and is made of, for example, undoped AlGaAs with a film thickness of 20 nm. The threshold adjustment layer 108 also functions as an etching stop layer that stops the etching of the ohmic contact layer 109 in contact with the threshold adjustment layer 108 from the uppermost layer.

  The ohmic contact layer 109 is divided into two regions, to which the ohmic electrode 14 is connected. The ohmic contact layer 109 is composed of, for example, two layers (not shown), the lower layer is made of n-type GaAs with a thickness of 50 nm, and the upper layer is made of n-type InGaAs with a thickness of 50 nm.

  The gate electrode 13 is formed on the threshold adjustment layer 108. The gate electrode 13 is made of, for example, Ti / Al / Ti and is in Schottky junction with the threshold adjustment layer 108.

  The ohmic electrode 14 is a source electrode and a drain electrode of the FET, is formed so as to sandwich the gate electrode 13, and is ohmically connected on the ohmic contact layer 109. The ohmic electrode 14 is electrically connected to the channel layer 105 through the ohmic contact layer 109, the threshold adjustment layer 108, the upper carrier supply layer 107, and the second spacer layer 106.

  As shown in the above configuration, the field effect transistor 10 according to the present embodiment is a double heterostructure HEMT, and includes a p-type buffer layer 101 and a lower carrier supply layer 103 formed on a semi-insulating GaAs substrate 11. Are provided with an n-type buffer layer 102B. With this configuration, the effect of depletion from the p-type buffer layer 101 on the lower carrier supply layer 103 can be reduced, and the performance as an FET can be sufficiently exhibited.

The field effect transistor 10 of the present embodiment is formed as follows.
First, each layer is epitaxially grown using MOCVD or MBE. Then, the ohmic contact layer 109 is divided into two regions by patterning by photolithography and etching such as dry etching or wet etching. Furthermore, after forming a metal on the entire surface by using a vapor deposition method or a sputtering method, patterning and etching are performed to form the gate electrode 13 and the ohmic electrode 14. Note that the gate electrode 13 and the ohmic electrode 14 may be formed by using a lift-off method instead of etching.

  Below, the characteristic and effect of the field effect transistor 10 of this Embodiment are demonstrated.

  FIG. 2 shows an example of a comparison diagram of the conduction band (Ec) between the field effect transistor 10 of the present embodiment and the conventional field effect transistor. According to this, in the field effect transistor 10 of the present embodiment, the band potential raised to the semi-insulating GaAs substrate side by the p-type buffer layer 101 can be reduced by providing the n-type buffer layer 102B. it can.

  In the figure, the horizontal axis indicates the distance from the upper surface of the threshold adjustment layer 108. A region surrounded by a broken-line square in FIG. 2 is a region corresponding to the channel layer 105.

  FIG. 3 is an enlarged view of the channel layer 105 portion made of InGaAs in FIG. According to this, by providing the n-type buffer layer 102B, the band potential is lowered, and the channel spreads in the direction of the semi-insulating GaAs substrate 11.

  FIG. 4 shows a comparison of electron concentrations in the InGaAs channel portion enlarged in FIG. According to this, by providing the n-type buffer layer 102B, the electron concentration of the channel layer 105 portion can be increased. As a result, the drive (current) capability of the FET increases and the on-resistance can be reduced, so that the characteristics of the FET can be improved.

  As described above, the field effect transistor according to the present invention has been described based on the embodiments, but the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, what made the various deformation | transformation which those skilled in the art conceivable to this Embodiment is also contained in the scope of the present invention.

  For example, in the embodiment, the configuration in which each semiconductor layer has GaAs or AlGaAs as a main component has been described. However, other nitride semiconductors such as GaN, or other semiconductors may be used. Further, the substrate is not limited to the semi-insulating GaAs substrate, but may be other compound semiconductor substrates or other substrates.

  The material, thickness, impurity doping concentration, etc. of each semiconductor layer are merely examples, and may be changed as appropriate.

  The field effect transistor according to the present invention can be applied to a communication device using GaAs MMIC (Monolithic Microwave Integrated Circuit), and is particularly suitable for use in a power amplifier and a switch of a mobile phone terminal.

10, 20 Field effect transistor 11, 201 Semi-insulating GaAs substrate 12 Epitaxial layer 13, 208 Gate electrode 14 Ohmic electrode 101, 202 P-type buffer layer 102 Stacked buffer layer 102A, 102C Buffer layer 102B n-type buffer layer 103 Lower carrier supply Layer 104 First spacer layer 105, 203 Channel layer 106 Second spacer layer 107 Upper carrier supply layer 108 Threshold adjustment layer 109, 205 Ohmic contact layer 200 Semiconductor layer 204 Carrier supply layer 206 Source electrode 207 Drain electrode

Claims (9)

A field effect transistor having a double hetero HEMT (High Electron Mobility Transistor) structure,
A substrate,
A p-type buffer layer formed on the substrate and doped with a p-type impurity;
A first carrier supply layer formed above the p-type buffer layer and doped with an n-type impurity;
An undoped channel layer formed above the first carrier supply layer;
A second carrier supply layer formed above the channel layer and doped with an n-type impurity;
A field effect transistor comprising one or more n-type buffer layers formed between the p-type buffer layer and the first carrier supply layer and doped with n-type impurities. The field effect transistor according to claim 1, wherein the p-type buffer layer and the n-type buffer layer are made of GaAs or AlGaAs. The field effect transistor according to claim 1, wherein the n-type buffer layer is uniformly doped with n-type impurities. The field effect transistor according to claim 1, wherein the n-type buffer layer is delta-doped with an n-type impurity. The field effect transistor according to any one of claims 1 to 4, wherein a doping concentration of the n-type buffer layer is equal to or lower than a doping concentration of the p-type buffer layer. The field effect transistor according to claim 1, wherein a doping concentration of the n-type buffer layer is lower than a doping concentration of the first carrier supply layer. The field effect transistor according to claim 1, wherein the channel layer is made of InGaAs. The field effect transistor further comprises:
An undoped first buffer layer formed on the p-type buffer layer;
An undoped second buffer layer formed on the one or more n-type buffer layers,
The field effect transistor according to claim 1, wherein the first carrier supply layer is formed on the second buffer layer. The field effect transistor further comprises:
An undoped first spacer layer formed on the first carrier supply layer;
An undoped second spacer layer formed on the channel layer,
The field effect transistor according to claim 1, wherein the second carrier supply layer is formed on the second spacer layer.

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