JP4904671B2 - 半導体装置、その製造方法及び電子機器 - Google Patents
半導体装置、その製造方法及び電子機器 Download PDFInfo
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- JP4904671B2 JP4904671B2 JP2004187036A JP2004187036A JP4904671B2 JP 4904671 B2 JP4904671 B2 JP 4904671B2 JP 2004187036 A JP2004187036 A JP 2004187036A JP 2004187036 A JP2004187036 A JP 2004187036A JP 4904671 B2 JP4904671 B2 JP 4904671B2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Description
一方、薄膜トランジスタのポリシリコン薄膜は、例えばCVD法により形成されるが、このCVD膜は、シリコン単結晶基板では殆ど存在しないSiダングリングボンドを多数含んでいる。Siダングリングボンドは、Si−Si結合が切断されたSiの未結合手のことであり、汚染原子と結合して半導体特性を劣化させる原因となる。従って、このようなSiダングリングボンドを無くす必要がある。
2;保護酸化膜
3;チャネル領域
4;拡散層
5;ゲート絶縁膜
6;ゲート
7;スイッチング用薄膜トランジスタ
8;層間絶縁膜
9、10;配線
11;水素化窒化シリコン膜
12;下部電極
13;強誘電体膜
14;上部電極
15;保護膜
17;液晶
18;対向電極
19;対向基板
21、22;ビット線
23;ワード線
24;プレート線
25;センスアンプ
33、37;ROM
34、38;RF/IF
35、39;CPU
36、40、45、49;不揮発性メモリ
41、46;受信データ復号化回路
42、47;送信データ符号化回路
43、50;アンテナ素子
44、48;制御回路
51、52;単結晶基板
Claims (21)
- 絶縁性基板と、この絶縁性基板の上方に配置されており能動素子を備える能動素子層と、前記能動素子層の上方に配置されており強誘電体容量素子を備える強誘電体容量素子層と、前記能動素子層と前記強誘電体容量素子層との間に形成された水素化窒化シリコン(SiN x :H)層とを有し、前記能動素子は、ソースドレイン領域及びチャネル領域を備えたポリシリコン薄膜と、前記チャネル領域の上方に形成されたゲート電極と、前記ポリシリコン薄膜と前記ゲート電極との間に形成されたゲート絶縁膜とを有する薄膜トランジスタを含むものであり、前記能動素子層は、前記ポリシリコン薄膜を覆い前記ゲート電極が埋め込まれた層間絶縁膜を有し、前記強誘電体容量素子は下部電極、強誘電体層及び上部電極が積層されたものであることを特徴とする半導体装置。
- 絶縁性基板と、この絶縁性基板の上方に配置されており能動素子を備える能動素子層と、前記能動素子層の上方に配置されており強誘電体容量素子を備える強誘電体容量素子層と、前記能動素子層と前記強誘電体容量素子層との間に形成された水素化窒化シリコン(SiN x :H)層と、この水素化窒化シリコン層と前記強誘電体容量素子層との間に形成された導電性酸化物層とを有し、前記能動素子は、ソースドレイン領域及びチャネル領域を備えたポリシリコン薄膜と、前記チャネル領域の上方に形成されたゲート電極と、前記ポリシリコン薄膜と前記ゲート電極との間に形成されたゲート絶縁膜とを有する薄膜トランジスタを含むものであり、前記能動素子層は、前記ポリシリコン薄膜を覆い前記ゲート電極が埋め込まれた層間絶縁膜を有し、前記強誘電体容量素子は下部電極、強誘電体層及び上部電極が積層されたものであることを特徴とする半導体装置。
- 前記水素化窒化シリコン層を挿通して前記能動素子と前記強誘電体容量素子とを接続する接続部を有することを特徴とする請求項1又は2に記載の半導体装置。
- 前記下部電極は、導電性酸化物により形成されていることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記導電性酸化物は、インジウム錫酸化物であることを特徴とする請求項2又は4に記載の半導体装置。
- 前記水素化窒化シリコン層はプラズマCVD(化学気相成長)により形成されたものであることを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。
- 前記接続部は、前記水素化窒化シリコン層に形成された配線と、前記水素化窒化シリコン層を挿通し前記下部電極と前記配線とを接続する第1のビアと、前記層間絶縁膜を挿通し前記ソースドレイン領域と前記配線とを接続する第2のビアとを有することを特徴とする請求項3に記載の半導体装置。
- 前記接続部は、前記水素化窒化シリコン層に形成された配線と、前記水素化窒化シリコン層を挿通し前記上部電極と前記配線とを接続する第1のビアと、前記層間絶縁膜を挿通し前記ソースドレイン領域と前記配線とを接続する第2のビアとを有することを特徴とする請求項3に記載の半導体装置。
- 前記強誘電体膜は前記下部電極を覆うように前記水素化窒化シリコン層上に形成されており、前記第1のビアは、前記強誘電体膜に設けた開口部を挿通していることを特徴とする請求項8に記載の半導体装置。
- 前記能動素子をスイッチング素子とし、前記強誘電体容量素子を容量部とする不揮発性メモリであることを特徴とする請求項1乃至9のいずれか1項に記載の半導体装置。
- 絶縁性基板上にポリシリコン薄膜を形成しゲート絶縁膜を介してゲート電極を形成し更に前記ゲート電極をマスクとして前記ポリシリコン薄膜にイオン注入することによりソースドレイン領域及びチャネル領域を形成して薄膜トランジスタを形成する工程と、この薄膜トランジスタを覆う層間絶縁膜上に配線層を形成すると共に前記層間絶縁膜を挿通して前記薄膜トランジスタに接続される第1コンタクトを形成する工程と、前記層間絶縁膜上に前記配線層を覆うようにして水素化窒化シリコン(SiN x :H)膜を形成する工程と、この水素化窒化シリコン膜上に下部電極を形成すると共に前記水素化窒化シリコン膜を挿通して前記配線層に接続される第2コンタクトを形成する工程と、前記下部電極上に強誘電体層を形成する工程と、前記強誘電体層上に上部電極を形成する工程と、を有することを特徴とする半導体装置の製造方法。
- 絶縁性基板上にポリシリコン薄膜を形成しゲート絶縁膜を介してゲート電極を形成し更に前記ゲート電極をマスクとして前記ポリシリコン薄膜にイオン注入することによりソースドレイン領域及びチャネル領域を形成して薄膜トランジスタを形成する工程と、この薄膜トランジスタを覆う層間絶縁膜上に配線層を形成すると共に前記層間絶縁膜を挿通して前記薄膜トランジスタに接続される第1コンタクトを形成する工程と、前記層間絶縁膜上に前記配線層を覆うようにして水素化窒化シリコン(SiN x :H)膜を形成する工程と、この水素化窒化シリコン膜上に下部電極を形成する工程と、前記下部電極上に強誘電体層を形成する工程と、前記強誘電体層上に上部電極を形成すると共に前記水素化窒化シリコン膜を挿通して前記配線層に接続される第2コンタクトを形成する工程と、を有することを特徴とする半導体装置の製造方法。
- 前記水素化窒化シリコン膜はプラズマCVD(気相成長)法により形成することを特徴とする請求項11又は12に記載の半導体装置の製造方法。
- 前記水素化窒化シリコン膜を形成する工程より後の工程においては、前記ポリシリコン薄膜の温度が350℃より高温になることがないことを特徴とする請求項11乃至13のいずれか1項に記載の半導体装置の製造方法。
- 請求項1乃至10のいずれか1項に記載の半導体装置を使用したことを特徴とする電子機器。
- 請求項10に記載の不揮発性メモリを使用したICカードであることを特徴とする電子機器。
- 前記不揮発性メモリは、中央演算装置(CPU)、外部とのデータの送受信を行う高周波(RF)インターフェイス部及びデータを保存する読み出し専用メモリ(ROM)と共に、同一基板上に一体的に形成されていることを特徴とする請求項16に記載の電子機器。
- 中央演算装置(CPU)、外部とのデータの送受信を行う高周波(RF)インターフェイス部及びデータを保存する読み出し専用メモリ(ROM)は、前記不揮発性メモリとは別に、単結晶シリコン基板上に形成されていることを特徴とする請求項16に記載の電子機器。
- 請求項10に記載の不揮発性メモリを有し、更に、送信データ符号化素子、受信データ復号化素子、外部とのデータの送受信を行うアンテナ素子及びこれらの制御を行う制御素子を有する高周波ICタグであることを特徴とする電子機器。
- 前記送信データ符号化素子、前記受信データ復号化素子及び前記制御素子は、単結晶半導体基板上に形成されていることを特徴とする請求項19に記載の電子機器。
- 請求項5に記載の半導体装置の前記絶縁性基板上に液晶表示装置の画素回路が形成されており、この画素回路のトランジスタに接続された画素電極が、前記半導体装置の水素化窒化シリコン層と同層の水素化窒化シリコン層上に形成され、前記半導体装置の下部電極を構成するインジウム錫酸化物層と同層のインジウム錫酸化物層であることを特徴とする液晶表示装置であることを特徴とする電子機器。
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US12/923,281 US8723240B2 (en) | 2004-06-24 | 2010-09-13 | Semiconductor device, manufacturing method for the same, and electronic device |
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