JP4896781B2 - Dram装置の製造方法 - Google Patents
Dram装置の製造方法 Download PDFInfo
- Publication number
- JP4896781B2 JP4896781B2 JP2007070975A JP2007070975A JP4896781B2 JP 4896781 B2 JP4896781 B2 JP 4896781B2 JP 2007070975 A JP2007070975 A JP 2007070975A JP 2007070975 A JP2007070975 A JP 2007070975A JP 4896781 B2 JP4896781 B2 JP 4896781B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- forming
- storage
- storage node
- contact plug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 238000003860 storage Methods 0.000 claims description 127
- 238000005530 etching Methods 0.000 claims description 39
- 239000010410 layer Substances 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000002344 surface layer Substances 0.000 claims description 5
- 238000002425 crystallisation Methods 0.000 claims description 3
- 230000008025 crystallization Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 description 22
- 239000003990 capacitor Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000011538 cleaning material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
102,152 素子隔離領域
106,158 ビットライン
104,114,154,160 絶縁膜
108,162,障壁コンタクト(ストレージコンタクトプラグ)
110,156,157 シリコン窒化膜
112 ポリシリコン膜
116,164 ストレージノード
118,166 HSG
Claims (7)
- ゲートが形成された半導体基板上に第1絶縁膜を形成する段階と、
前記第1絶縁膜上に上部表面が第1絶縁膜と別のエッチング選択比を有する第2絶縁膜で覆われたビットラインを形成する段階と、
前記第2絶縁膜及びビットラインの両側壁に前記第1絶縁膜と別の選択比を有するスペーサを形成する段階と、
前記ビットラインを含んで前記第1絶縁膜上に第2絶縁膜及びスペーサと相異なるエッチング選択比を有する第3絶縁膜を形成する段階と、
前記ストレージコンタクト領域を定義するためのマスクを使用して前記第3絶縁膜と前記第1絶縁膜をエッチングして前記ビットラインとビットラインとの間を通過する自己整列型ストレージコンタクトホールを形成する段階と、
前記ストレージコンタクトホールを導電膜で充填してストレージコンタクトプラグを形成する段階と、
前記第3絶縁膜と前記ストレージコンタクトプラグ上に前記ストレージコンタクトプラグと電気的に連結されるように、HSG表面層を有するストレージノードを形成する段階とを含み、
前記HSG表面層を有するストレージノードを形成する段階は、前記ストレージコンタクトプラグを含んで第3絶縁膜上に第4絶縁膜、物質層、そして第5絶縁膜を順次形成する段階と、ストレージノード形成用マスクを使用して前記第5絶縁膜、物質層、そして第4絶縁膜を順次エッチングして前記ストレージコンタクトプラグ及び第3絶縁膜一部の上部表面を露出させる開口部を形成する段階と、前記開口部を導電膜で充填してストレージノードを形成する段階と、前記ストレージノード両側の物質層の上部表面が露出されるときまで、第5絶縁膜をエッチングする段階と、前記ストレージノード両側の第4絶縁膜の上部表面が露出されるときまで前記物質層をエッチングする段階と、前記ストレージノード両側の第3絶縁膜の上部表面が露出されるときまで前記第4絶縁膜をエッチングする段階と、前記ストレージノード表面上にHSG表面層を形成する段階とをさらに含み、
前記物質層及び前記ストレージノードはポリシリコンで形成され、
前記第3絶縁膜及び前記第5絶縁膜は同じエッチング物質でエッチングされ得る酸化物系の絶縁物で形成され、
前記第4絶縁膜は窒化物系の絶縁物で形成され、
前記第3絶縁膜は、USG、BPSG、HDP、そしてO 3 −TEOSのうち、いずれか1つで形成され、
前記第4絶縁膜は、SiN及びSiONのうち、いずれか1つで形成され、
前記第5絶縁膜は、USG、BPSG、HDP、そしてO 3 −TEOSのうち、いずれか1つで形成されることを特徴とするDRAM装置の製造方法。 - 前記第1絶縁膜は、USG、BPSG、HDP、そしてO3−TEOSのうち、いずれか1つで形成されることを特徴とする請求項1に記載のDRAM装置の製造方法。
- 前記第2絶縁膜は、SiN及びSiONのうち、いずれか1つで形成されることを特徴とする請求項1に記載のDRAM装置の製造方法。
- 前記スペーサは、SiN及びSiONのうち、いずれか1つで形成されることを特徴とする請求項1に記載のDRAM装置の製造方法。
- 前記ストレージコンタクトプラグを形成した後、前記ストレージコンタクトプラグを結晶化する段階をさらに含むことを特徴とする請求項1に記載のDRAM装置の製造方法。
- 前記結晶化段階は、熱処理工程で実施されることを特徴とする請求項5に記載のDRAM装置の製造方法。
- 前記熱処理工程は、550℃以上の温度で実施されることを特徴とする請求項6に記載のDRAM装置の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR199828191 | 1998-07-13 | ||
KR1019980028191A KR100299594B1 (ko) | 1998-07-13 | 1998-07-13 | 디램 장치의 제조 방법 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19778599A Division JP4550185B2 (ja) | 1998-07-13 | 1999-07-12 | Dram装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007227944A JP2007227944A (ja) | 2007-09-06 |
JP4896781B2 true JP4896781B2 (ja) | 2012-03-14 |
Family
ID=19543994
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19778599A Expired - Fee Related JP4550185B2 (ja) | 1998-07-13 | 1999-07-12 | Dram装置の製造方法 |
JP2007070975A Expired - Fee Related JP4896781B2 (ja) | 1998-07-13 | 2007-03-19 | Dram装置の製造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19778599A Expired - Fee Related JP4550185B2 (ja) | 1998-07-13 | 1999-07-12 | Dram装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6207574B1 (ja) |
JP (2) | JP4550185B2 (ja) |
KR (1) | KR100299594B1 (ja) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3539887B2 (ja) * | 1999-04-09 | 2004-07-07 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6451666B2 (en) * | 1999-12-27 | 2002-09-17 | Hyundai Electronics Industries Co., Ltd | Method for forming a lower electrode by using an electroplating method |
KR100331568B1 (ko) * | 2000-05-26 | 2002-04-06 | 윤종용 | 반도체 메모리 소자 및 그 제조방법 |
KR100593955B1 (ko) * | 2000-06-28 | 2006-06-30 | 매그나칩 반도체 유한회사 | 반도체 메모리 소자의 스토리지 노드 형성방법 |
KR100653982B1 (ko) * | 2000-09-04 | 2006-12-05 | 주식회사 하이닉스반도체 | 반도체 메모리장치의 스토리지노드 전극 제조 방법 |
KR100432785B1 (ko) * | 2001-12-20 | 2004-05-24 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100976412B1 (ko) * | 2003-06-30 | 2010-08-17 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 제조방법 |
KR100781858B1 (ko) * | 2006-01-06 | 2007-12-03 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
JP2010161173A (ja) * | 2009-01-07 | 2010-07-22 | Renesas Electronics Corp | 半導体記憶装置 |
KR101565797B1 (ko) * | 2009-02-16 | 2015-11-05 | 삼성전자주식회사 | 콘택 플러그를 포함하는 반도체 장치 |
US20120142172A1 (en) * | 2010-03-25 | 2012-06-07 | Keith Fox | Pecvd deposition of smooth polysilicon films |
US9028924B2 (en) | 2010-03-25 | 2015-05-12 | Novellus Systems, Inc. | In-situ deposition of film stacks |
US8741394B2 (en) * | 2010-03-25 | 2014-06-03 | Novellus Systems, Inc. | In-situ deposition of film stacks |
US8709551B2 (en) * | 2010-03-25 | 2014-04-29 | Novellus Systems, Inc. | Smooth silicon-containing films |
KR20120100003A (ko) * | 2011-03-02 | 2012-09-12 | 삼성전자주식회사 | 보우잉 방지막을 사용하여 반도체 소자를 제조하는 방법 |
US9165788B2 (en) | 2012-04-06 | 2015-10-20 | Novellus Systems, Inc. | Post-deposition soft annealing |
US9117668B2 (en) | 2012-05-23 | 2015-08-25 | Novellus Systems, Inc. | PECVD deposition of smooth silicon films |
US9388491B2 (en) | 2012-07-23 | 2016-07-12 | Novellus Systems, Inc. | Method for deposition of conformal films with catalysis assisted low temperature CVD |
US10043706B2 (en) | 2013-01-18 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company Limited | Mitigating pattern collapse |
US8895415B1 (en) | 2013-05-31 | 2014-11-25 | Novellus Systems, Inc. | Tensile stressed doped amorphous silicon |
KR102462134B1 (ko) * | 2015-05-19 | 2022-11-02 | 삼성전자주식회사 | 배선 구조물, 배선 구조물 형성 방법, 반도체 장치 및 반도체 장치의 제조 방법 |
CN109003938A (zh) * | 2018-07-26 | 2018-12-14 | 长鑫存储技术有限公司 | 半导体接触结构、存储器结构及其制备方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3010945B2 (ja) * | 1991-12-13 | 2000-02-21 | 日本電気株式会社 | セルフアライン・コンタクト孔の形成方法 |
US5763286A (en) * | 1994-09-14 | 1998-06-09 | Micron Semiconductor, Inc. | Process for manufacturing a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate which stores charge on inner and outer surfaces |
JP2827958B2 (ja) * | 1995-04-27 | 1998-11-25 | 日本電気株式会社 | 半導体記憶装置の容量素子の製造方法 |
KR0155886B1 (ko) * | 1995-09-19 | 1998-10-15 | 김광호 | 고집적 dram 셀의 제조방법 |
TW315510B (ja) * | 1995-12-26 | 1997-09-11 | Samsung Electronics Co Ltd | |
JP2790110B2 (ja) * | 1996-02-28 | 1998-08-27 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH09270461A (ja) * | 1996-03-29 | 1997-10-14 | Mitsubishi Electric Corp | 半導体装置 |
JPH09307077A (ja) * | 1996-05-20 | 1997-11-28 | Sony Corp | 半導体装置の製造方法 |
JP2962250B2 (ja) * | 1996-11-12 | 1999-10-12 | 日本電気株式会社 | 半導体記憶装置の製造方法 |
JP2819498B2 (ja) * | 1996-11-26 | 1998-10-30 | 台湾茂▲しい▼電子股▲ふん▼有限公司 | 両側に皺のあるケース型コンデンサを有するdramの製造方法 |
JP3396144B2 (ja) * | 1997-01-23 | 2003-04-14 | 三菱電機株式会社 | 半導体記憶装置およびその製造方法 |
JPH1154724A (ja) * | 1997-08-06 | 1999-02-26 | Sony Corp | 半導体装置の製造方法 |
KR100303059B1 (ko) * | 1998-03-30 | 2001-11-30 | 윤종용 | 디램셀커패시터의제조방법 |
-
1998
- 1998-07-13 KR KR1019980028191A patent/KR100299594B1/ko not_active IP Right Cessation
-
1999
- 1999-07-12 JP JP19778599A patent/JP4550185B2/ja not_active Expired - Fee Related
- 1999-07-13 US US09/353,024 patent/US6207574B1/en not_active Expired - Lifetime
-
2007
- 2007-03-19 JP JP2007070975A patent/JP4896781B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100299594B1 (ko) | 2001-09-22 |
JP4550185B2 (ja) | 2010-09-22 |
JP2000068481A (ja) | 2000-03-03 |
US6207574B1 (en) | 2001-03-27 |
KR20000008401A (ko) | 2000-02-07 |
JP2007227944A (ja) | 2007-09-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4896781B2 (ja) | Dram装置の製造方法 | |
US6649508B1 (en) | Methods of forming self-aligned contact structures in semiconductor integrated circuit devices | |
KR100503519B1 (ko) | 반도체 장치 및 그 제조방법 | |
KR100539272B1 (ko) | 반도체 장치 및 그 제조방법 | |
KR100414220B1 (ko) | 공유 콘택을 가지는 반도체 장치 및 그 제조 방법 | |
KR100476690B1 (ko) | 반도체 장치 및 그 제조방법 | |
KR100936585B1 (ko) | 반도체 장치 및 그 제조 방법 | |
KR100553835B1 (ko) | 캐패시터 및 그 제조 방법 | |
KR100545866B1 (ko) | 커패시터 및 그 제조 방법 | |
US20030048679A1 (en) | Methods of forming contact holes using multiple insulating layers and integrated circuit devices having the same | |
JPH11354641A (ja) | 半導体装置の製造方法 | |
JP2002280452A (ja) | 効果的に短絡を防止できる集積回路装置およびその製造方法 | |
KR101168606B1 (ko) | 반도체 장치의 배선 구조물 및 이의 형성 방법 | |
JP2990497B2 (ja) | Cmosアナログ半導体装置の製造方法 | |
US6404020B1 (en) | Method of forming contact pads in a semiconductor device and a semiconductor device formed using the method | |
KR100576083B1 (ko) | 반도체 장치 및 그 제조방법 | |
KR100356776B1 (ko) | 반도체소자의 자기정렬 콘택 구조체를 형성하는 방법 | |
JPH1197529A (ja) | 半導体装置の製造方法 | |
JP3172229B2 (ja) | 半導体装置の製造方法 | |
KR100712493B1 (ko) | 반도체 소자 및 그 제조방법 | |
KR100349345B1 (ko) | 반도체 장치의 비트라인 및 그 제조방법 | |
KR20090008607A (ko) | 콘택 형성 방법 | |
KR20050078777A (ko) | 반도체 소자의 자기 정렬 콘택홀 형성 방법 | |
JPH0613580A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090811 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101005 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110105 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110802 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111101 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111122 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111221 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150106 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |