JP4892044B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4892044B2
JP4892044B2 JP2009183673A JP2009183673A JP4892044B2 JP 4892044 B2 JP4892044 B2 JP 4892044B2 JP 2009183673 A JP2009183673 A JP 2009183673A JP 2009183673 A JP2009183673 A JP 2009183673A JP 4892044 B2 JP4892044 B2 JP 4892044B2
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JP
Japan
Prior art keywords
clock generation
circuit
flip
inverter
flop
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JP2009183673A
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English (en)
Japanese (ja)
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JP2011040826A (ja
JP2011040826A5 (enExample
Inventor
野 宗 昭 前
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2009183673A priority Critical patent/JP4892044B2/ja
Priority to US12/723,796 priority patent/US8274319B2/en
Publication of JP2011040826A publication Critical patent/JP2011040826A/ja
Publication of JP2011040826A5 publication Critical patent/JP2011040826A5/ja
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Publication of JP4892044B2 publication Critical patent/JP4892044B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type
    • H03K3/35625—Bistable circuits of the primary-secondary type using complementary field-effect transistors

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2009183673A 2009-08-06 2009-08-06 半導体装置 Active JP4892044B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009183673A JP4892044B2 (ja) 2009-08-06 2009-08-06 半導体装置
US12/723,796 US8274319B2 (en) 2009-08-06 2010-03-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009183673A JP4892044B2 (ja) 2009-08-06 2009-08-06 半導体装置

Publications (3)

Publication Number Publication Date
JP2011040826A JP2011040826A (ja) 2011-02-24
JP2011040826A5 JP2011040826A5 (enExample) 2011-09-15
JP4892044B2 true JP4892044B2 (ja) 2012-03-07

Family

ID=43534369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009183673A Active JP4892044B2 (ja) 2009-08-06 2009-08-06 半導体装置

Country Status (2)

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US (1) US8274319B2 (enExample)
JP (1) JP4892044B2 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5724408B2 (ja) * 2011-01-27 2015-05-27 富士通セミコンダクター株式会社 半導体装置
US8547155B2 (en) * 2011-08-22 2013-10-01 Cisco Technology, Inc. Soft error robust low power latch device layout techniques
US8482314B2 (en) * 2011-11-08 2013-07-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for improved multiplexing using tri-state inverter
JP5875996B2 (ja) * 2013-02-13 2016-03-02 株式会社東芝 フリップフロップ回路
EP3123522A4 (en) * 2014-03-27 2017-11-22 Intel Corporation Multiplexor logic functions implemented with circuits having tunneling field effect transistors (tfets)
CN105811922A (zh) * 2015-01-15 2016-07-27 联发科技股份有限公司 低功耗保持触发器
US9948282B2 (en) * 2015-01-15 2018-04-17 Mediatek Inc. Low-power retention flip-flops
US9496854B2 (en) * 2015-03-10 2016-11-15 International Business Machines Corporation High-speed latch circuits by selective use of large gate pitch
JP6396834B2 (ja) * 2015-03-23 2018-09-26 ルネサスエレクトロニクス株式会社 半導体装置
KR102386907B1 (ko) * 2015-09-10 2022-04-14 삼성전자주식회사 반도체 집적 회로
JP6453732B2 (ja) 2015-09-11 2019-01-16 株式会社東芝 半導体集積回路
TWI575875B (zh) * 2015-10-29 2017-03-21 智原科技股份有限公司 正反器電路
US9660627B1 (en) 2016-01-05 2017-05-23 Bitfury Group Limited System and techniques for repeating differential signals
US9514264B1 (en) 2016-01-05 2016-12-06 Bitfury Group Limited Layouts of transmission gates and related systems and techniques
US9645604B1 (en) 2016-01-05 2017-05-09 Bitfury Group Limited Circuits and techniques for mesochronous processing
JP2019008859A (ja) * 2017-06-28 2019-01-17 東芝メモリ株式会社 半導体装置
CN111095528B (zh) * 2017-09-11 2024-03-08 索尼半导体解决方案公司 半导体集成电路
KR102362016B1 (ko) 2017-09-19 2022-02-10 삼성전자주식회사 마스터 슬레이브 플립 플롭
KR102367860B1 (ko) 2018-01-03 2022-02-24 삼성전자주식회사 반도체 장치
WO2019171937A1 (ja) * 2018-03-07 2019-09-12 株式会社ソシオネクスト 半導体集積回路装置
US10522542B1 (en) 2018-06-28 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Double rule integrated circuit layouts for a dual transmission gate
US11386254B2 (en) 2018-12-13 2022-07-12 Samsung Electronics Co., Ltd. Semiconductor circuit and semiconductor circuit layout system
US10868524B2 (en) 2018-12-13 2020-12-15 Samsung Electronics Co., Ltd. Semiconductor circuit and semiconductor circuit layout system
KR102719776B1 (ko) * 2019-08-07 2024-10-21 삼성전자주식회사 멀티-하이트 스탠다드 셀로 구현되는 세미-다이나믹 플립-플롭 및 이를 포함하는 집적 회로의 설계 방법
KR102834486B1 (ko) 2019-09-06 2025-07-17 삼성전자주식회사 반도체 소자
CN112614837A (zh) * 2019-10-04 2021-04-06 三星电子株式会社 垂直场效应晶体管半导体单元的优化
KR102736651B1 (ko) 2019-11-18 2024-12-02 삼성전자주식회사 스캔 플립플롭 및 이를 포함하는 스캔 테스트 회로
KR102853671B1 (ko) 2020-01-03 2025-09-03 삼성전자주식회사 표준 셀을 포함하는 반도체 장치
US11296682B2 (en) * 2020-04-01 2022-04-05 Taiwan Semiconductor Manufacturing Company Ltd. Input circuit of a flip-flop and associated manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10134591A (ja) * 1996-10-28 1998-05-22 Toshiba Corp ダィナミックレジスタを含む半導体集積回路
JPH1155081A (ja) * 1997-08-07 1999-02-26 Sony Corp フリップフロップ回路および回路設計システム
JP2001332626A (ja) * 2000-05-24 2001-11-30 Fujitsu Ltd 半導体集積回路の設計方法
US6680622B2 (en) * 2002-05-14 2004-01-20 Stmicroelectronics, Inc. Method and system for disabling a scanout line of a register flip-flop
US7053424B2 (en) * 2002-10-31 2006-05-30 Yamaha Corporation Semiconductor integrated circuit device and its manufacture using automatic layout
US6975152B1 (en) * 2003-04-22 2005-12-13 Advanced Micro Devices, Inc. Flip flop supporting glitchless operation on a one-hot bus and method

Also Published As

Publication number Publication date
JP2011040826A (ja) 2011-02-24
US8274319B2 (en) 2012-09-25
US20110032016A1 (en) 2011-02-10

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