JP4880006B2 - 流れ防止用ダムを備えたプリント基板の製造方法 - Google Patents
流れ防止用ダムを備えたプリント基板の製造方法 Download PDFInfo
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- JP4880006B2 JP4880006B2 JP2009032914A JP2009032914A JP4880006B2 JP 4880006 B2 JP4880006 B2 JP 4880006B2 JP 2009032914 A JP2009032914 A JP 2009032914A JP 2009032914 A JP2009032914 A JP 2009032914A JP 4880006 B2 JP4880006 B2 JP 4880006B2
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- 230000008569 process Effects 0.000 claims description 25
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- BWHMMNNQKKPAPP-UHFFFAOYSA-L potassium carbonate Chemical compound [K+].[K+].[O-]C([O-])=O BWHMMNNQKKPAPP-UHFFFAOYSA-L 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H01L2224/8119—Arrangement of the bump connectors prior to mounting
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2203/04—Soldering or other types of metallurgic bonding
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- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
- Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal
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Description
104 ソルダーパッド
106 ソルダーレジスト層
110 ドライフィルムレジスト
110a 未露光されたドライフィルムレジスト
110b 1次露光されたドライフィルムレジスト
110c 流れ防止用ダム
112 開口部
114 ソルダーペースト
116 ソルダーバンプ
118 半導体チップ
120 アンダーフィル液
Claims (7)
- (A)ソルダーパッドが形成されたベース基板にドライフィルムレジストを塗布し、前
記ドライフィルムレジストを1次露光させる段階;
(B)前記ベース基板の縁部に形成された1次露光された前記ドライフィルムレジスト
を2次露光させて流れ防止用ダムを形成する段階;
(C)前記ソルダーパッドが露出するように、露光されていない前記ドライフィルムレ
ジストを除去して開口部を形成する段階;
(D)前記開口部にソルダーペーストを印刷し、リフロー工程によってソルダーバンプ
を形成する段階;及び
(E)1次露光された前記ドライフィルムレジストを除去する段階;
を含むことを特徴とする、流れ防止用ダムを備えたプリント基板の製造方法。 - 前記(E)段階の後、(F)前記ソルダーパッドに形成されたソルダーバンプを介して
半導体チップをフリップチップボンディングする段階をさらに含むことを特徴とする、請
求項1に記載の流れ防止用ダムを備えたプリント基板の製造方法。 - 前記(F)段階の後、(G)前記半導体チップと前記ベース基板の間のギャップにアン
ダーフィル液を注入する段階をさらに含むことを特徴とする、請求項2に記載の流れ防止
用ダムを備えたプリント基板の製造方法。 - 前記(F)段階の後、(G)前記半導体チップと前記ベース基板の間のギャップにアン
ダーフィル液を注入する段階をさらに含み、
前記半導体チップと前記ベース基板の間のギャップに注入される前記アンダーフィル液
の外部流出を防止するために前記流れ防止用ダムが前記半導体チップの外縁部に沿って前
記ベース基板上に突出するように形成されていることを特徴とする、請求項2に記載の流
れ防止用ダムを備えたプリント基板の製造方法。 - 前記流れ防止用ダムは、前記ベース基板上にフリップチップボンディングされる前記半
導体チップの上面の高さよりは低くて前記半導体チップと前記ベース基板の間のギャップ
よりは高い高さを持つことを特徴とする、請求項2に記載の流れ防止用ダムを備えたプリ
ント基板の製造方法。 - 前記流れ防止用ダムは、前記ベース基板の外縁部と前記半導体チップの外縁部の間に備
えられることを特徴とする、請求項2に記載の流れ防止用ダムを備えたプリント基板の製
造方法。 - 前記ベース基板には、ソルダーパッドを露出させるオープン部を持つソルダーレジスト
層が形成されていることを特徴とする、請求項1に記載の流れ防止用ダムを備えたプリン
ト基板の製造方法。
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KR1020080112362A KR101022942B1 (ko) | 2008-11-12 | 2008-11-12 | 흐름 방지용 댐을 구비한 인쇄회로기판 및 그 제조방법 |
KR10-2008-0112362 | 2008-11-12 |
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JP2010118634A JP2010118634A (ja) | 2010-05-27 |
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US (2) | US8039761B2 (ja) |
JP (1) | JP4880006B2 (ja) |
KR (1) | KR101022942B1 (ja) |
CN (1) | CN101740538B (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5360221B2 (ja) * | 2009-09-16 | 2013-12-04 | 株式会社村田製作所 | 電子部品内蔵モジュール |
CN102906867B (zh) * | 2010-05-20 | 2016-04-27 | 株式会社Lg化学 | 包括底部填充用围堰的印刷电路板及其制造方法 |
WO2011145828A2 (ko) * | 2010-05-20 | 2011-11-24 | 주식회사 엘지화학 | 언더-필용 댐을 포함하는 인쇄 회로 기판 및 이의 제조 방법 |
KR101067216B1 (ko) | 2010-05-24 | 2011-09-22 | 삼성전기주식회사 | 인쇄회로기판 및 이를 구비하는 반도체 패키지 |
JP5662855B2 (ja) | 2011-03-25 | 2015-02-04 | 株式会社日立製作所 | プリント基板の製造装置および製造方法 |
CN102157445A (zh) * | 2011-03-31 | 2011-08-17 | 无锡中微高科电子有限公司 | 提高集成电路封装连接强度的方法 |
US9966350B2 (en) * | 2011-06-06 | 2018-05-08 | Maxim Integrated Products, Inc. | Wafer-level package device |
US9025339B2 (en) * | 2011-12-29 | 2015-05-05 | Stmicroelectronics Pte Ltd. | Adhesive dam |
US9263378B1 (en) | 2014-08-04 | 2016-02-16 | International Business Machines Corporation | Ball grid array and land grid array assemblies fabricated using temporary resist |
KR102249660B1 (ko) | 2014-08-14 | 2021-05-10 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판의 제조 방법 |
US10431533B2 (en) * | 2014-10-31 | 2019-10-01 | Ati Technologies Ulc | Circuit board with constrained solder interconnect pads |
TW201624645A (zh) * | 2014-12-26 | 2016-07-01 | 矽品精密工業股份有限公司 | 半導體結構及其製法 |
US10325783B2 (en) * | 2015-06-09 | 2019-06-18 | Infineon Technologies Ag | Semiconductor device including structure to control underfill material flow |
JP6591234B2 (ja) * | 2015-08-21 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2018056234A (ja) * | 2016-09-27 | 2018-04-05 | キヤノン株式会社 | プリント回路板、電子機器及びプリント回路板の製造方法 |
US10398037B2 (en) * | 2017-02-20 | 2019-08-27 | Canon Kabushiki Kaisha | Printed circuit board and electronic device |
KR102000592B1 (ko) * | 2017-07-04 | 2019-07-16 | 주식회사 엔디디 | 바이오 감지 장치 및 그 제조방법 |
US11367700B2 (en) | 2017-12-29 | 2022-06-21 | Huawei Technologies Co., Ltd. | Electronic package, terminal and method for processing electronic package |
KR102068162B1 (ko) * | 2018-04-20 | 2020-01-20 | (주)파트론 | 칩 패키지 단자 구조물 |
JP2020053563A (ja) * | 2018-09-27 | 2020-04-02 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
KR102565715B1 (ko) * | 2019-05-03 | 2023-08-10 | 삼성전자주식회사 | 반도체 패키지 |
JP2021072423A (ja) | 2019-11-01 | 2021-05-06 | イビデン株式会社 | 配線板及びその製造方法 |
KR20210098659A (ko) | 2020-02-03 | 2021-08-11 | 삼성전자주식회사 | 댐 구조물을 갖는 반도체 패키지 |
CN111970851A (zh) * | 2020-08-25 | 2020-11-20 | 深圳市景旺电子股份有限公司 | 一种液态防水胶阻流的方法 |
CN112738990B (zh) * | 2020-11-12 | 2022-08-23 | 深圳市艾比森光电股份有限公司 | 一种印刷电路板、显示模组及led显示屏 |
CN113488495B (zh) * | 2021-06-16 | 2022-09-09 | 深圳市华星光电半导体显示技术有限公司 | 显示面板及其制备方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55156447U (ja) * | 1979-04-24 | 1980-11-11 | ||
JPS5882541A (ja) * | 1981-11-12 | 1983-05-18 | Omron Tateisi Electronics Co | 樹脂コ−テイング方法 |
JP2842704B2 (ja) * | 1991-04-17 | 1999-01-06 | イビデン株式会社 | プリント配線板およびその製造方法 |
US5162257A (en) * | 1991-09-13 | 1992-11-10 | Mcnc | Solder bump fabrication method |
JPH05299535A (ja) * | 1992-04-23 | 1993-11-12 | Matsushita Electric Works Ltd | 半導体装置 |
JP3674954B2 (ja) * | 1993-03-02 | 2005-07-27 | Jsr株式会社 | 回路基板形成用アルカリ現像型液状フォトレジスト組成物 |
JPH08125305A (ja) * | 1994-10-26 | 1996-05-17 | Mitsumi Electric Co Ltd | メンブレン基板 |
CN1080981C (zh) * | 1995-06-06 | 2002-03-13 | 揖斐电株式会社 | 印刷电路板 |
JPH11150206A (ja) * | 1997-11-17 | 1999-06-02 | Oki Electric Ind Co Ltd | 半導体素子の実装基板 |
JP3646500B2 (ja) * | 1998-01-20 | 2005-05-11 | 株式会社村田製作所 | 電子回路装置 |
JP4087876B2 (ja) * | 1998-08-10 | 2008-05-21 | 富士通株式会社 | ハンダバンプの形成方法 |
US6461953B1 (en) * | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
US8035214B1 (en) * | 1998-12-16 | 2011-10-11 | Ibiden Co., Ltd. | Conductive connecting pin for package substance |
JP2000260818A (ja) * | 1999-03-05 | 2000-09-22 | Fuji Xerox Co Ltd | プリント配線組立体 |
US6531335B1 (en) * | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
JP4963148B2 (ja) * | 2001-09-18 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2004258181A (ja) * | 2003-02-25 | 2004-09-16 | Fuji Photo Film Co Ltd | 光硬化性感光材料の露光方法と露光装置 |
JP2006173460A (ja) * | 2004-12-17 | 2006-06-29 | Renesas Technology Corp | 半導体装置の製造方法 |
KR100691443B1 (ko) * | 2005-11-16 | 2007-03-09 | 삼성전기주식회사 | 플립칩 패키지 및 그 제조방법 |
TW200746964A (en) * | 2006-01-27 | 2007-12-16 | Ibiden Co Ltd | Method of manufacturing printed wiring board |
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2009
- 2009-02-16 JP JP2009032914A patent/JP4880006B2/ja not_active Expired - Fee Related
- 2009-02-27 US US12/379,759 patent/US8039761B2/en not_active Expired - Fee Related
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US8336201B2 (en) | 2012-12-25 |
US20100116534A1 (en) | 2010-05-13 |
CN101740538B (zh) | 2012-05-16 |
US8039761B2 (en) | 2011-10-18 |
KR20100053307A (ko) | 2010-05-20 |
KR101022942B1 (ko) | 2011-03-16 |
JP2010118634A (ja) | 2010-05-27 |
US20120000067A1 (en) | 2012-01-05 |
CN101740538A (zh) | 2010-06-16 |
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