JP4842609B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4842609B2 JP4842609B2 JP2005293234A JP2005293234A JP4842609B2 JP 4842609 B2 JP4842609 B2 JP 4842609B2 JP 2005293234 A JP2005293234 A JP 2005293234A JP 2005293234 A JP2005293234 A JP 2005293234A JP 4842609 B2 JP4842609 B2 JP 4842609B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下に、本発明の第1の実施形態に係る半導体装置の製造方法について説明する。
まず、図1(a)に示すように、半導体基板100の上に、通常の素子分離形成方法によって、酸化膜よりなる素子分離101を形成した後、コアトランジスタ形成領域Raにおいて、半導体基板100の上に、例えば膜厚が2nmのシリコン窒化酸化膜102a’を形成する。また一方で、I/Oトランジスタ形成領域Rbにおいて、例えば膜厚が8nmのシリコン窒化酸化膜102b’を形成する。続いて、シリコン窒化酸化膜102a’及びシリコン窒化酸化膜102b’の上にポリシリコン膜103を形成する。
以下に、本発明の第2の実施形態に係る半導体装置の製造方法について説明する。
以下に、本発明の第3の実施形態に係る半導体装置の製造方法について説明する。
101 素子分離
102a’、102b’、102c’、102d’ シリコン窒化酸化膜
103 ポリシリコン膜
102a、102b、102c、102d ゲート絶縁膜
103a、103b、103c、103d ゲート電極
104a、104c、104d エクステンション拡散層
105a、105b、105c、105d サイドウォール
106a、106b、106c、106d ソース・ドレイン拡散層
107a、107b、107c、107d ニッケルシリサイド層
108 第1の層間絶縁膜
109a、109b、109c、109d プラグ
110 第2の層間絶縁膜
111a、111b、111c、111d 配線
Ra コアトランジスタ形成領域
Rb I/Oトランジスタ形成領域
pd コアトランジスタにおける単位ゲート当たりのドレイン寄生抵抗
ps コアトランジスタにおける単位ゲート当たりのソース寄生抵抗
c コアトランジスタにおける単位ゲート当たりのチャネル抵抗
PD I/Oトランジスタにおける単位ゲート当たりのドレイン寄生抵抗
PS I/Oトランジスタにおける単位ゲート当たりのソース寄生抵抗
C I/Oトランジスタにおける単位ゲート当たりのチャネル抵抗
Claims (4)
- 同一の半導体基板上に、相対的に低い電源電圧で駆動する第1のMIS型トランジスタと相対的に高い電源電圧で駆動する第2のMIS型トランジスタとを有する半導体装置であって、
第1のMIS型トランジスタは、
前記半導体基板上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜の上に形成された第1のゲート電極と、
前記第1のゲート電極の側面に形成された第1の側壁絶縁膜と、
前記半導体基板における前記第1のゲート電極の側方に位置する領域に形成された第1の不純物拡散領域とを備え、
前記第2のMIS型トランジスタは、
前記半導体基板上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜の上に形成された第2のゲート電極と、
前記第2のゲート電極の側面に形成された第2の側壁絶縁膜と、
前記半導体基板における前記第2のゲート電極の側方に位置する領域に形成された第2の不純物拡散領域とを備え、
前記第1のゲート絶縁膜の直下に位置する第1のチャネル領域と前記第1の不純物拡散領域とはオフセットしていない一方で、前記第2のゲート絶縁膜の直下に位置する第2のチャネル領域と前記第2の不純物拡散領域とはオフセットしている構造を有しており、
前記半導体基板における前記第1の側壁絶縁膜下に位置する領域の上面は、前記第1のチャネル領域の上面と同一の高さ位置に存在しており、
前記半導体基板における前記第2の側壁絶縁膜下に位置する領域の上面は、前記第2のチャネル領域の上面よりも低い位置に存在しており、
前記第1の不純物拡散領域及び前記第2の不純物拡散領域はエクステンション拡散領域であり、
前記第1の不純物拡散領域の上面は、前記第1のチャネル領域の上面と同一の高さ位置に存在しており、
前記第2の不純物拡散領域の上面は、前記第2のチャネル領域の上面よりも低い位置に存在していることを特徴とする請求項1に記載の半導体装置。 - 前記第2のチャネル領域の上面と前記第2の不純物拡散領域とは、前記第2のゲート電極の端部下において鉛直方向にオフセットしていることを特徴とする請求項1に記載の半導体装置。
- 前記半導体基板における前記第2のゲート電極の側方に位置する部分の上面位置と前記第2のゲート絶縁膜の下面位置との差分だけオフセットしていることを特徴とする請求項2に記載の半導体装置。
- 前記第2の不純物拡散領域の濃度は、前記第1の不純物拡散領域の濃度よりも低いことを特徴とする請求項1〜3のうちのいずれか1項に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2005293234A JP4842609B2 (ja) | 2005-10-06 | 2005-10-06 | 半導体装置 |
US11/480,902 US7468540B2 (en) | 2005-10-06 | 2006-07-06 | Semiconductor device and method for manufacturing the same |
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JP2005293234A JP4842609B2 (ja) | 2005-10-06 | 2005-10-06 | 半導体装置 |
Publications (2)
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JP2007103753A JP2007103753A (ja) | 2007-04-19 |
JP4842609B2 true JP4842609B2 (ja) | 2011-12-21 |
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JP2005293234A Active JP4842609B2 (ja) | 2005-10-06 | 2005-10-06 | 半導体装置 |
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JP (1) | JP4842609B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US8828855B2 (en) * | 2007-04-30 | 2014-09-09 | Texas Instruments Incorporated | Transistor performance using a two-step damage anneal |
JP2010232362A (ja) * | 2009-03-26 | 2010-10-14 | Oki Semiconductor Co Ltd | 半導体素子およびその製造方法 |
JP6119454B2 (ja) * | 2013-06-24 | 2017-04-26 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び半導体装置を測定する方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0488669A (ja) * | 1990-07-31 | 1992-03-23 | Fujitsu Ltd | 半導体装置 |
JPH04268768A (ja) * | 1991-02-25 | 1992-09-24 | Fujitsu Ltd | 半導体装置及びその製造方法 |
KR930001452A (ko) * | 1991-06-21 | 1993-01-16 | 김광호 | 트렌치형 소스/드레인 mosfet 및 그 제조방법 |
JPH06244366A (ja) * | 1993-02-12 | 1994-09-02 | Sony Corp | Mosトランジスタの製造方法 |
JPH06244411A (ja) * | 1993-02-18 | 1994-09-02 | Nippon Steel Corp | 半導体装置 |
US6498376B1 (en) * | 1994-06-03 | 2002-12-24 | Seiko Instruments Inc | Semiconductor device and manufacturing method thereof |
JPH10144804A (ja) * | 1996-11-08 | 1998-05-29 | Toshiba Microelectron Corp | 半導体記憶装置及びその製造方法 |
JP3262752B2 (ja) * | 1997-03-28 | 2002-03-04 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6157062A (en) * | 1998-04-13 | 2000-12-05 | Texas Instruments Incorporated | Integrating dual supply voltage by removing the drain extender implant from the high voltage device |
JP3144385B2 (ja) * | 1998-07-15 | 2001-03-12 | 日本電気株式会社 | 半導体装置とその製造方法 |
JP2000077536A (ja) * | 1998-09-03 | 2000-03-14 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002118255A (ja) | 2000-07-31 | 2002-04-19 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2003007717A (ja) * | 2001-06-19 | 2003-01-10 | Sharp Corp | 半導体装置及びその製造方法 |
DE10131276B4 (de) | 2001-06-28 | 2007-08-02 | Infineon Technologies Ag | Feldeffekttransistor und Verfahren zu seiner Herstellung |
JP2003218232A (ja) * | 2002-01-25 | 2003-07-31 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4198401B2 (ja) | 2002-06-28 | 2008-12-17 | 株式会社東芝 | 電界効果型トランジスタ |
JP2004221245A (ja) * | 2003-01-14 | 2004-08-05 | Seiko Epson Corp | 半導体装置及びその製造方法 |
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US20070080373A1 (en) | 2007-04-12 |
US7468540B2 (en) | 2008-12-23 |
JP2007103753A (ja) | 2007-04-19 |
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