JP4754270B2 - 半導体素子のゲート電極形成方法 - Google Patents

半導体素子のゲート電極形成方法 Download PDF

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JP4754270B2
JP4754270B2 JP2005156759A JP2005156759A JP4754270B2 JP 4754270 B2 JP4754270 B2 JP 4754270B2 JP 2005156759 A JP2005156759 A JP 2005156759A JP 2005156759 A JP2005156759 A JP 2005156759A JP 4754270 B2 JP4754270 B2 JP 4754270B2
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基元 南
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Description

本発明は半導体素子のゲート電極形成方法に関し、窒化膜で構成されたハードマスク層の蒸着後追加的な表面蒸着処理を介し窒化膜表面の格子構造を従来より緻密にし、ゲート電極の形成時に前記ハードマスク層のエッチング率を減少させてハードマスク層が残される厚さを増加させる半導体素子のゲート電極形成方法に関する。
従来の技術に係る半導体素子のゲート電極形成方法は、半導体基板の上部にゲート酸化膜、ポリシリコン層、金属層及びハードマスク層を順次形成し、前記ハードマスク層の表面に反射防止膜（ＡＲＣ）を形成した後でゲート電極領域を定義する感光膜パターンを形成する。次に、前記感光膜パターンをマスクに前記ハードマスク層をエッチングしてハードマスク層パターンを形成し、前記ハードマスク層パターンをマスクに前記金属層、ポリシリコン層及びゲート酸化膜をエッチングして半導体素子のゲート電極を形成する。
前述の従来の技術に係る半導体素子のゲート電極形成方法において、ゲート電極形成の工程時にハードマスク層の残留する厚さが増加するほど、後続工程のランディングプラグコンタクトエッチング工程時にＳＡＣ工程のマージンが向上するが、前記ハードマスク層の蒸着厚さを増加させることになると、ゲート電極周辺回路部の線幅が増加及び変形するという問題点がある。
本発明は前記のような問題点を解決するためのものであり、窒化膜で構成されたハードマスク層の蒸着後追加的な表面蒸着処理を介し窒化膜表面の格子構造を従来より緻密にし、ゲート電極の形成時に前記ハードマスク層のエッチング率を減少させてハードマスク層が残される厚さを増加させる。これにより、周辺回路部の線幅のサイズ増加及び変化を防止する半導体素子のゲート電極形成方法を提供することに本発明の目的がある。
本発明に係る半導体素子のゲート電極形成方法は、半導体基板の上部にゲート酸化膜、ポリシリコン層、金属層及び窒化膜からなるハードマスク層を順次形成する段階と、酸化工程を行ない前記ハードマスク層の表面を酸化させる段階と、前記酸化されたハードマスク層の上部に、シリコンオキシナイトライドでなる反射防止膜を形成する段階と、前記反射防止膜の上部にゲート領域を定義する感光膜パターンを形成する段階と、前記感光膜パターンをマスクに、前記反射防止膜及びハードマスク層をエッチングしてハードマスク層パターンを形成した後、前記感光膜パターンを除去する段階と、前記感光膜パターンを除去した後、前記ハードマスク層パターンをエッチングマスクに、前記金属層、ポリシリコン層及びゲート酸化膜をエッチングしてゲート電極を形成する段階とを含むことを特徴とする。
本発明に係る半導体素子のゲート電極形成方法は、前記ハードマスク層表面の結合力が増加し安定的で堅固な結合を形成することにより、前記ハードマスク層のエッチング率が減少し残るハードマスク層の最終の厚さが増加することになる。したがって、後続工程のランディングプラグコンタクトエッチング時にＳＡＣ工程に対するマージンが向上し、初期に蒸着されるハードマスク層の厚さを減少させてゲート電極形成の過程で発生する周辺回路部の線幅の増加及び変化を防止するという効果が得られる。
以下では、本発明の実施の形態を図を参照しながら詳しく説明する。
図１ａ〜図１ｄは、本発明に係る半導体素子のゲート電極形成方法を示した断面図等である。
図１ａに示されているように、半導体基板１００の上部にゲート酸化膜１１０、ポリシリコン層１２０、金属層１３０及びハードマスク層１４０を順次形成する。ここで、金属層１３０はタングステンシリサイドで形成し、ハードマスク層１４０は窒化膜で形成するのが好ましい。
図１ｂに示されているように、ハードマスク層１４０の表面に酸化工程を行なう。
前記酸化工程は、酸素ガスをソースに用いたＲＰＥＡ（Remote Plasma Enhanced Atomic）法を利用してハードマスク層１４０の表面を酸化窒化膜１５０に変換させる。前記ＲＰＥＡ法を利用した酸化工程は２５０〜３５０℃の温度で行ない、既に形成されているハードマスク層１４０の表面の窒素イオンと酸素ガスの酸素イオンが反応してＮｘＯｙの結合で５０〜１００Åの酸化窒化膜１５０が形成されるよう行なうのが好ましい。
図１ｃに示されているように、酸化窒化膜１５０の上部に反射防止膜（ＡＲＣ）１６０を形成する。次は、ゲート電極領域を定義する感光膜パターン１７０を形成する。このとき、反射防止膜１６０はシリコンオキシナイトライドで形成するのが好ましい。
図１ｄに示されているように、感光膜パターン１７０をマスクにハードマスク層１４０をエッチングしてハードマスク層パターン１４０ａを形成した後、感光膜パターン１７０を取り除く。ハードマスク層パターン１４０ａをエッチングマスクに金属層１３０、ポリシリコン層１２０及びゲート酸化膜１１０をエッチングしてゲート電極を形成する。
本発明に係る半導体素子のゲート電極形成方法を示す断面図である。 本発明に係る半導体素子のゲート電極形成方法を示す断面図である。 本発明に係る半導体素子のゲート電極形成方法を示す断面図である。 本発明に係る半導体素子のゲート電極形成方法を示す断面図である。
符号の説明
１００ 半導体基板
１１０ ゲート酸化膜
１２０ ポリシリコン層
１３０ 金属層
１４０ ハードマスク層
１４０ａ ハードマスク層パターン
１５０ 酸化窒化膜
１６０ 反射防止膜（ＡＲＣ）
１７０ 感光膜パターン

Claims (5)

  1. 半導体基板の上部にゲート酸化膜、ポリシリコン層、金属層及び窒化膜からなるハードマスク層を順次形成する段階と、
    酸化工程を行ない前記ハードマスク層の表面を酸化させる段階と、
    前記酸化されたハードマスク層の上部に、シリコンオキシナイトライドでなる反射防止膜を形成する段階と、
    前記反射防止膜の上部にゲート領域を定義する感光膜パターンを形成する段階と、
    前記感光膜パターンをマスクに、前記反射防止膜及びハードマスク層をエッチングしてハードマスク層パターンを形成した後、前記感光膜パターンを除去する段階と、
    前記感光膜パターンを除去した後、前記ハードマスク層パターンをエッチングマスクに、前記金属層、ポリシリコン層及びゲート酸化膜をエッチングしてゲート電極を形成する段階と
    を含むことを特徴とする半導体素子のゲート電極形成方法。
  2. 前記金属層はタングステンシリサイドで形成することを特徴とする請求項１に記載の半導体素子のゲート電極形成方法。
  3. 前記酸化工程は、酸素ガスをソースに用いたＲＰＥＡ法を利用して行なうことを特徴とする請求項１に記載の半導体素子のゲート電極形成方法。
  4. 前記ＲＰＥＡ法は、２５０〜３５０℃の温度で行なうことを特徴とする請求項３に記載の半導体素子のゲート電極形成方法。
  5. 前記ハードマスク層のうち酸化されたハードマスク層の厚さは５０〜１００Åであることを特徴とする請求項１に記載の半導体素子のゲート電極形成方法。
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JP3422580B2 (ja) * 1994-12-16 2003-06-30 三菱電機株式会社 半導体装置の製造方法
US6287975B1 (en) * 1998-01-20 2001-09-11 Tegal Corporation Method for using a hard mask for critical dimension growth containment
JP2000058830A (ja) * 1998-05-28 2000-02-25 Texas Instr Inc <Ti> 反射防止構造体とその製造法
JP2000003901A (ja) * 1998-06-16 2000-01-07 Matsushita Electron Corp 半導体装置の製造方法及び半導体製造装置
JP2000150803A (ja) * 1998-09-11 2000-05-30 Mitsubishi Electric Corp 半導体装置の製造方法
US6194323B1 (en) * 1998-12-16 2001-02-27 Lucent Technologies Inc. Deep sub-micron metal etch with in-situ hard mask etch
JP2001237168A (ja) * 2000-02-24 2001-08-31 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2001284582A (ja) * 2000-03-31 2001-10-12 Toshiba Corp 半導体トランジスタの製造方法
US6794279B1 (en) * 2000-05-23 2004-09-21 Advanced Micro Devices, Inc. Passivating inorganic bottom anti-reflective coating (BARC) using rapid thermal anneal (RTA) with oxidizing gas
JP2002093741A (ja) * 2000-09-20 2002-03-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR100425666B1 (ko) * 2001-07-28 2004-04-03 삼성전자주식회사 반도체 장치에서 게이트 전극 형성방법 및 이를 이용한불휘발성 메모리 장치에서 셀 게이트 전극 형성 방법
TWI276153B (en) * 2001-11-12 2007-03-11 Hynix Semiconductor Inc Method for fabricating semiconductor device
JP3827603B2 (ja) * 2002-04-05 2006-09-27 エルピーダメモリ株式会社 半導体装置の製造方法
US7396773B1 (en) * 2002-12-06 2008-07-08 Cypress Semiconductor Company Method for cleaning a gate stack
US7033957B1 (en) * 2003-02-05 2006-04-25 Fasl, Llc ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices
KR100471407B1 (ko) * 2003-06-30 2005-03-14 주식회사 하이닉스반도체 폴리메탈 게이트 전극을 갖는 트랜지스터 제조 방법
US6933219B1 (en) * 2003-11-18 2005-08-23 Advanced Micro Devices, Inc. Tightly spaced gate formation through damascene process
US7154779B2 (en) * 2004-01-21 2006-12-26 Sandisk Corporation Non-volatile memory cell using high-k material inter-gate programming
KR100586009B1 (ko) * 2004-05-31 2006-06-01 삼성전자주식회사 반도체 장치의 제조 방법 및 이를 수행하기 위한 장치
KR100586020B1 (ko) * 2004-11-19 2006-06-01 삼성전자주식회사 반도체 장치의 게이트 형성 방법
US7320914B1 (en) * 2005-02-23 2008-01-22 Spansion Llc System and method for gate formation in a semiconductor device

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