JP2005197474A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2005197474A JP2005197474A JP2004002407A JP2004002407A JP2005197474A JP 2005197474 A JP2005197474 A JP 2005197474A JP 2004002407 A JP2004002407 A JP 2004002407A JP 2004002407 A JP2004002407 A JP 2004002407A JP 2005197474 A JP2005197474 A JP 2005197474A
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- Prior art keywords
- film
- silicon
- trench
- semiconductor device
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】シリコン基板11上に、パッド酸化膜12、シリコン窒化膜13の積層膜が堆積され、さらに積層膜上にポリシリコン膜14が形成されており、レシストマスク15にてポリシリコン膜14、シリコン窒化膜13、パッド酸化膜12が順次エッチングされる。そして、ポリシリコン膜14をマスクとしてシリコン基板11をエッチングしてトレンチ16を形成する。
【選択図】 図5
Description
2、12 パッド酸化膜
3、13 シリコン窒化膜
4、」5 レジストパターン
5、16 トレンチ
14 ポリシリコン膜
Claims (6)
- シリコン基板上に絶縁膜及び該絶縁膜上にシリコン系の膜を形成する工程と、レジストをマスクとして前記シリコン系の膜及び前記絶縁膜をエッチングする工程と、前記レジストを除去した後前記シリコン系の膜をマスクとしてシリコン基板をエッチングしトレンチを形成する工程を含むことを特徴とする半導体装置装置の製造方法。
- 前記シリコン系の膜は、多結晶シリコンあるいはアモルファスシリコンの何れかであることを特徴とする請求項1記載の半導体装置装置の製造方法。
- 前記トレンチの深さは前記シリコン系の膜厚に等しいことを特徴とする請求項1、2記載の半導体装置装置の製造方法。
- 前記絶縁膜はシリコン酸化膜及びシリコン窒化膜の多層膜であることを特徴とする請求項1乃至3記載の半導体装置装置の製造方法。
- 前記多層膜は下層膜がシリコン酸化膜であり、上層膜がシリコン窒化膜である2層膜であることを特徴とする請求項4記載の半導体装置装置の製造方法。
- 前記トレンチのエッチング終点は前記絶縁膜表面の露出を検出することによりおこなわれることを特徴とする請求項1乃至5記載の半導体装置装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004002407A JP2005197474A (ja) | 2004-01-07 | 2004-01-07 | 半導体装置の製造方法 |
US10/866,032 US20050148191A1 (en) | 2004-01-07 | 2004-06-14 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004002407A JP2005197474A (ja) | 2004-01-07 | 2004-01-07 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005197474A true JP2005197474A (ja) | 2005-07-21 |
Family
ID=34709047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004002407A Abandoned JP2005197474A (ja) | 2004-01-07 | 2004-01-07 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20050148191A1 (ja) |
JP (1) | JP2005197474A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007227892A (ja) * | 2005-12-23 | 2007-09-06 | Interuniv Micro Electronica Centrum Vzw | ソース/ドレイン領域の選択的エピタキシャル成長方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100399531C (zh) * | 2005-11-03 | 2008-07-02 | 上海华虹Nec电子有限公司 | 一种特殊结构的硅片 |
CN204760384U (zh) * | 2015-05-18 | 2015-11-11 | 华天科技(昆山)电子有限公司 | 高像素影像传感芯片的晶圆级封装结构 |
CN109920734A (zh) * | 2019-03-13 | 2019-06-21 | 德淮半导体有限公司 | 半导体器件的形成方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
US6015757A (en) * | 1997-07-02 | 2000-01-18 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer |
US5811345A (en) * | 1997-09-18 | 1998-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planarization of shallow- trench- isolation without chemical mechanical polishing |
US6140206A (en) * | 1999-06-14 | 2000-10-31 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures |
JP2001345375A (ja) * | 2000-05-31 | 2001-12-14 | Miyazaki Oki Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
US6737316B2 (en) * | 2001-10-30 | 2004-05-18 | Promos Technologies Inc. | Method of forming a deep trench DRAM cell |
US6613649B2 (en) * | 2001-12-05 | 2003-09-02 | Chartered Semiconductor Manufacturing Ltd | Method for buffer STI scheme with a hard mask layer as an oxidation barrier |
-
2004
- 2004-01-07 JP JP2004002407A patent/JP2005197474A/ja not_active Abandoned
- 2004-06-14 US US10/866,032 patent/US20050148191A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007227892A (ja) * | 2005-12-23 | 2007-09-06 | Interuniv Micro Electronica Centrum Vzw | ソース/ドレイン領域の選択的エピタキシャル成長方法 |
Also Published As
Publication number | Publication date |
---|---|
US20050148191A1 (en) | 2005-07-07 |
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