JP2007227892A - ソース/ドレイン領域の選択的エピタキシャル成長方法 - Google Patents
ソース/ドレイン領域の選択的エピタキシャル成長方法 Download PDFInfo
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- JP2007227892A JP2007227892A JP2006347125A JP2006347125A JP2007227892A JP 2007227892 A JP2007227892 A JP 2007227892A JP 2006347125 A JP2006347125 A JP 2006347125A JP 2006347125 A JP2006347125 A JP 2006347125A JP 2007227892 A JP2007227892 A JP 2007227892A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 abstract description 2
- 125000006850 spacer group Chemical group 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/924—To facilitate selective etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】ソース/ドレイン(S/D)領域の選択的エピタキシャル成長方法であって、基板は第1基板領域(I)と第2基板領域(II)とからなり、第1領域は少なくとも1つのゲートスタックを含む、 基板上に、基板1と同じエッチング化学的特性でエッチング可能である、多結晶シリコンまたは多結晶SiGeのトップ層を形成する工程と、 基板の第1領域(I)から、トップ層5を、第2基板領域(II)の多結晶シリコンまたは多結晶SiGeに対して選択的に除去する工程と、 第2基板領域(II)のトップ層5と、第1基板領域(I)のS/D領域の基板の少なくとも一部とを、少なくとも1つのゲートスタックに対して選択的に、同時に除去する工程と、 第1基板領域(I)に、S/D領域の選択的エピタキシャル成長を行う工程とを含む。
【選択図】図2
Description
基板上に少なくとも多結晶シリコンのトップ層を提供する工程であって、トップ層は、所定のエッチング化学的特性でエッチング可能である工程と、
基板の第1領域から、多結晶シリコンのトップ層を、第2基板領域の多結晶シリコンに対して選択的に除去する工程と、
第2基板領域の多結晶シリコンのトップ層と、第1基板領域の基板の少なくとも一部とを、所定の溶液で同時に除去する工程と、
第1基板領域に、S/D領域の選択的エピタキシャル成長を行う工程とを含む。
Claims (14)
- ソース/ドレイン(S/D)領域の選択的エピタキシャル成長方法であって、半導体材料の基板(1)を提供する工程を含み、該基板は第1基板領域(I)と第2基板領域(II)とからなり、該第1領域は少なくとも1つのゲートスタックを含む該成長方法が、更に、
該基板上に少なくとも多結晶シリコンまたは多結晶SiGeのトップ層(5)を提供する工程であって、該トップ層は、該基板(1)と同じエッチング化学的特性でエッチング可能である工程と、
該基板(1)の該第1領域(I)から、該多結晶シリコンまたは多結晶SiGeのトップ層(5)を、該第2基板領域(II)の該多結晶シリコンまたは多結晶SiGeに対して選択的に除去する工程と、
該第2基板領域(II)の該多結晶シリコンまたは多結晶SiGeのトップ層(5)と、該第1基板領域(I)のS/D領域の該基板の少なくとも一部とを、該少なくとも1つのゲートスタックに対して選択的に、同時に除去する工程と、
該第1基板領域(I)に、S/D領域の選択的エピタキシャル成長を行う工程と、を含む選択的エピタキシャル成長方法。 - 上記多結晶シリコンまたは多結晶SiGeのトップ層(5)と上記基板との間に、ストップ層(3、6)が形成され、該ストップ層は、該トップ層(5)と同じエッチング化学的特性でエッチングされない請求項1にかかる選択的エピタキシャル成長方法。
- 上記第1領域(I)から、上記多結晶シリコンまたは多結晶SiGeのトップ層(5)を除去する工程が、上記ストップ層(3、6)が露出するまで行われる請求項2にかかる選択的エピタキシャル成長方法。
- 上記同時に除去する工程が、上記ストップ層(3、6)を除去するブレークスルーエッチング工程を含む請求項3にかかる選択的エピタキシャル成長方法。
- 更に、上記第2領域(II)を覆い上記第1領域(I)を露出させるために、上記多結晶シリコンまたは多結晶SiGeのトップ層(5)の上にレジスト層を堆積する工程とパターニングする工程とを含む請求項1にかかる選択的エピタキシャル成長方法。
- 上記第1領域(I)から上記多結晶シリコンまたは多結晶SiGeのトップ層(5)を除去する工程と、同時に除去する工程との間に、上記第2領域(II)の上のレジストを除去する工程が行われる請求項5にかかる選択的エピタキシャル成長方法。
- 上記第2領域が、少なくとも1つのゲートスタックを含む請求項1にかかる方法。
- 更に、最終点を引き起こす工程を含む請求項3にかかる方法。
- 上記基板が、シリコン、ゲルマニウム、またはSiGeからなる請求項1にかかる方法。
- 上記基板と上記多結晶シリコンのトップ層が、SF6とHBrの混合物でエッチングされる請求項1にかかる方法。
- 上記多結晶シリコンまたは多結晶SiGeのトップ層(5)が、20nmから150nmの間の厚みを有する請求項1にかかる選択的エピタキシャル成長方法。
- 上記多結晶SiGeのトップ層(5)が、0%から0.5%の間のGe濃度を有する請求項1にかかる選択的エピタキシャル成長方法。
- 上記ストップ層が、シリコン酸化物からなる請求項2にかかる選択的エピタキシャル成長方法。
- 上記シリコン酸化物のストップ層が、0nmから30nmの間の厚みを有する請求項13の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05447290A EP1801864B1 (en) | 2005-12-23 | 2005-12-23 | Method for selective epitaxial growth of source/drain areas |
Publications (1)
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JP2007227892A true JP2007227892A (ja) | 2007-09-06 |
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JP2006347125A Pending JP2007227892A (ja) | 2005-12-23 | 2006-12-25 | ソース/ドレイン領域の選択的エピタキシャル成長方法 |
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Country | Link |
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US (1) | US7799664B2 (ja) |
EP (1) | EP1801864B1 (ja) |
JP (1) | JP2007227892A (ja) |
AT (1) | ATE449418T1 (ja) |
DE (1) | DE602005017806D1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US8877596B2 (en) * | 2010-06-24 | 2014-11-04 | International Business Machines Corporation | Semiconductor devices with asymmetric halo implantation and method of manufacture |
CN103871902A (zh) | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | 半导体处理工艺及半导体器件的制备方法 |
CN105869991B (zh) | 2015-01-23 | 2018-05-11 | 上海华力微电子有限公司 | 用于改善SiGe厚度的均匀性的方法和系统 |
CN105990172B (zh) | 2015-01-30 | 2018-07-31 | 上海华力微电子有限公司 | 嵌入式SiGe外延测试块的设计 |
CN105990342B (zh) | 2015-02-13 | 2019-07-19 | 上海华力微电子有限公司 | 具有用于嵌入锗材料的成形腔的半导体器件及其制造工艺 |
CN104851884A (zh) | 2015-04-14 | 2015-08-19 | 上海华力微电子有限公司 | 用于锗硅填充材料的成形腔 |
CN104821336B (zh) | 2015-04-20 | 2017-12-12 | 上海华力微电子有限公司 | 用于使用保形填充层改善器件表面均匀性的方法和系统 |
CN105097554B (zh) | 2015-08-24 | 2018-12-07 | 上海华力微电子有限公司 | 用于减少高浓度外延工艺中的位错缺陷的方法和系统 |
Citations (9)
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JPS62120028A (ja) * | 1985-11-20 | 1987-06-01 | Toshiba Corp | 半導体基板のエツチング方法 |
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KR20030090411A (ko) * | 2002-05-23 | 2003-11-28 | 삼성전자주식회사 | 선택적 성장을 이용한 씨모스 게이트 및 그 제조방법 |
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US7288802B2 (en) * | 2005-07-27 | 2007-10-30 | International Business Machines Corporation | Virtual body-contacted trigate |
-
2005
- 2005-12-23 DE DE602005017806T patent/DE602005017806D1/de active Active
- 2005-12-23 EP EP05447290A patent/EP1801864B1/en active Active
- 2005-12-23 AT AT05447290T patent/ATE449418T1/de not_active IP Right Cessation
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2006
- 2006-12-22 US US11/645,149 patent/US7799664B2/en active Active
- 2006-12-25 JP JP2006347125A patent/JP2007227892A/ja active Pending
Patent Citations (9)
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JPS5242375A (en) * | 1975-09-30 | 1977-04-01 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
JPS62120028A (ja) * | 1985-11-20 | 1987-06-01 | Toshiba Corp | 半導体基板のエツチング方法 |
JPH04370929A (ja) * | 1991-06-20 | 1992-12-24 | Sharp Corp | ドライエッチング方法 |
JPH0864579A (ja) * | 1994-08-23 | 1996-03-08 | Toshiba Corp | 半導体装置の製造方法 |
JP2000299462A (ja) * | 1999-04-15 | 2000-10-24 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003109969A (ja) * | 2001-09-28 | 2003-04-11 | Toshiba Corp | 半導体装置及びその製造方法 |
WO2005017964A2 (en) * | 2003-08-04 | 2005-02-24 | International Business Machines Corporation | Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions |
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JP2005197474A (ja) * | 2004-01-07 | 2005-07-21 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
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Publication number | Publication date |
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EP1801864B1 (en) | 2009-11-18 |
US7799664B2 (en) | 2010-09-21 |
ATE449418T1 (de) | 2009-12-15 |
US20070148860A1 (en) | 2007-06-28 |
EP1801864A1 (en) | 2007-06-27 |
DE602005017806D1 (de) | 2009-12-31 |
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