US20030211730A1 - Method for forming contact hole in semiconductor device - Google Patents
Method for forming contact hole in semiconductor device Download PDFInfo
- Publication number
- US20030211730A1 US20030211730A1 US10/330,913 US33091302A US2003211730A1 US 20030211730 A1 US20030211730 A1 US 20030211730A1 US 33091302 A US33091302 A US 33091302A US 2003211730 A1 US2003211730 A1 US 2003211730A1
- Authority
- US
- United States
- Prior art keywords
- silicon nitride
- layer
- oxide layer
- nitride layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Definitions
- the present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole which can prevent an isolation region from being damaged because there is little overlap margin for a contact hole in the active region, when a contact hole is formed over both an active region and an isolation region, i.e., when a borderless contact hole is formed.
- a contact hole According to the design of the structure of a logic device, it is necessary to form a contact hole on a gate or active region only. However, as the dimensions of a logic device are reduced, an overlap margin for a contact hole gradually decreases in the active region. As a result, due to a misalignment phenomena caused from a lithography process, a contact hole, which is meant to be formed only in an active region, may be sometimes be partially formed in an isolation region beyond the border of the active region. Such a contact hole is called as “borderless contact hole.”
- Polysilicon or silicide employed for forming a gate or active region has a characteristic of being scarcely etched by such plasma. In such a case, no damage is caused while a contact hole is being etched.
- a silicon oxide-based material (SiO 2- ⁇ ) employed for forming an isolation region has a characteristic of being easily etched by such plasma. Therefore, a problem arises in that an isolation region is deeply and sharply hollowed out in the process of forming a borderless hole.
- FIG. 1 is a drawing for illustrating the problematic situation when a contact hole is formed without using an etch-stop layer.
- 1 designates a silicon substrate
- 2 designates a shallow trench isolation (STI)
- 3 designates a well
- 4 designates a gate oxide layer
- 5 designates a gate (polysilicon)
- 6 designates a silicide layer
- 7 designates a spacer
- 8 designates a source
- 9 designates a drain
- 10 designates an interlayer insulation layer
- 11 designates a contact hole.
- the overlap margin for a contact hole decreases in the active region. If such an overlap margin for a contact hole is insufficient in an active region, the contact hole, which is meant to be formed only in the active region, is formed into an isolation region, beyond the border of the active region. As a result, a problem is caused in that the isolation region is deeply and sharply hollowed out, as shown in the drawing. If the isolation region is damaged in the process of forming a contact hole like this, leakage current or deterioration of the properties is caused in a resulting semiconductor device, thereby causing problems in operation of the device.
- a contact hole is formed using an etch-stop layer in a conventional semiconductor device manufacturing process, which will now be sequentially described with reference to FIG. 2.
- a predetermined thickness of a pad oxide layer (SiO 2 ) 22 is deposited on a silicon substrate 21 , and then a predetermined thickness of a silicon nitride layer (Si 3 N 4 ) 23 is deposited on the pad oxide layer 22 .
- the deposited silicon nitride layer 23 is used as a polish-stop layer when an oxidation material formed in a subsequent step for filling a trench is planarized using chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- the pad oxide layer 22 serves as a buffer layer for alleviating the mechanical stress influencing on the silicon substrate 21 ; stress which are induced by the silicon nitride layer 23 having been deposited on the pad oxide layer 22 .
- the thickness of the pad oxide layer 22 and the thickness of the silicon nitride layer 23 may be varied depending on the type of process employed, wherein the pad oxide layer 22 is applied to a thickness of about 70 ⁇ to 200 ⁇ and the silicon nitride layer 23 is applied to a thickness of about 500 ⁇ to 1500 ⁇ .
- a pattern of STI shallow trench isolation
- the silicon nitride layer 23 and the pad oxide layer 22 are completely etched by dry etching using activated plasma.
- Activated gases of plasma may be varied depending on the type of employed process. In general, however, a gas formed by mixing C x F y , H o H p F q , Ar, etc., in a predetermined ratio is mainly used for generating plasma. If the dry etching is continuously performed using activated plasma, a trench 25 is formed in the silicon substrate 21 . When forming the trench 25 in the silicon substrate 21 , plasma is generated mainly using a gas formed by properly mixing Cl 2 , HBr, N 2 , Ar, etc. After the silicon substrate 21 is etched to a desired depth, the remaining photoresist is completely removed.
- the trench 25 formed in the step shown in FIG. 2 c is filled with an oxide layer (SiO 2 ) 26 deposited using a plasma enhanced chemical vapor deposition (PECVD) process.
- PECVD plasma enhanced chemical vapor deposition
- one or more stepped portions may be formed in the top surface of the deposited oxide layer, which reflects the surface topology of a layer laid under the oxide layer.
- the top surface of the oxide layer 26 deposited in the step of FIG. 2 a is planarized and the oxide layer 26 deposited on the silicon nitride layer 23 ′ is removed, using CMP process, as shown in FIG. 2 b .
- the silicon nitride layer 23 ′ serves as a polish-stop layer to prevent the silicon substrate 21 from being polished.
- the silicon nitride layer 23 ′ is partially polished and thus its thickness is reduced.
- the remaining silicon nitride 23 ′ is removed using a phosphoric acid aqueous solution (H 3 PO 4 ). If the concentration and temperature of the phosphoric acid aqueous solution of are properly controlled, the etch selectivity ratio of a typical SiO 2 layer to the silicon nitride 23 ′ can be made to exceed about 1:50. Therefore, using the phosphoric acid aqueous solution, it is possible to completely remove the remaining silicon nitride film 23 ′ without damaging the oxide layer 26 filled in the trench 25 .
- a phosphoric acid aqueous solution H 3 PO 4
- a well 27 , a gate 28 , a spacer 29 , a source/drain 30 , and a silicide layer 31 are formed in accordance with the method of manufacturing a typical logic device.
- a silicon nitride (Si 3 N 4 ) layer 32 is thinly deposited on the entire surface to a thickness of about 200 ⁇ to 400 ⁇ .
- the deposited silicon nitride layer 32 serves as an etch-stop layer in a subsequent step for forming a contact hole.
- the top surface of the interlayer oxide film 33 is planarized using chemical mechanical polishing process.
- the interlayer oxide film 33 has a thickness of about 7,000 ⁇ to 9,000 ⁇ after the planarization is completed. In most cases, even if the thickness of the interlayer oxide film 33 is controlled to be constant and its planarization is completed, some variations in thickness exist in the interlayer oxide film, due to incompleteness of deposition and subsequent polishing steps.
- a photoresist layer 34 is coated on the interlayer oxide film 33 , exposed and developed to pattern a form of contact hole.
- the interlayer oxide film 33 is etched using plasma generated by activating a ‘C x F y +O 2 ’ gas as a main component, so that a contact hole is formed within the interlayer oxide film 33 .
- the etching proceeds in the following manner.
- the etching is performed using plasma generated by activating a gas having a relatively high ratio of C TO F, for example, C 4 F 8 or C 5 F 8 gas, with a minimum amount of O 2 being added. If the etching proceeds in this manner, the interlayer oxide film 33 is relatively well etched but an etch-stop phenomenon is generated in the silicon nitride layer 32 .
- the silicon nitride layer deposited in the aforementioned process is thin, it is not necessary to perform excessive over-etching in the silicon nitride layer (for example, for 30% over-etch, it is necessary to perform over-etch of 2,100 to 2,700 ⁇ if no etch-stop layer exists, whereas it is sufficient to perform over-etching of 60 to 120 ⁇ if an etch-stop layer is exist). Accordingly, even if a part of a contact hole, which is meant to be formed within an active region, is partially formed in the isolation region due to misalignment resulting from a lithography process, the problem of the isolation region being deeply and sharply hollowed out will not arise.
- a deposited silicon layer induces a strong compressive stress of about 10 9 dynes/cm 2 .
- Such strong stress induced by a silicon nitride layer deposited on an active region may deform the crystal structure of the active region, thereby resulting in deterioration of characteristics of a resulting semiconductor device.
- silicide a compound of silicon and a metallic component, i.e., Ti or Co
- the high temperature environment in the range of about 700 to 1,000° C. required for deposition of a silicon nitride layer may cause deterioration of the characteristics of previously formed silicide.
- a silicon nitride layer is deposited on both of an active region and an isolation region.
- the silicon nitride layer deposited on the isolation region is helpful in that it serves as an etch-stop layer. If no etch-stop layer exists, however, the active region will be lost when forming a contact hole, thereby causing junction leakage in a resulting semiconductor device.
- an object of the present invention is to provide a method for forming a contact hole in a semiconductor device, which can prevent an isolation region from being damaged because there is little overlap margin for the contact hole in the active region, when a contact hole is formed in both an active region and an isolation region, i.e., when a borderless contact hole is formed.
- PECVD plasma enhanced chemical vapor deposition
- FIG. 1 is a cross-sectional view for illustrating a problem arising in the prior art when forming a contact hole without an etch-stop layer;
- FIGS. 2 a to 2 f are cross-sectional views for illustrating a problem of a method for forming a contact hole of the prior art using an etch-stop layer.
- FIGS. 3 a to 3 i are cross-sectional views for illustrating a method for forming a contact hole in a semiconductor device in accordance with the present invention.
- FIGS. 3 a to 3 i are cross-sectional views for illustrating a method for forming a contact hole in a semiconductor device in accordance with the present invention.
- a predetermined thickness of a pad oxide (SiO 2 ) layer 102 is deposited on a silicon substrate 100 , and then a predetermined thickness of a silicon nitride (Si 3 N 4 ) 104 is deposited on the pad oxide layer 102 .
- the deposited silicon nitride layer 104 is used as a polish-stop layer when an oxidation material deposited in a subsequent step for filling in a trench is planarized using chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- a photoresist layer is coated on the silicon nitride layer 104 a , and the form of a shallow trench isolation (STI) is patterned by exposing and developing the photoresist.
- STI shallow trench isolation
- the silicon nitride layer 104 a and the pad oxide layer 102 a are completely etched by dry etching using activated plasma.
- the activated gas of the plasma may be varied depending on the type of process. In general, however, a gas formed by mixing C x F y , H o H p F q , Ar, etc., in a predetermined ratio is mainly used for the plasma. If the dry etch is continuously performed using the activated plasma, a trench 108 is formed in the silicon substrate 100 a . When forming the trench 108 in the silicon substrate 100 a , a gas formed by properly mixing Cl 2 , HBr, N 2 , Ar, etc., is mainly used. After the silicon substrate 100 a is etched to a desired depth, the remaining photoresist is completely removed.
- one or more trenches 108 formed in the process shown in FIG. 3 c are filled with an oxide (SiO 2 ) layer 110 a deposited using a plasma enhanced chemical vapor deposition (PECVD).
- PECVD plasma enhanced chemical vapor deposition
- one or more stepped portions exist in the top of the deposited oxide layer, which reflect the surface topology of the layer below.
- the top of the oxide layer 110 a deposited in the process of FIG. 3 a is planarized and, concurrently with this, the oxide layer 110 a deposited on the silicon nitride layer 104 a is removed, using CMP process.
- the silicon nitride layer 104 a serves as a polish-stop layer to prevent the silicon substrate 100 a under the silicon nitride layer 104 a from being polished.
- a part of the silicon nitride layer 104 a is polished, so that the thickness thereof is reduced.
- plasma etching proceeds with a plasma produced by activating a ‘C x F y +O 2 ’ gas as a main component, so that a part of the oxide layer 110 b filled in the trenches 108 is recessed.
- a gas having a relatively high ratio of C TO F for example C 4 F 8 or C 5 F 8 gas is used while adjusting the added amount of O 2 .
- the oxide layer 110 b filled in the trenches is relatively rapidly etched but the remaining silicon nitride layer 104 a is very slowly etched. If the etching condition is controlled in this manner, the oxide layer 110 b filled in the trenches is sufficiently recessed but the pad oxide layer 102 a laid under the silicon nitride layer 104 a is not damaged.
- a nitride layer (Si 3 N 4 ) 112 is deposited on the entire surface to a thickness larger than the recessed depth of the oxide layer 110 b etched out in the step of FIG. 3 d , for example, to a thickness about 2,000 ⁇ to 3,000 ⁇ .
- CMP chemical mechanical polishing
- FIG. 3 e is a cross-sectional view showing a state after the portions at which the gate and the spacer are to be formed have been patterned.
- the silicon nitride layer 104 c remaining in the other areas after the patterning is used as an etch-stop layer for preventing the isolation region from being damaged when a borderless contact hole is formed in a subsequent contact-etching step. Furthermore, the silicon nitride layer is used as a barrier for preventing the silicon from being damaged.
- the silicon nitride layer 104 c and the pad oxide layer 102 b are etched by means of dry etching using plasma formed by activating a ‘C x F y +O 2 ’ gas.
- a gate 118 and a spacer 120 are formed, as shown in FIG. 3 f.
- an ion implantation step 122 is performed for forming a source/drain 124 , as shown in FIG. 3 g .
- the silicon nitride layer 104 c and the pad oxide layer 102 b , on which the source/drain 124 is to be formed serve as a barrier against the ion implantation, thereby preventing the surface of the silicon substrate 100 a from being damaged.
- an interlayer oxide film 126 is deposited and its top surface is planarized using chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- a photoresist layer 128 is coated on the interlayer oxide film 126 , and the contact hole 130 is patterned by exposing and developing the photoresist layer, as shown in FIG. 3 h.
- a contact hole 132 is formed in the interlayer oxide 126 a by etching the interlayer oxide film 126 using plasma generated by activating a ‘C x F y +O 2 ’ gas as a main component.
- the etching proceeds using plasma generated by activating a gas having a relatively high ratio of C to F, for example, C 4 F 8 or C 5 F 8 gas, with a minimum amount of O 2 being added.
- the interlayer oxide film 126 a may be relatively well etched but an etch-stop phenomenon may be generated in the silicon nitride layer 104 d .
- some variations in thickness arise in the interlayer oxide film 126 a depending on the portions on a wafer. Therefore, it is necessary to perform sufficient over-etching so that those variations are removed. Even if such over-etching is performed, however, a problem, which renders the isolation region to be deeply and sharply hollowed out, will not arise because a predetermined thickness of the silicon nitride layer 104 d exists on the isolation region and serves as an etch-stop layer.
- the method of the present invention it is possible to secure a margin for etching a borderless contact hole and to prevent the surface of the silicon substrate from being damaged at the time of ion implantation. Furthermore, it is also possible to prevent the isolation region from being recessed, so that junction leakage current will not be generated in a resulting semiconductor device.
- a nitride layer is formed beforehand on an active region, it is also possible to solve the problem that a characteristic of the device deteriorates due to the deformation of the lattice structure of the silicon surface of the active region caused from ion implantation.
- nitride layer formed beforehand serves as an etch-stop layer in the step for forming a borderless contact, it is possible to secure a process margin.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole which can prevent an isolation region from being damaged because there is little overlap margin for a contact hole in the active region, when a contact hole is formed over both an active region and an isolation region, i.e., when a borderless contact hole is formed.
- 2. Description of the Prior Art
- According to the design of the structure of a logic device, it is necessary to form a contact hole on a gate or active region only. However, as the dimensions of a logic device are reduced, an overlap margin for a contact hole gradually decreases in the active region. As a result, due to a misalignment phenomena caused from a lithography process, a contact hole, which is meant to be formed only in an active region, may be sometimes be partially formed in an isolation region beyond the border of the active region. Such a contact hole is called as “borderless contact hole.”
- In the conventional process of manufacturing semiconductor devices, it is common to form a contact hole by performing dry etching using plasma formed by activating a ‘CxFy+O2’ gas, wherein the ‘CxFy’ means a gas selected from a group consisting of CF4, C2F6, C4F8, C5F8, etc., or a combination thereof. If desired, CHF3, Ar or the like may be added to that gas or the combination.
- Polysilicon or silicide employed for forming a gate or active region has a characteristic of being scarcely etched by such plasma. In such a case, no damage is caused while a contact hole is being etched. However, a silicon oxide-based material (SiO2-δ) employed for forming an isolation region has a characteristic of being easily etched by such plasma. Therefore, a problem arises in that an isolation region is deeply and sharply hollowed out in the process of forming a borderless hole.
- FIG. 1 is a drawing for illustrating the problematic situation when a contact hole is formed without using an etch-stop layer. In the drawing,1 designates a silicon substrate, 2 designates a shallow trench isolation (STI), 3 designates a well, 4 designates a gate oxide layer, 5 designates a gate (polysilicon), 6 designates a silicide layer, 7 designates a spacer, 8 designates a source, 9 designates a drain, 10 designates an interlayer insulation layer, and 11 designates a contact hole.
- As the dimensions of logic devices are reduced, the overlap margin for a contact hole decreases in the active region. If such an overlap margin for a contact hole is insufficient in an active region, the contact hole, which is meant to be formed only in the active region, is formed into an isolation region, beyond the border of the active region. As a result, a problem is caused in that the isolation region is deeply and sharply hollowed out, as shown in the drawing. If the isolation region is damaged in the process of forming a contact hole like this, leakage current or deterioration of the properties is caused in a resulting semiconductor device, thereby causing problems in operation of the device.
- Therefore, in order to solve this problem, a contact hole is formed using an etch-stop layer in a conventional semiconductor device manufacturing process, which will now be sequentially described with reference to FIG. 2.
- Referring to FIG. 2a, a predetermined thickness of a pad oxide layer (SiO2) 22 is deposited on a
silicon substrate 21, and then a predetermined thickness of a silicon nitride layer (Si3N4) 23 is deposited on thepad oxide layer 22. Herein, the depositedsilicon nitride layer 23 is used as a polish-stop layer when an oxidation material formed in a subsequent step for filling a trench is planarized using chemical mechanical polishing (CMP) process. - The
pad oxide layer 22 serves as a buffer layer for alleviating the mechanical stress influencing on thesilicon substrate 21; stress which are induced by thesilicon nitride layer 23 having been deposited on thepad oxide layer 22. The thickness of thepad oxide layer 22 and the thickness of thesilicon nitride layer 23 may be varied depending on the type of process employed, wherein thepad oxide layer 22 is applied to a thickness of about 70 Å to 200 Å and thesilicon nitride layer 23 is applied to a thickness of about 500 Å to 1500 Å. - Next, after a photoresist layer24 is coated on the
silicon nitride layer 23, a pattern of STI (shallow trench isolation) is formed by exposing and developing the photoresist layer 24. - Then, the
silicon nitride layer 23 and thepad oxide layer 22 are completely etched by dry etching using activated plasma. Activated gases of plasma may be varied depending on the type of employed process. In general, however, a gas formed by mixing CxFy, HoHpFq, Ar, etc., in a predetermined ratio is mainly used for generating plasma. If the dry etching is continuously performed using activated plasma, atrench 25 is formed in thesilicon substrate 21. When forming thetrench 25 in thesilicon substrate 21, plasma is generated mainly using a gas formed by properly mixing Cl2, HBr, N2, Ar, etc. After thesilicon substrate 21 is etched to a desired depth, the remaining photoresist is completely removed. - Thereafter, the
trench 25 formed in the step shown in FIG. 2c is filled with an oxide layer (SiO2) 26 deposited using a plasma enhanced chemical vapor deposition (PECVD) process. Here, one or more stepped portions may be formed in the top surface of the deposited oxide layer, which reflects the surface topology of a layer laid under the oxide layer. - The top surface of the
oxide layer 26 deposited in the step of FIG. 2a is planarized and theoxide layer 26 deposited on thesilicon nitride layer 23′ is removed, using CMP process, as shown in FIG. 2b. At this time, thesilicon nitride layer 23′ serves as a polish-stop layer to prevent thesilicon substrate 21 from being polished. During this step, thesilicon nitride layer 23′ is partially polished and thus its thickness is reduced. - Referring to FIG. 2c, the
remaining silicon nitride 23′ is removed using a phosphoric acid aqueous solution (H3PO4). If the concentration and temperature of the phosphoric acid aqueous solution of are properly controlled, the etch selectivity ratio of a typical SiO2 layer to thesilicon nitride 23′ can be made to exceed about 1:50. Therefore, using the phosphoric acid aqueous solution, it is possible to completely remove the remainingsilicon nitride film 23′ without damaging theoxide layer 26 filled in thetrench 25. - Referring to FIG. 2d, a well 27, a
gate 28, aspacer 29, a source/drain 30, and asilicide layer 31 are formed in accordance with the method of manufacturing a typical logic device. - Next, a silicon nitride (Si3N4)
layer 32 is thinly deposited on the entire surface to a thickness of about 200 Å to 400 Å. The depositedsilicon nitride layer 32 serves as an etch-stop layer in a subsequent step for forming a contact hole. - Referring to FIG. 2e, after an
interlayer oxide film 33 is deposited, the top surface of theinterlayer oxide film 33 is planarized using chemical mechanical polishing process. In general, theinterlayer oxide film 33 has a thickness of about 7,000 Å to 9,000 Å after the planarization is completed. In most cases, even if the thickness of theinterlayer oxide film 33 is controlled to be constant and its planarization is completed, some variations in thickness exist in the interlayer oxide film, due to incompleteness of deposition and subsequent polishing steps. - Next, a photoresist layer34 is coated on the
interlayer oxide film 33, exposed and developed to pattern a form of contact hole. - Referring to FIG. 2f, the
interlayer oxide film 33 is etched using plasma generated by activating a ‘CxFy+O2’ gas as a main component, so that a contact hole is formed within theinterlayer oxide film 33. The etching proceeds in the following manner. The etching is performed using plasma generated by activating a gas having a relatively high ratio of C TO F, for example, C4F8 or C5F8 gas, with a minimum amount of O2 being added. If the etching proceeds in this manner, theinterlayer oxide film 33 is relatively well etched but an etch-stop phenomenon is generated in thesilicon nitride layer 32. - Therefore, even if variations in thickness had been caused in the
interlayer oxide film 33 according to the various parts of the wafer in the abovementioned process, those variations are completely removed if the etching reaches thesilicon nitride layer 32. If the etching of theinterlayer oxide film 33 is completed, the plasma activation condition is changed so that thesilicon nitride layer 32 can be etched well. That is, the etching proceeds using plasma generated by activating a gas having a reduced ratio of C to F with an increased amount of O2. - Herein, because the silicon nitride layer deposited in the aforementioned process is thin, it is not necessary to perform excessive over-etching in the silicon nitride layer (for example, for 30% over-etch, it is necessary to perform over-etch of 2,100 to 2,700 Å if no etch-stop layer exists, whereas it is sufficient to perform over-etching of 60 to 120 Å if an etch-stop layer is exist). Accordingly, even if a part of a contact hole, which is meant to be formed within an active region, is partially formed in the isolation region due to misalignment resulting from a lithography process, the problem of the isolation region being deeply and sharply hollowed out will not arise.
- When a contact hole is formed according to the aforementioned process, an isolation region is not deeply and sharply hollowed out, as shown in FIG. 2k, even if a part of the contact hole is formed in the isolation region. However, the aforementioned process includes some problems, as follows.
- (1) In general, a deposited silicon layer induces a strong compressive stress of about 109 dynes/cm2. Such strong stress induced by a silicon nitride layer deposited on an active region may deform the crystal structure of the active region, thereby resulting in deterioration of characteristics of a resulting semiconductor device.
- (2) In order to properly deposit a silicon nitride layer, an environment of high temperature in the range of about 700 to 1,000° C. is required. However, such a high temperature environment may change the operating characteristics of a transistor which has been optimized prior to depositing the silicon nitride layer.
- (3) According to an existing method for manufacturing a logic device, silicide (a compound of silicon and a metallic component, i.e., Ti or Co) is formed prior to deposition of a silicon nitride layer. However, the high temperature environment in the range of about 700 to 1,000° C. required for deposition of a silicon nitride layer may cause deterioration of the characteristics of previously formed silicide.
- (4) In the aforementioned process, a silicon nitride layer is deposited on both of an active region and an isolation region. The silicon nitride layer deposited on the isolation region is helpful in that it serves as an etch-stop layer. If no etch-stop layer exists, however, the active region will be lost when forming a contact hole, thereby causing junction leakage in a resulting semiconductor device.
- Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming a contact hole in a semiconductor device, which can prevent an isolation region from being damaged because there is little overlap margin for the contact hole in the active region, when a contact hole is formed in both an active region and an isolation region, i.e., when a borderless contact hole is formed.
- It is also an object of the present invention to provide a method for forming a contact hole in a semiconductor device, wherein a nitride layer is formed beforehand on an active region to solve the problem that characteristics of the device are caused to deteriorate due to the deformation of the lattice structure of the silicon surface in the active region, the deformation resulting from ion implantation.
- It is another object of the present invention to provide a method for forming a contact hole in a semiconductor device, wherein a nitride layer is formed beforehand on an active region, thereby simplifying the entire process.
- It is still another object of the present invention to provide a method for forming a contact hole in a semiconductor device, wherein a nitride layer formed beforehand serves as an etch-stop layer in the step of etching a borderless contact hole, thereby being capable of securing a process margin.
- In order to accomplish the above objects, according to the present invention, there is provided a method for forming a contact hole in a semiconductor device comprising the steps of:
- forming a pad oxide layer and a first silicon nitride layer to a predetermined thickness on a silicon substrate;
- forming a trench for shallow trench isolation by dry etching the first silicon nitride layer, the pad oxide layer and the silicon substrate;
- depositing an oxide layer on the entire structure formed through the above steps, using a plasma enhanced chemical vapor deposition (PECVD) process, so that the trench is sufficiently filled with the oxide layer;
- planarizing the oxide layer by means of chemical mechanical polishing process, so that the top of the first silicon nitride layer is exposed;
- recessing a part of the oxide layer filled in the trench by means of first plasma etching;
- forming a second silicon nitride over the entire structure formed in the above steps to a thickness thicker than the recessed depth of the oxide layer;
- planarizing the second silicon nitride layer using CMP process, so that the top of the first silicon nitride is exposed and partially planarized;
- selectively removing the first silicon nitride layer and the pad oxide layer by means of a second plasma etching in the portions where a gate and a space are to be formed;
- forming a well, a gate, a spacer and a source/drain, and then forming a silicide layer;
- depositing an interlayer oxide film on the above structure, and then planarizing the top of the interlayer oxide film using CMP process;
- coating a photoresist layer on the interlayer oxide film and then forming a shape of a contact hole by exposing and developing the photoresist layer; and
- forming a contact hole in the interlayer oxide layer by removing a part of the interlayer oxide layer using a third plasma etching.
- The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
- FIG. 1 is a cross-sectional view for illustrating a problem arising in the prior art when forming a contact hole without an etch-stop layer;
- FIGS. 2a to 2 f are cross-sectional views for illustrating a problem of a method for forming a contact hole of the prior art using an etch-stop layer; and
- FIGS. 3a to 3 i are cross-sectional views for illustrating a method for forming a contact hole in a semiconductor device in accordance with the present invention.
- Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description for the same or similar components will be omitted.
- FIGS. 3a to 3 i are cross-sectional views for illustrating a method for forming a contact hole in a semiconductor device in accordance with the present invention.
- Referring to FIG. 3a, a predetermined thickness of a pad oxide (SiO2) layer 102 is deposited on a silicon substrate 100, and then a predetermined thickness of a silicon nitride (Si3N4) 104 is deposited on the pad oxide layer 102. Herein, the deposited silicon nitride layer 104 is used as a polish-stop layer when an oxidation material deposited in a subsequent step for filling in a trench is planarized using chemical mechanical polishing (CMP) process.
- Next, a photoresist layer is coated on the
silicon nitride layer 104 a, and the form of a shallow trench isolation (STI) is patterned by exposing and developing the photoresist. - Thereafter, the
silicon nitride layer 104 a and thepad oxide layer 102 a are completely etched by dry etching using activated plasma. Herein, the activated gas of the plasma may be varied depending on the type of process. In general, however, a gas formed by mixing CxFy, HoHpFq, Ar, etc., in a predetermined ratio is mainly used for the plasma. If the dry etch is continuously performed using the activated plasma, atrench 108 is formed in thesilicon substrate 100 a. When forming thetrench 108 in thesilicon substrate 100 a, a gas formed by properly mixing Cl2, HBr, N2, Ar, etc., is mainly used. After thesilicon substrate 100 a is etched to a desired depth, the remaining photoresist is completely removed. - Thereafter, one or
more trenches 108 formed in the process shown in FIG. 3c are filled with an oxide (SiO2)layer 110 a deposited using a plasma enhanced chemical vapor deposition (PECVD). Here, one or more stepped portions exist in the top of the deposited oxide layer, which reflect the surface topology of the layer below. - Next, referring to FIG. 3b, the top of the
oxide layer 110 a deposited in the process of FIG. 3a is planarized and, concurrently with this, theoxide layer 110 a deposited on thesilicon nitride layer 104 a is removed, using CMP process. In this case, thesilicon nitride layer 104 a serves as a polish-stop layer to prevent thesilicon substrate 100 a under thesilicon nitride layer 104 a from being polished. During this process, a part of thesilicon nitride layer 104 a is polished, so that the thickness thereof is reduced. - Referring to FIG. 3c, plasma etching proceeds with a plasma produced by activating a ‘CxFy+O2’ gas as a main component, so that a part of the
oxide layer 110 b filled in thetrenches 108 is recessed. At this time, if a gas having a relatively high ratio of C TO F, for example C4F8 or C5F8 gas is used while adjusting the added amount of O2, theoxide layer 110 b filled in the trenches is relatively rapidly etched but the remainingsilicon nitride layer 104 a is very slowly etched. If the etching condition is controlled in this manner, theoxide layer 110 b filled in the trenches is sufficiently recessed but thepad oxide layer 102 a laid under thesilicon nitride layer 104 a is not damaged. - Next, referring to FIG. 3d, a nitride layer (Si3N4) 112 is deposited on the entire surface to a thickness larger than the recessed depth of the
oxide layer 110 b etched out in the step of FIG. 3d, for example, to a thickness about 2,000 Å to 3,000 Å. - Then, chemical mechanical polishing (CMP) process is performed, so that a predetermined thickness of the
nitride layer 112 deposited in the step of FIG. 3d is removed and the top of the nitride layer 104 b on the active layer is planarized. Herein, the thickness of the silicon nitride layer 104 b is controlled to be about 300 Å to 500 Å. Then, the portions at which a gate and a spacer are to be formed are patterned using a negative photoresist film. - FIG. 3e is a cross-sectional view showing a state after the portions at which the gate and the spacer are to be formed have been patterned. The
silicon nitride layer 104 c remaining in the other areas after the patterning is used as an etch-stop layer for preventing the isolation region from being damaged when a borderless contact hole is formed in a subsequent contact-etching step. Furthermore, the silicon nitride layer is used as a barrier for preventing the silicon from being damaged. Thesilicon nitride layer 104 c and thepad oxide layer 102 b are etched by means of dry etching using plasma formed by activating a ‘CxFy+O2’ gas. - Next, after a well116 has been formed in accordance with a method for forming a common logic device, a
gate 118 and aspacer 120 are formed, as shown in FIG. 3f. - Then, an
ion implantation step 122 is performed for forming a source/drain 124, as shown in FIG. 3g. At this time, thesilicon nitride layer 104 c and thepad oxide layer 102 b, on which the source/drain 124 is to be formed, serve as a barrier against the ion implantation, thereby preventing the surface of thesilicon substrate 100 a from being damaged. - Next, like the existing method described above, an
interlayer oxide film 126 is deposited and its top surface is planarized using chemical mechanical polishing (CMP) process. - Next, like the existing method described above, a
photoresist layer 128 is coated on theinterlayer oxide film 126, and thecontact hole 130 is patterned by exposing and developing the photoresist layer, as shown in FIG. 3h. - Next, referring to FIG. 3i, a
contact hole 132 is formed in theinterlayer oxide 126 a by etching theinterlayer oxide film 126 using plasma generated by activating a ‘CxFy+O2’ gas as a main component. When etching theinterlayer oxide film 126 a, like the existing method described above, the etching proceeds using plasma generated by activating a gas having a relatively high ratio of C to F, for example, C4F8 or C5F8 gas, with a minimum amount of O2 being added. - If the etching proceeds in this manner, the
interlayer oxide film 126 a may be relatively well etched but an etch-stop phenomenon may be generated in thesilicon nitride layer 104 d. Like the existing method, some variations in thickness arise in theinterlayer oxide film 126 a depending on the portions on a wafer. Therefore, it is necessary to perform sufficient over-etching so that those variations are removed. Even if such over-etching is performed, however, a problem, which renders the isolation region to be deeply and sharply hollowed out, will not arise because a predetermined thickness of thesilicon nitride layer 104 d exists on the isolation region and serves as an etch-stop layer. - According to the method of the present invention, it is possible to secure a margin for etching a borderless contact hole and to prevent the surface of the silicon substrate from being damaged at the time of ion implantation. Furthermore, it is also possible to prevent the isolation region from being recessed, so that junction leakage current will not be generated in a resulting semiconductor device.
- As described above, according to the present invention, it is possible to prevent an isolation region from being damaged because there is little overlap margin for the contact hole in the active region, when a contact hole is formed in an isolation region beyond the border of an active region, i.e., when a borderless contact hole is formed.
- According to the present invention, because a nitride layer is formed beforehand on an active region, it is also possible to solve the problem that a characteristic of the device deteriorates due to the deformation of the lattice structure of the silicon surface of the active region caused from ion implantation.
- Furthermore, by forming a nitride layer beforehand on an active region, it is possible to simplify the entire process. In addition, because the nitride layer formed beforehand serves as an etch-stop layer in the step for forming a borderless contact, it is possible to secure a process margin.
- The preferred embodiment of the present invention has been described for illustrative purposes, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (7)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0025030A KR100451513B1 (en) | 2002-05-07 | 2002-05-07 | Method of manufacture contact hole in semiconduct device |
KR10-2002-0025030 | 2002-05-07 | ||
KR2002-25030 | 2002-05-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030211730A1 true US20030211730A1 (en) | 2003-11-13 |
US6653194B1 US6653194B1 (en) | 2003-11-25 |
Family
ID=29398472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/330,913 Expired - Lifetime US6653194B1 (en) | 2002-05-07 | 2002-12-27 | Method for forming contact hole in semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US6653194B1 (en) |
KR (1) | KR100451513B1 (en) |
CN (1) | CN1270354C (en) |
TW (1) | TWI255526B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070131964A1 (en) * | 2005-12-13 | 2007-06-14 | Sang Yong Lee | Semiconductor device and method for manufacturing the same |
US20070243671A1 (en) * | 2006-04-17 | 2007-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Butted source contact and well strap |
US20090001446A1 (en) * | 2007-06-27 | 2009-01-01 | Dongbu Hitek Co., Ltd. | Flash memory device and methods for fabricating the same |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100763680B1 (en) * | 2006-08-23 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Structure and method for manufacturing contact of image sensor device |
KR20110120695A (en) * | 2010-04-29 | 2011-11-04 | 삼성전자주식회사 | Semiconductor device |
DE102011004922B4 (en) * | 2011-03-01 | 2016-12-15 | Globalfoundries Dresden Module One Llc & Co. Kg | Method of fabricating transistors with metal gate stacks with increased integrity |
US20120292735A1 (en) | 2011-05-20 | 2012-11-22 | GLOBALFOUNDRIES Singapore Pte.Ltd. | Corner transistor suppression |
US8692353B2 (en) | 2011-09-02 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method |
US8877614B2 (en) | 2011-10-13 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer for semiconductor structure contact |
CN103165507A (en) * | 2011-12-09 | 2013-06-19 | 上海华虹Nec电子有限公司 | Method preventing electric leakage on shallow trough isolation edge |
US8629008B2 (en) * | 2012-01-11 | 2014-01-14 | International Business Machines Corporation | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices |
US8664050B2 (en) | 2012-03-20 | 2014-03-04 | International Business Machines Corporation | Structure and method to improve ETSOI MOSFETS with back gate |
CN103594417A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Production method of interconnection structure |
CN104143530B (en) * | 2013-05-09 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and preparation method thereof |
CN107093577A (en) * | 2017-04-17 | 2017-08-25 | 上海华虹宏力半导体制造有限公司 | The manufacture method of contact hole |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH098135A (en) * | 1995-06-26 | 1997-01-10 | Toshiba Corp | Manufacture of semiconductor device |
US6133105A (en) | 1999-04-27 | 2000-10-17 | United Microelectronics Corp. | Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure |
KR100325600B1 (en) * | 1999-05-11 | 2002-02-25 | 황인길 | a manufacturing method of contact holes of semiconductor devices |
US6204185B1 (en) * | 1999-05-24 | 2001-03-20 | United Microelectronics Corp. | Method for forming self-align stop layer for borderless contact process |
KR100293052B1 (en) * | 1999-06-08 | 2001-06-15 | 황인길 | Semiconductor device manufacturing method |
US6297126B1 (en) | 1999-07-12 | 2001-10-02 | Chartered Semiconductor Manufacturing Ltd. | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts |
KR20020010795A (en) * | 2000-07-31 | 2002-02-06 | 박종섭 | Manufacturing method for semiconductor device |
-
2002
- 2002-05-07 KR KR10-2002-0025030A patent/KR100451513B1/en active IP Right Grant
- 2002-12-27 TW TW091137747A patent/TWI255526B/en not_active IP Right Cessation
- 2002-12-27 US US10/330,913 patent/US6653194B1/en not_active Expired - Lifetime
-
2003
- 2003-01-03 CN CNB031001599A patent/CN1270354C/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070131964A1 (en) * | 2005-12-13 | 2007-06-14 | Sang Yong Lee | Semiconductor device and method for manufacturing the same |
US7704817B2 (en) * | 2005-12-13 | 2010-04-27 | Dongbu Hitek Co., Ltd. | Method for manufacturing semiconductor device |
US20070243671A1 (en) * | 2006-04-17 | 2007-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Butted source contact and well strap |
US7586147B2 (en) | 2006-04-17 | 2009-09-08 | Taiwan Semiconductor Manufacturing Co. Ltd. | Butted source contact and well strap |
US20090286395A1 (en) * | 2006-04-17 | 2009-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Butted Source Contact and Well Strap |
US7906389B2 (en) * | 2006-04-17 | 2011-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Butted source contact and well strap |
US20090001446A1 (en) * | 2007-06-27 | 2009-01-01 | Dongbu Hitek Co., Ltd. | Flash memory device and methods for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
KR20030086837A (en) | 2003-11-12 |
TWI255526B (en) | 2006-05-21 |
KR100451513B1 (en) | 2004-10-06 |
CN1457087A (en) | 2003-11-19 |
TW200306643A (en) | 2003-11-16 |
US6653194B1 (en) | 2003-11-25 |
CN1270354C (en) | 2006-08-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6331469B1 (en) | Trench isolation structure, semiconductor device having the same, and trench isolation method | |
KR100870616B1 (en) | Methods of Forming Trench Isolation Regions | |
US6121110A (en) | Trench isolation method for semiconductor device | |
KR100546378B1 (en) | Method of manufacturing transistor having recessed channel | |
US6653194B1 (en) | Method for forming contact hole in semiconductor device | |
JPH10303290A (en) | Component isolating method of semiconductor device | |
JPH10303291A (en) | Semiconductor device and its manufacture | |
US7468298B2 (en) | Method of manufacturing flash memory device | |
KR100475025B1 (en) | Forming method for field oxide of semiconductor device | |
KR100762865B1 (en) | method for manufacturing of flash memory device | |
KR100532839B1 (en) | Method for manufacturing shallow trench of semiconductor device | |
KR100403350B1 (en) | Method for forming borderless contact hole in a semiconductor device | |
KR100920000B1 (en) | Method for forming contact of semiconductor device | |
US7371665B2 (en) | Method for fabricating shallow trench isolation layer of semiconductor device | |
KR20030002870A (en) | Method for forming isolation in semiconductor device | |
KR20080000785A (en) | Method of manufacturing a nand type flash memory device | |
KR100493423B1 (en) | Method of manufacturing a semiconductor device | |
KR20030092525A (en) | Method of manufacture contact hole in semiconduct device | |
KR100223825B1 (en) | Method of forming an element isolation region in a semiconductor device | |
KR100575616B1 (en) | Method for forming borderless contact hole in a semiconductor device | |
KR20030045216A (en) | Method of manufacturing a trench in semiconductor device | |
KR100239425B1 (en) | Manufacturing process of transistor | |
KR20030002884A (en) | Method for forming isolation in semiconductor device | |
KR20060113269A (en) | Method for manufacturing semiconductor device using recess process | |
US20080001190A1 (en) | Semiconductor device with recess gate and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PARK, KUN JOO;REEL/FRAME:013622/0469 Effective date: 20021218 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR, INC.;REEL/FRAME:016216/0649 Effective date: 20041004 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUS Free format text: SECURITY INTEREST;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:016470/0530 Effective date: 20041223 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: MAGNACHIP SEMICONDUCTOR LTD.,KOREA, DEMOCRATIC PEO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION;REEL/FRAME:024563/0807 Effective date: 20100527 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: MAGNACHIP SEMICONDUCTOR LTD., KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY;ASSIGNOR:US BANK NATIONAL ASSOCIATION;REEL/FRAME:034469/0001 Effective date: 20100527 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: KEY FOUNDRY CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:053703/0227 Effective date: 20200828 |