JP4750034B2 - 半導体装置および書き込み方法 - Google Patents
半導体装置および書き込み方法 Download PDFInfo
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- JP4750034B2 JP4750034B2 JP2006527752A JP2006527752A JP4750034B2 JP 4750034 B2 JP4750034 B2 JP 4750034B2 JP 2006527752 A JP2006527752 A JP 2006527752A JP 2006527752 A JP2006527752 A JP 2006527752A JP 4750034 B2 JP4750034 B2 JP 4750034B2
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- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000000034 method Methods 0.000 title claims description 21
- 230000015654 memory Effects 0.000 claims description 93
- 238000012795 verification Methods 0.000 claims description 49
- 238000012546 transfer Methods 0.000 claims description 19
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 16
- 101000739577 Homo sapiens Selenocysteine-specific elongation factor Proteins 0.000 description 6
- 102100037498 Selenocysteine-specific elongation factor Human genes 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 4
- 102100040577 Dermatan-sulfate epimerase-like protein Human genes 0.000 description 2
- 241001649081 Dina Species 0.000 description 2
- 101100346656 Drosophila melanogaster strat gene Proteins 0.000 description 2
- 101000816741 Homo sapiens Dermatan-sulfate epimerase-like protein Proteins 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Description
また、特許文献1では、入力された書き込みデータを保持するバイナリデータレジスタを有する半導体記憶装置が提案されている。また、特許文献2では、外部からの書き込みデータをラッチするデータラッチ回路と、書き込み制御情報をラッチするセンスラッチ回路を有する半導体装置が提案されている。
本発明は、上記構成において、前記第1のラッチ回路は、前記第2のラッチ回路と同数の回路で構成され、かつ、前記書き込み回路よりも多い数の回路で構成される。
Claims (14)
- 各々が複数ビットを有する複数ワードの入力情報を多値メモリセルの各レベルに応じて変換させた複数ワードの書き込み情報をラッチする第1のラッチ回路と、
前記複数ワードの書き込み情報を同時に書き込めるメモリセル数に対応したグループごとに前記多値メモリセルに書き込む書き込み回路と、
前記複数ワードの入力情報を前記複数ワードの書き込み情報に変換して前記第1のラッチ回路に転送する第2のラッチ回路とを含み、
前記第1のラッチ回路は、前記第2のラッチ回路と同数の回路で構成され、かつ、前記書き込み回路よりも多い数の回路で構成される
半導体装置。 - 前記第1のラッチ回路は、前記グループごとに前記書き込み情報を前記書き込み回路に転送する請求項1記載の半導体装置。
- 前記半導体装置は更に、前記グループ単位にベリファイおよび書き込みを行う信号を生成する制御回路を含む請求項1または2記載の半導体装置。
- 前記半導体装置は更に、前記複数のグループ単位にベリファイおよび書き込みを繰り返す信号を生成する制御回路を含む請求項1から請求項3のいずれか一項に記載の半導体装置。
- 前記半導体装置は更に、所定のグループに対するベリファイがパスしたかを判定する回路を含み、
前記制御回路は、前記判定回路の判定結果に応じて、ベリファイがパスしたグループに対して以後のベリファイおよび書き込みをパスする信号を生成する請求項3または4記載の半導体装置。 - 前記半導体装置は更に、前記グループ内で選択されていないワードに対するベリファイをパスする信号を生成する回路を含む請求項1から請求項5のいずれか一項に記載の半導体装置。
- 前記半導体装置は更に、前記多値メモリセルの所定のレベルに対する書き込みが十分である場合、次のレベルの書き込み動作を行う制御回路を含む請求項1から請求項6のいずれか一項に記載の半導体装置。
- 前記半導体装置は、半導体記憶装置である請求項1から請求項7のいずれか一項に記載の半導体装置。
- 入力バッファにより、各々が複数ビットを有する複数の入力ワードの書き込み情報を受けて、複数ワードの書き込み入力情報を生成するステップと、
前記複数ワードの書き込み入力情報を入力ラッチ回路により受けて、多値メモリセルの各レベルに応じた複数ワードの書き込み情報に変換して転送して、前記入力ラッチ回路と同数の書き込みラッチ回路で該転送情報をラッチするステップと、
前記複数ワードの書き込み情報を同時に書き込めるメモリセル数に対応したグループごとに前記多値メモリセルに書き込むステップとを含み、前記同時に書き込めるメモリ数は前記入力ラッチ回路数および書き込みラッチ回路数よりも小さい、
書き込み方法。 - 前記書き込み方法は更に、前記グループ単位にベリファイおよび書き込みを繰り返すステップを含む請求項9記載の書き込み方法。
- 前記書き込み方法は更に、前記複数のグループ単位にベリファイおよび書き込みを繰り返すステップを含む請求項9記載の書き込み方法。
- 前記書き込み方法は更に、前記多値メモリセルの所定レベルに対するベリファイがパスしたかを判定する判定ステップと、
前記判定結果に応じて、ベリファイがパスしたグループに対して以後のベリファイおよび書き込みをパスするステップとを含む請求項9から請求項11のいずれか一項に記載の書き込み方法。 - 前記書き込み方法は更に、前記グループ内で選択されていないワードに対するベリファイをパスするステップを含む請求項9から請求項12のいずれか一項に記載の半導体装置。
- 前記書き込み方法は更に、前記多値メモリセルの所定レベルに対する書き込みが十分である場合、次のレベルの書き込み動作を行う信号を生成するステップを含む請求項9から請求項13のいずれか一項に記載の半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/010914 WO2006011222A1 (ja) | 2004-07-30 | 2004-07-30 | 半導体装置および書き込み方法 |
Publications (2)
Publication Number | Publication Date |
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JPWO2006011222A1 JPWO2006011222A1 (ja) | 2008-05-01 |
JP4750034B2 true JP4750034B2 (ja) | 2011-08-17 |
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JP2006527752A Expired - Fee Related JP4750034B2 (ja) | 2004-07-30 | 2004-07-30 | 半導体装置および書き込み方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7227778B2 (ja) |
JP (1) | JP4750034B2 (ja) |
KR (1) | KR101092012B1 (ja) |
CN (1) | CN100555460C (ja) |
DE (1) | DE112004002927B4 (ja) |
GB (1) | GB2431026B (ja) |
WO (1) | WO2006011222A1 (ja) |
Families Citing this family (11)
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GB2436272B (en) * | 2005-01-27 | 2011-01-19 | Spansion Llc | Semiconductor device, address assignment method, and verify method |
GB2468051B (en) * | 2005-01-27 | 2011-02-09 | Spansion Llc | Semiconductor device,address assignment method and verify method |
US7751242B2 (en) * | 2005-08-30 | 2010-07-06 | Micron Technology, Inc. | NAND memory device and programming methods |
US7609559B2 (en) * | 2007-01-12 | 2009-10-27 | Micron Technology, Inc. | Word line drivers having a low pass filter circuit in non-volatile memory device |
KR100885912B1 (ko) * | 2007-01-23 | 2009-02-26 | 삼성전자주식회사 | 기입된 데이터 값에 기초하여 데이터를 선택적으로검증하는 데이터 검증 방법 및 반도체 메모리 장치 |
JP5292052B2 (ja) * | 2008-10-21 | 2013-09-18 | 力晶科技股▲ふん▼有限公司 | 不揮発性半導体記憶装置とその書き込み方法 |
WO2010077414A1 (en) * | 2008-12-09 | 2010-07-08 | Rambus Inc. | Non-volatile memory device for concurrent and pipelined memory operations |
JP2011014195A (ja) * | 2009-07-02 | 2011-01-20 | Toshiba Corp | フラッシュメモリ |
US9007843B2 (en) * | 2011-12-02 | 2015-04-14 | Cypress Semiconductor Corporation | Internal data compare for memory verification |
KR20140076128A (ko) * | 2012-12-12 | 2014-06-20 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 동작 방법과, 이를 포함하는 데이터 처리 시스템 |
US9653180B1 (en) * | 2016-05-26 | 2017-05-16 | Sandisk Technologies Llc | System method and apparatus for screening a memory system |
Citations (3)
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JP2001357682A (ja) * | 2000-06-12 | 2001-12-26 | Sony Corp | メモリシステムおよびそのプログラム方法 |
JP2002025277A (ja) * | 2000-06-30 | 2002-01-25 | Fujitsu Ltd | 多値データを記録する不揮発性メモリ |
JP2004022112A (ja) * | 2002-06-18 | 2004-01-22 | Toshiba Corp | 不揮発性半導体メモリ装置 |
Family Cites Families (15)
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KR0169267B1 (ko) | 1993-09-21 | 1999-02-01 | 사토 후미오 | 불휘발성 반도체 기억장치 |
JP3226677B2 (ja) * | 1993-09-21 | 2001-11-05 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP3170437B2 (ja) * | 1995-09-20 | 2001-05-28 | 株式会社日立製作所 | 不揮発性半導体多値記憶装置 |
US5870335A (en) * | 1997-03-06 | 1999-02-09 | Agate Semiconductor, Inc. | Precision programming of nonvolatile memory cells |
JP3883687B2 (ja) | 1998-02-16 | 2007-02-21 | 株式会社ルネサステクノロジ | 半導体装置、メモリカード及びデータ処理システム |
JP3905979B2 (ja) * | 1998-06-03 | 2007-04-18 | 株式会社東芝 | 不揮発性半導体メモリ |
JP3800466B2 (ja) | 1998-06-29 | 2006-07-26 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JPH1173789A (ja) * | 1998-06-29 | 1999-03-16 | Hitachi Ltd | 半導体不揮発性メモリ |
US6091631A (en) * | 1998-07-01 | 2000-07-18 | Advanced Micro Devices, Inc. | Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed |
JP2000251484A (ja) * | 1999-02-26 | 2000-09-14 | Sony Corp | 不揮発性半導体記憶装置 |
IT1313197B1 (it) * | 1999-07-22 | 2002-06-17 | St Microelectronics Srl | Metodo per la memorizzazione di byte in celle di memoria non volatilimultilivello. |
US6771536B2 (en) * | 2002-02-27 | 2004-08-03 | Sandisk Corporation | Operating techniques for reducing program and read disturbs of a non-volatile memory |
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JP3935139B2 (ja) * | 2002-11-29 | 2007-06-20 | 株式会社東芝 | 半導体記憶装置 |
JP3920768B2 (ja) * | 2002-12-26 | 2007-05-30 | 株式会社東芝 | 不揮発性半導体メモリ |
-
2004
- 2004-07-30 WO PCT/JP2004/010914 patent/WO2006011222A1/ja active Application Filing
- 2004-07-30 KR KR1020077002296A patent/KR101092012B1/ko active IP Right Grant
- 2004-07-30 GB GB0701433A patent/GB2431026B/en not_active Expired - Fee Related
- 2004-07-30 CN CNB2004800440769A patent/CN100555460C/zh not_active Expired - Fee Related
- 2004-07-30 JP JP2006527752A patent/JP4750034B2/ja not_active Expired - Fee Related
- 2004-07-30 DE DE112004002927T patent/DE112004002927B4/de not_active Expired - Fee Related
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2005
- 2005-07-29 US US11/194,023 patent/US7227778B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001357682A (ja) * | 2000-06-12 | 2001-12-26 | Sony Corp | メモリシステムおよびそのプログラム方法 |
JP2002025277A (ja) * | 2000-06-30 | 2002-01-25 | Fujitsu Ltd | 多値データを記録する不揮発性メモリ |
JP2004022112A (ja) * | 2002-06-18 | 2004-01-22 | Toshiba Corp | 不揮発性半導体メモリ装置 |
Also Published As
Publication number | Publication date |
---|---|
KR101092012B1 (ko) | 2011-12-09 |
DE112004002927B4 (de) | 2011-07-21 |
GB2431026A (en) | 2007-04-11 |
CN101027728A (zh) | 2007-08-29 |
DE112004002927T5 (de) | 2008-03-20 |
WO2006011222A1 (ja) | 2006-02-02 |
GB0701433D0 (en) | 2007-03-07 |
JPWO2006011222A1 (ja) | 2008-05-01 |
WO2006011222A8 (ja) | 2006-03-16 |
US20060176742A1 (en) | 2006-08-10 |
KR20070042538A (ko) | 2007-04-23 |
CN100555460C (zh) | 2009-10-28 |
GB2431026B (en) | 2008-05-07 |
US7227778B2 (en) | 2007-06-05 |
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