JP4748705B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4748705B2 JP4748705B2 JP2004198959A JP2004198959A JP4748705B2 JP 4748705 B2 JP4748705 B2 JP 4748705B2 JP 2004198959 A JP2004198959 A JP 2004198959A JP 2004198959 A JP2004198959 A JP 2004198959A JP 4748705 B2 JP4748705 B2 JP 4748705B2
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- 239000004065 semiconductor Substances 0.000 title claims description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 230000015572 biosynthetic process Effects 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 33
- 239000003990 capacitor Substances 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000000151 deposition Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
Claims (6)
- 半導体基板上のメモリセル形成領域に第1の絶縁膜を介してフローティングゲートを形成する工程と、
前記フローティングゲート上にトンネル絶縁膜を形成する工程と、
前記トンネル絶縁膜上及び前記半導体基板上に第1の半導体膜を形成する工程と、
前記第1の半導体膜上に第2の絶縁膜を形成する工程と、
前記第1の半導体膜及び前記第2の絶縁膜を選択的にエッチングして、前記半導体基板上の容量素子形成領域に容量素子の下部電極及び容量絶縁膜を形成する工程と、
前記半導体基板上の全面に第2の半導体膜を形成する工程と、
前記第2の半導体膜を選択的にエッチングして前記容量絶縁膜上に前記下部電極と対向した上部電極を形成する工程と、
前記メモリ形成領域に残存している前記第2の絶縁膜及び前記第1の半導体膜を選択的にエッチングして前記フローティングゲートに隣接するコントロールゲートを形成する工程とを含むことを特徴とする半導体装置の製造方法。 - 前記第2の半導体膜を選択的にエッチングして、前記上部電極と同時に、前記半導体基板上のMOSトランジスタ形成領域にMOSトランジスタのゲート電極を形成する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記フローティングゲートを形成する工程は、
半導体基板上に前記第1の絶縁膜を介して第3の半導体膜、マスク層を順次形成する工程と、
前記マスク層を加工して前記第3の半導体膜の表面を露出する開口部を形成する工程と、
前記マスク層をエッチングマスクとして、第3の半導体膜の表面を等方性エッチングする工程と、
前記マスク層の開口部の側壁にスペーサ膜を形成する工程と、
前記スペーサ膜をエッチングマスクとして前記第3の半導体膜及び前記第1の絶縁膜を順次エッチングして前記半導体基板を露出する工程と、
前記ハードマスクを除去した後に、前記スペーサ膜をエッチングマスクとして前記第3の半導体膜をエッチングする工程とを含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記マスク層は窒化シリコン膜であることを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第1の半導体膜及び第2の半導体膜はポリシリコン膜であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1絶縁膜及び第2の絶縁膜は酸化シリコン膜又は窒化シリコン膜であることを特徴とする請求項1に記載の半導体装置の製造方法
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004198959A JP4748705B2 (ja) | 2004-07-06 | 2004-07-06 | 半導体装置の製造方法 |
CNB2005100819061A CN100370600C (zh) | 2004-07-06 | 2005-07-06 | 半导体装置的制造方法 |
US11/175,050 US7211486B2 (en) | 2004-07-06 | 2005-07-06 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004198959A JP4748705B2 (ja) | 2004-07-06 | 2004-07-06 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006024604A JP2006024604A (ja) | 2006-01-26 |
JP4748705B2 true JP4748705B2 (ja) | 2011-08-17 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004198959A Expired - Fee Related JP4748705B2 (ja) | 2004-07-06 | 2004-07-06 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7211486B2 (ja) |
JP (1) | JP4748705B2 (ja) |
CN (1) | CN100370600C (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7154140B2 (en) * | 2002-06-21 | 2006-12-26 | Micron Technology, Inc. | Write once read only memory with large work function floating gates |
JP2006135178A (ja) * | 2004-11-08 | 2006-05-25 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
CN102361021B (zh) * | 2011-09-28 | 2016-10-19 | 上海华虹宏力半导体制造有限公司 | 一种嵌入式闪存的制作方法 |
CN102361022B (zh) * | 2011-11-02 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | 一种嵌入式闪存的制作方法 |
CN103199091B (zh) * | 2012-01-10 | 2015-12-09 | 旺宏电子股份有限公司 | 半导体结构及其制造方法 |
JP6416595B2 (ja) * | 2014-11-14 | 2018-10-31 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体装置の製造方法 |
CN104637884B (zh) * | 2015-01-31 | 2017-08-25 | 上海华虹宏力半导体制造有限公司 | 快闪存储器的制作方法 |
US9570592B2 (en) * | 2015-06-08 | 2017-02-14 | Silicon Storage Technology, Inc. | Method of forming split gate memory cells with 5 volt logic devices |
CN105679713B (zh) * | 2016-04-26 | 2018-07-27 | 上海华虹宏力半导体制造有限公司 | 闪存器件的制造方法 |
EP3296727B1 (en) * | 2016-09-19 | 2019-04-17 | Murata Integrated Passive Solutions | Electrical stimulation and monitoring device |
CN109065717B (zh) * | 2018-08-06 | 2022-05-10 | 上海华虹宏力半导体制造有限公司 | 一种pip电容的形成方法 |
CN109887914B (zh) * | 2019-03-07 | 2021-04-23 | 上海华虹宏力半导体制造有限公司 | 分栅快闪存储器及其制备方法 |
CN110828373B (zh) * | 2019-11-19 | 2022-02-22 | 上海华虹宏力半导体制造有限公司 | 半导体结构的形成方法 |
CN112382635B (zh) * | 2020-11-12 | 2023-11-10 | 上海华虹宏力半导体制造有限公司 | 半导体器件的制造方法 |
WO2023182376A1 (ja) * | 2022-03-22 | 2023-09-28 | ラピスセミコンダクタ株式会社 | 半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH10154792A (ja) * | 1996-11-21 | 1998-06-09 | Sanyo Electric Co Ltd | 半導体集積回路とその製造方法 |
JP3669200B2 (ja) * | 1999-04-06 | 2005-07-06 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US6277686B1 (en) * | 1999-07-06 | 2001-08-21 | Taiwan Semiconductor Manufacturing Company | PIP capacitor for split-gate flash process |
JP3587100B2 (ja) * | 1999-09-17 | 2004-11-10 | セイコーエプソン株式会社 | 不揮発性メモリトランジスタを含む半導体装置の製造方法 |
JP3617435B2 (ja) * | 2000-09-06 | 2005-02-02 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4076725B2 (ja) * | 2001-01-29 | 2008-04-16 | セイコーインスツル株式会社 | 半導体装置及びその製造方法 |
JP4540899B2 (ja) * | 2001-09-13 | 2010-09-08 | パナソニック株式会社 | 半導体装置の製造方法 |
JP2003124361A (ja) | 2001-10-18 | 2003-04-25 | Sanyo Electric Co Ltd | 半導体メモリ |
US20030080366A1 (en) * | 2001-10-29 | 2003-05-01 | Matsushita Electric Industrial Co., Ltd. | Non-volatile semiconductor memory device and manufacturing method thereof |
JP3924521B2 (ja) * | 2001-10-29 | 2007-06-06 | 松下電器産業株式会社 | 不揮発性半導体記憶装置の製造方法 |
JP3481934B1 (ja) * | 2002-06-21 | 2003-12-22 | 沖電気工業株式会社 | 半導体記憶装置の製造方法 |
KR100487547B1 (ko) * | 2002-09-12 | 2005-05-03 | 삼성전자주식회사 | 비휘발성 메모리 장치의 제조 방법 |
-
2004
- 2004-07-06 JP JP2004198959A patent/JP4748705B2/ja not_active Expired - Fee Related
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2005
- 2005-07-06 CN CNB2005100819061A patent/CN100370600C/zh not_active Expired - Fee Related
- 2005-07-06 US US11/175,050 patent/US7211486B2/en active Active
Also Published As
Publication number | Publication date |
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US7211486B2 (en) | 2007-05-01 |
US20060008986A1 (en) | 2006-01-12 |
CN100370600C (zh) | 2008-02-20 |
CN1719599A (zh) | 2006-01-11 |
JP2006024604A (ja) | 2006-01-26 |
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