JP4691493B2 - マルチプロセッサ・グラフィックス処理システムの適応型負荷分散 - Google Patents
マルチプロセッサ・グラフィックス処理システムの適応型負荷分散 Download PDFInfo
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- 238000012545 processing Methods 0.000 title claims description 45
- 230000003044 adaptive effect Effects 0.000 title description 2
- 238000009877 rendering Methods 0.000 claims description 65
- 230000015654 memory Effects 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 51
- 230000004044 response Effects 0.000 claims description 11
- 239000000872 buffer Substances 0.000 description 64
- 230000008569 process Effects 0.000 description 25
- 238000012546 transfer Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 7
- 238000004364 calculation method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000009466 transformation Effects 0.000 description 4
- 238000000844 transformation Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011094 buffer selection Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2210/00—Indexing scheme for image generation or computer graphics
- G06T2210/52—Parallel processing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Description
本開示は、本出願と同日に出願された「Private Addressing in a Multi−Processor Graphics Processing System」という表題の同一出願人による同時係属米国特許出願第_____号(整理番号019680−006000US)および__年__月__日に出願された「Programming Multiple Chips from a Command Buffer」という表題の同一出願人による同時係属米国特許出願第_____号(整理番号019680−005900US)に関係し、それぞれの開示は、あらゆる目的に関して参照により本明細書に組み込まれる。
以下の詳細な説明を付属の図面と併せて読むと、本発明の性質および利点をよく理解できる。
Claims (22)
- 並列動作するように構成された複数のグラフィックス・プロセッサに命令を与えるCPUによって該複数のグラフィックス・プロセッサの負荷分散を行うための方法であって、
前記CPUによって、表示領域を、前記複数のグラフィックス・プロセッサのうちの第1のプロセッサによりレンダリングされる少なくとも第1の部分と前記複数のグラフィックス・プロセッサのうちの第2のプロセッサによりレンダリングされる第2の部分とに分割するステップと、
前記CPUによって、フレームをレンダリングするよう前記複数のグラフィックス・プロセッサに命令し、前記第1と第2のグラフィックス・プロセッサは、前記表示領域の前記第1と第2の部分に対するレンダリングをそれぞれ実行するステップと、
前記CPUによって、フィードバック・データが前記第1と第2のグラフィックス・プロセッサに対するそれぞれのレンダリング時間を反映するデータであり、前記第1と第2のグラフィックス・プロセッサから前記フレームに対する前記フィードバック・データを受信するステップと、
前記CPUによって、前記フィードバック・データに基づき、前記第1と第2のグラフィックス・プロセッサのそれぞれの負荷の間に不均衡が存在するかどうかを判定するステップと、
不均衡が存在する場合に、
前記CPUによって、前記フィードバック・データに基づき、前記第1と第2のグラフィックス・プロセッサのうちのどちらにより重い負荷がかかっているかを識別するステップと、
前記CPUによって、前記第1と第2のグラフィックス・プロセッサのうちのより重い負荷がかかっているプロセッサでレンダリングされる表示領域の前記第1と第2の部分のうちの前記一方のサイズを増やし、前記表示領域の前記第1と第2の部分の前記他方のサイズを減らすように前記表示領域を再分割するステップと
を含んでおり、
前記フィードバック・データは、前記第1と第2のグラフィックス・プロセッサのうちのどちらがフレームのレンダリングを最後に終了するかを示すデータを含み、
前記受信するステップは、複数のフレームのそれぞれに対する前記フィードバック・データを受信することを含み、
前記判定するステップは、前記複数のフレームに対する前記フィードバック・データから負荷係数を計算することを含み、前記負荷係数は前記第1と第2のグラフィックス・プロセッサのうちの一方が前記レンダリングを最後に終了する頻度を示す、方法。 - 前記表示領域の前記第1の部分は、ピクセルの連続的なラインの第1の数を含み、前記表示領域の前記第2の部分は、ピクセルの連続的なラインの第2の数を含む請求項1に記載の方法。
- 前記表示領域を再分割するステップは、ピクセルの連続的なラインの第3の数を前記表示領域の前記第1の部分から前記表示領域の前記第2の部分にシフトすることを含み、前記第3の数は前記第1の数よりも小さい請求項2に記載の方法。
- ピクセルの前記ラインは、水平方向に向けられている請求項2に記載の方法。
- ピクセルの前記ラインは、垂直方向に向けられている請求項2に記載の方法。
- さらに、前記CPUによって、異なる1つのプロセッサ識別子を前記第1と第2のグラフィックス・プロセッサのそれぞれに割り当てることを含み、
前記第1と第2のグラフィックス・プロセッサのそれぞれから受信された前記フィードバック・データは、前記それぞれのプロセッサ識別子を含む請求項1に記載の方法。 - 前記プロセッサ識別子のそれぞれは数値を持つ請求項6に記載の方法。
- 前記フィードバック・データは、タイムスタンプを含む請求項1に記載の方法。
- 最後に終了する前記第1と第2のグラフィックス・プロセッサのうちの一方からの前記フィードバック・データが前記第1と第2のグラフィックス・プロセッサのうちの他方からのフィードバック・データを上書きする請求項1に記載の方法。
- さらに、
前記CPUによって、それぞれ前記複数のフレームのうちの異なる1つのフレームに関連付けられている複数の格納先を用意することを含み、
前記複数のフレームのそれぞれに対する前記フィードバック・データを受信する前記ステップは、
前記フレームに対する前記表示領域の前記第1の部分をレンダリングした後、前記複数のフレームのそれぞれについて前記格納先のうちの関連付けられた1つに第1のプロセッサ識別子を格納するように前記第1のグラフィックス・プロセッサに命令することと、
前記フレームに対する前記表示領域の前記第2の部分をレンダリングした後、前記複数のフレームのそれぞれについて前記格納先のうちの関連付けられた1つに第1のプロセッサ識別子と異なる第2のプロセッサ識別子を格納するよう前記第2のグラフィックス・プロセッサに命令することと
を含む請求項1に記載の方法。 - フレームのレンダリングを最後に終了した前記第1と第2のグラフィックス・プロセッサのうちの前記一方の前記プロセッサ識別子が前記格納先の中の前記第1と第2のグラフィックス・プロセッサのうちの前記他方の前記プロセッサ識別子を上書きする請求項10に記載の方法。
- 前記第1と第2のグラフィックス・プロセッサのそれぞれに数値識別子が関連付けられ、前記負荷係数は、それぞれのフレームを最後に終了した前記プロセッサの前記数値識別子の前記複数のフレーム上でとった平均である請求項1に記載の方法。
- 判定する前記ステップは、さらに、前記負荷係数を前記数値識別子の算術平均と比較することを含む請求項12に記載の方法。
- 再分割の前記ステップ時に、前記表示領域の前記第1の部分の前記サイズが縮小される量は、前記負荷係数と前記算術平均との差の大きさに少なくとも一部は依存する請求項12に記載の方法。
- さらに、
前記CPUによって、前記第1と第2のグラフィックス・プロセッサのそれぞれについて、前記フレームのレンダリング・コマンドの集合を含むコマンド・ストリームを生成することと、
前記CPUによって、レンダリング・コマンドの前記集合の後に、前記第1と第2のグラフィックス・プロセッサのそれぞれについてライト・ノティファイヤ・コマンドをコマンド・ストリーム内に挿入することと
を含み、前記第1と第2のグラフィックス・プロセッサはそれぞれ、前記フィードバック・データを格納先に送信することにより前記ライト・ノティファイヤ・コマンドに応答する請求項1に記載の方法。 - グラフィックス処理システムであって、
グラフィックス・ドライバ・モジュールと、
表示領域のそれぞれの部分をレンダリングし、フィードバック・データを前記グラフィックス・ドライバ・モジュールに供給するため並列動作するように構成された複数のグラフィックス・プロセッサとを備え、
前記グラフィックス・ドライバ・モジュールは、さらに、前記フィードバック・データに基づき、前記複数のグラフィックス・プロセッサの2つのそれぞれの負荷の間の不均衡を検出し、不均衡を検出したことに対する応答として、前記2つのグラフィックス・プロセッサのうちの負荷が重い方によりレンダリングされる前記表示領域の第1の部分のサイズを減らし、前記2つのグラフィックス・プロセッサのうちの他方によりレンダリングされる前記表示領域の第2の部分のサイズを増やすように構成されており、
前記フィードバック・データは、前記2つのグラフィックス・プロセッサのうちフレームのレンダリングを最後に終了したのはどちらであるのかを示す情報を含み、
前記フィードバック・データは、最後に終了した前記2つのグラフィックス・プロセッサのうちの前記1つの数値識別子を含み、
前記グラフィックス・ドライバ・モジュールは、さらに、複数のフレームについて前記数値識別子からの負荷係数を計算するよう構成され、
前記負荷係数は、前記2つのグラフィックス・プロセッサのうちの一方が前記レンダリングを最後に終了する頻度を示す、グラフィックス処理システム。 - さらに、それぞれ前記グラフィックス・プロセッサのそれぞれの1つに結合され、結合された前記グラフィックス・プロセッサによりレンダリングされる前記表示領域の前記部分に対するピクセル・データを格納する複数のグラフィックス・メモリを備える請求項16に記載のグラフィックス処理システム。
- さらに、前記複数のグラフィックス・メモリに結合され、前記グラフィックス・メモリから前記表示領域に対するピクセル・データを読み取るように構成されたスキャンアウト制御論理回路を備える請求項17に記載のグラフィックス処理システム。
- 前記グラフィックス・ドライバ・モジュールは、さらに、前記複数のグラフィックス・プロセッサに対しコマンド・ストリームを生成するように構成され、
前記コマンド・ストリームは
フレームのレンダリング・コマンドの集合と、
前記フィードバック・データを送信する前記2つのグラフィックス・プロセッサのそれぞれへの命令であって、前記フィードバック・データは、該フィードバック・データを送信する前記グラフィックス・プロセッサが前記レンダリング・コマンドの集合を実行したことを示す、命令と、
を含む請求項16に記載のグラフィックス処理システム。 - 前記グラフィックス・ドライバ・モジュールは、さらに、前記負荷係数が第1しきい値よりも大きいか、または、該第1しきい値よりも低い第2しきい値よりも小さい場合に不均衡を検出するように構成される請求項16に記載のグラフィックス処理システム。
- 前記表示領域のそれぞれの部分は、ピクセルの連続的ラインのいくつかを含み、前記2つのグラフィックス・プロセッサは、隣接する部分をレンダリングするように構成される請求項16に記載のグラフィックス処理システム。
- 前記グラフィックス・ドライバは、さらに、前記第1の部分から前記第2の部分にピクセルのラインのいくつかをシフトすることにより、前記第1の部分の前記サイズを減らし、前記第2の部分の前記サイズを増やすように構成される請求項21に記載のグラフィックス処理システム。
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US10/642,905 US7075541B2 (en) | 2003-08-18 | 2003-08-18 | Adaptive load balancing in a multi-processor graphics processing system |
PCT/US2004/026656 WO2005020157A1 (en) | 2003-08-18 | 2004-08-17 | Adaptive load balancing in a multi-processor graphics processing system |
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- 2004-08-17 DE DE602004019104T patent/DE602004019104D1/de active Active
- 2004-08-17 JP JP2006523975A patent/JP4691493B2/ja active Active
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2006
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Also Published As
Publication number | Publication date |
---|---|
DE602004019104D1 (de) | 2009-03-05 |
CA2535878A1 (en) | 2005-03-03 |
US20050041031A1 (en) | 2005-02-24 |
EP1661092B1 (en) | 2009-01-14 |
US20060221087A1 (en) | 2006-10-05 |
US7075541B2 (en) | 2006-07-11 |
JP2007503059A (ja) | 2007-02-15 |
TWI344108B (en) | 2011-06-21 |
EP1661092A1 (en) | 2006-05-31 |
US20060221086A1 (en) | 2006-10-05 |
TW200511113A (en) | 2005-03-16 |
WO2005020157A1 (en) | 2005-03-03 |
US20100271375A1 (en) | 2010-10-28 |
US8077181B2 (en) | 2011-12-13 |
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