JP4638614B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP4638614B2
JP4638614B2 JP2001027709A JP2001027709A JP4638614B2 JP 4638614 B2 JP4638614 B2 JP 4638614B2 JP 2001027709 A JP2001027709 A JP 2001027709A JP 2001027709 A JP2001027709 A JP 2001027709A JP 4638614 B2 JP4638614 B2 JP 4638614B2
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JP
Japan
Prior art keywords
layer
semiconductor device
forming
manufacturing
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001027709A
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English (en)
Japanese (ja)
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JP2002231855A5 (enExample
JP2002231855A (ja
Inventor
悟 倉持
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2001027709A priority Critical patent/JP4638614B2/ja
Publication of JP2002231855A publication Critical patent/JP2002231855A/ja
Publication of JP2002231855A5 publication Critical patent/JP2002231855A5/ja
Application granted granted Critical
Publication of JP4638614B2 publication Critical patent/JP4638614B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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  • Wire Bonding (AREA)
JP2001027709A 2001-02-05 2001-02-05 半導体装置の作製方法 Expired - Fee Related JP4638614B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001027709A JP4638614B2 (ja) 2001-02-05 2001-02-05 半導体装置の作製方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001027709A JP4638614B2 (ja) 2001-02-05 2001-02-05 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2002231855A JP2002231855A (ja) 2002-08-16
JP2002231855A5 JP2002231855A5 (enExample) 2007-11-29
JP4638614B2 true JP4638614B2 (ja) 2011-02-23

Family

ID=18892317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001027709A Expired - Fee Related JP4638614B2 (ja) 2001-02-05 2001-02-05 半導体装置の作製方法

Country Status (1)

Country Link
JP (1) JP4638614B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7276801B2 (en) 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
WO2005117096A1 (ja) * 2004-05-31 2005-12-08 Sharp Takaya Electronics Industry Co., Ltd. 回路モジュールの製造方法、及びその方法により製造された回路モジュール
JP2007220959A (ja) 2006-02-17 2007-08-30 Fujitsu Ltd 半導体装置及びその製造方法
KR100757910B1 (ko) * 2006-07-06 2007-09-11 삼성전기주식회사 매립패턴기판 및 그 제조방법
JP2008060100A (ja) * 2006-08-29 2008-03-13 Casio Comput Co Ltd 半導体装置およびその製造方法
JP5001957B2 (ja) * 2009-01-27 2012-08-15 パナソニック株式会社 半導体装置及び半導体装置実装基板
JP2014143448A (ja) * 2014-05-12 2014-08-07 Invensys Corp 配線用電子部品及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3398319B2 (ja) * 1997-12-16 2003-04-21 新光電気工業株式会社 半導体装置及びその製造方法
JP2000077565A (ja) * 1998-09-02 2000-03-14 Dainippon Printing Co Ltd 半導体装置および半導体装置の製造方法
JP3661444B2 (ja) * 1998-10-28 2005-06-15 株式会社ルネサステクノロジ 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法
JP2000183223A (ja) * 1998-12-16 2000-06-30 Dainippon Printing Co Ltd 配線部材の製造方法と配線部材
JP2000252384A (ja) * 1999-02-26 2000-09-14 Sumitomo Metal Mining Co Ltd 突起電極付き配線基板への熱可塑性接着剤層形成方法

Also Published As

Publication number Publication date
JP2002231855A (ja) 2002-08-16

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