JP4621049B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

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Publication number
JP4621049B2
JP4621049B2 JP2005089977A JP2005089977A JP4621049B2 JP 4621049 B2 JP4621049 B2 JP 4621049B2 JP 2005089977 A JP2005089977 A JP 2005089977A JP 2005089977 A JP2005089977 A JP 2005089977A JP 4621049 B2 JP4621049 B2 JP 4621049B2
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JP
Japan
Prior art keywords
adhesion layer
layer
wiring
adhesion
wiring structure
Prior art date
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Expired - Fee Related
Application number
JP2005089977A
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English (en)
Japanese (ja)
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JP2006269994A5 (enExample
JP2006269994A (ja
Inventor
香苗 中川
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Fujitsu Ltd
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Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2005089977A priority Critical patent/JP4621049B2/ja
Priority to US11/169,007 priority patent/US7247524B2/en
Publication of JP2006269994A publication Critical patent/JP2006269994A/ja
Publication of JP2006269994A5 publication Critical patent/JP2006269994A5/ja
Application granted granted Critical
Publication of JP4621049B2 publication Critical patent/JP4621049B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0522—Using an adhesive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2005089977A 2005-03-25 2005-03-25 配線基板の製造方法 Expired - Fee Related JP4621049B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005089977A JP4621049B2 (ja) 2005-03-25 2005-03-25 配線基板の製造方法
US11/169,007 US7247524B2 (en) 2005-03-25 2005-06-29 Manufacturing method of wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005089977A JP4621049B2 (ja) 2005-03-25 2005-03-25 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2006269994A JP2006269994A (ja) 2006-10-05
JP2006269994A5 JP2006269994A5 (enExample) 2007-02-22
JP4621049B2 true JP4621049B2 (ja) 2011-01-26

Family

ID=37035732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005089977A Expired - Fee Related JP4621049B2 (ja) 2005-03-25 2005-03-25 配線基板の製造方法

Country Status (2)

Country Link
US (1) US7247524B2 (enExample)
JP (1) JP4621049B2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7485962B2 (en) * 2002-12-10 2009-02-03 Fujitsu Limited Semiconductor device, wiring substrate forming method, and substrate processing apparatus
JP4343044B2 (ja) * 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP4895594B2 (ja) * 2005-12-08 2012-03-14 株式会社ディスコ 基板の切削加工方法
US7545042B2 (en) 2005-12-22 2009-06-09 Princo Corp. Structure combining an IC integrated substrate and a carrier, and method of manufacturing such structure
JP2007194469A (ja) * 2006-01-20 2007-08-02 Renesas Technology Corp 半導体装置の製造方法
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
JP4837696B2 (ja) * 2008-03-24 2011-12-14 新光電気工業株式会社 配線基板の製造方法及び半導体装置の製造方法
TWI419091B (zh) 2009-02-10 2013-12-11 Ind Tech Res Inst 可轉移的可撓式電子裝置結構及可撓式電子裝置的製造方法
CN101833215B (zh) * 2009-03-09 2013-07-10 财团法人工业技术研究院 可挠式电子装置的转移结构及可挠式电子装置的制造方法
US9355962B2 (en) * 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
DE102010016779A1 (de) 2010-05-04 2011-11-10 Cicor Management AG Verfahren zur Herstellung einer flexiblen Schaltungsanordnung
JP5416724B2 (ja) * 2011-01-26 2014-02-12 積水化学工業株式会社 複合体、複合体の製造方法及び多層ビルドアップ配線基板の製造方法
TWI560835B (en) * 2011-11-07 2016-12-01 Siliconware Precision Industries Co Ltd Package substrate and fabrication method thereof
DE102012209328A1 (de) * 2012-06-01 2013-12-05 3D-Micromac Ag Verfahren und Anlage zum Herstellen eines Mehrschichtelements sowie Mehrschichtelement
US20150366077A1 (en) * 2013-01-30 2015-12-17 Kyocera Corporation Method for producing mounted structure
JP7092031B2 (ja) * 2016-09-08 2022-06-28 凸版印刷株式会社 配線基板の製造方法
JP7423907B2 (ja) * 2019-05-24 2024-01-30 Ｔｏｐｐａｎホールディングス株式会社 配線基板の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933743A (en) * 1989-03-11 1990-06-12 Fairchild Semiconductor Corporation High performance interconnect system for an integrated circuit
US6300242B1 (en) * 1999-04-28 2001-10-09 Matsuhita Electronics Corporation Semiconductor device and method of fabricating the same
US7064412B2 (en) * 2000-01-25 2006-06-20 3M Innovative Properties Company Electronic package with integrated capacitor
JP4640878B2 (ja) * 2000-06-21 2011-03-02 富士通株式会社 低誘電率樹脂絶縁層を用いた回路基板の製造方法及び低誘電率樹脂絶縁層を用いた薄膜多層回路フィルムの製造方法
JP3546961B2 (ja) * 2000-10-18 2004-07-28 日本電気株式会社 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ
JP2004087701A (ja) * 2002-08-26 2004-03-18 Nec Toppan Circuit Solutions Toyama Inc 多層配線構造の製造方法および半導体装置の搭載方法
JP3526854B1 (ja) * 2002-09-27 2004-05-17 沖電気工業株式会社 強誘電体メモリ装置
JP2005063988A (ja) * 2003-08-08 2005-03-10 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP2005079108A (ja) * 2003-08-29 2005-03-24 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP4580633B2 (ja) * 2003-11-14 2010-11-17 スタンレー電気株式会社 半導体装置及びその製造方法
JP4549694B2 (ja) * 2004-02-27 2010-09-22 日本特殊陶業株式会社 配線基板の製造方法及び多数個取り基板
JP4565861B2 (ja) * 2004-02-27 2010-10-20 日本特殊陶業株式会社 配線基板の製造方法

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Publication number Publication date
US7247524B2 (en) 2007-07-24
JP2006269994A (ja) 2006-10-05
US20060216861A1 (en) 2006-09-28

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