JP4574976B2 - 微細パターン形成方法 - Google Patents
微細パターン形成方法 Download PDFInfo
- Publication number
- JP4574976B2 JP4574976B2 JP2003385309A JP2003385309A JP4574976B2 JP 4574976 B2 JP4574976 B2 JP 4574976B2 JP 2003385309 A JP2003385309 A JP 2003385309A JP 2003385309 A JP2003385309 A JP 2003385309A JP 4574976 B2 JP4574976 B2 JP 4574976B2
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- Prior art keywords
- photosensitive film
- pattern
- fine pattern
- forming
- film
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
Description
20 …第2コンタクトホール
102 …半導体基板
104 …下部膜
106 …感光膜パターン
106a …第1感光膜
106b …第2感光膜
Claims (11)
- (a)下部膜が形成された半導体基板を提供する段階と、
(b)前記下部膜上に第1感光膜を塗布する段階と、
(c)前記第1感光膜上に前記第1感光膜よりガラス転移温度の高い第2感光膜を塗布する段階と、
(d)フォトマスクを用いた露光工程及び湿式現像工程を行って前記第2感光膜及び前記第1感光膜をパターニングし、これにより第1の臨界寸法を有する第1及び第2感光膜パターンを形成する段階と、
(e)前記第1及び第2感光膜パターンに対してRFP(Resist Flow Process)を行い、前記第1及び第2感光膜パターンの流れを引き起こす段階と、
(f)前記RFPが行われ、前記第1の臨界寸法より小さい第2の臨界寸法となった第1及び第2感光膜パターンをエッチングマスクとして利用したエッチング工程を行って、前記下部膜をパターニングする段階とを含む微細パターン形成方法。 - 前記下部膜はTiN、SiON、Si3N4、アモルファスカーボン系列の有機反射防止膜又は無機反射防止膜であることを特徴とする請求項1記載の微細パターン形成方法。
- 前記第1感光膜と第2感光膜とのガラス転移温度差は1〜10℃であることを特徴とする請求項1記載の微細パターン形成方法。
- 前記第1感光膜と前記第2感光膜は前記ガラス転移温度を除いた物性的特性が互いに同一であることを特徴とする請求項1記載の微細パターン形成方法。
- 前記第1感光膜は0.1μmの厚さに塗布することを特徴とする請求項1記載の微細パターン形成方法。
- 前記第2感光膜は0.5μmの厚さに塗布することを特徴とする請求項1記載の微細パターン形成方法。
- 前記露光工程は、感光剤としてI線、KrF、ArF、EUV、Eビーム又はX線を使用することを特徴とする請求項1記載の微細パターン形成方法。
- 前記RFPの際、加熱時間を50〜200秒とすることを特徴とする請求項1記載の微細パターン形成方法。
- 前記RFPは132℃で90秒間行うことを特徴とする請求項1記載の微細パターン形成方法
- 前記第1感光膜パターンの第2の臨界寸法が0.20μmであることを特徴とする請求項1記載の微細パターン形成方法。
- 前記第2感光膜パターンの第2の臨界寸法が0.13μmであることを特徴とする請求項1記載の微細パターン形成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0079606A KR100498716B1 (ko) | 2002-12-13 | 2002-12-13 | 미세 패턴 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004200659A JP2004200659A (ja) | 2004-07-15 |
JP4574976B2 true JP4574976B2 (ja) | 2010-11-04 |
Family
ID=32653100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003385309A Expired - Fee Related JP4574976B2 (ja) | 2002-12-13 | 2003-11-14 | 微細パターン形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6998351B2 (ja) |
JP (1) | JP4574976B2 (ja) |
KR (1) | KR100498716B1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100775561B1 (ko) * | 2006-05-26 | 2007-11-16 | 주식회사 케이티프리텔 | 이동 통신 단말기에서의 통화중 감성 및 상태 전달 방법 |
KR100891703B1 (ko) * | 2007-03-30 | 2009-04-03 | 주식회사 엘지화학 | 마이크로 패턴이 형성된 필름의 제조방법 및 그로부터제조된 필름 |
CN109270796B (zh) * | 2017-07-17 | 2020-12-04 | 京东方科技集团股份有限公司 | 阵列基板的制备方法 |
CN110931354B (zh) * | 2018-09-19 | 2023-05-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构以及半导体结构的制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61271840A (ja) * | 1985-05-27 | 1986-12-02 | Toshiba Corp | 半導体装置の製造方法 |
JPS6236827A (ja) * | 1985-08-10 | 1987-02-17 | Nippon Gakki Seizo Kk | 選択エツチング方法 |
JPH01307228A (ja) * | 1988-06-06 | 1989-12-12 | Hitachi Ltd | パターン形成法 |
JPH05267254A (ja) * | 1992-03-17 | 1993-10-15 | Oki Electric Ind Co Ltd | 半導体素子のパターン形成方法 |
JPH0697128A (ja) * | 1992-07-31 | 1994-04-08 | Internatl Business Mach Corp <Ibm> | 多層金属構造の製造中におけるポリイミド皮膜のパターン形成方法 |
JP2001326153A (ja) * | 2000-05-12 | 2001-11-22 | Nec Corp | レジストパターンの形成方法 |
Family Cites Families (15)
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CA2071598C (en) * | 1991-06-21 | 1999-01-19 | Akira Eda | Optical device and method of manufacturing the same |
US5477360A (en) * | 1993-04-23 | 1995-12-19 | Kabushiki Kaisha Toshiba | Liquid crystal display device |
US5519802A (en) * | 1994-05-09 | 1996-05-21 | Deacon Research | Method for making devices having a pattern poled structure and pattern poled structure devices |
TWI250379B (en) * | 1998-08-07 | 2006-03-01 | Az Electronic Materials Japan | Chemical amplified radiation-sensitive composition which contains onium salt and generator |
US6284149B1 (en) * | 1998-09-18 | 2001-09-04 | Applied Materials, Inc. | High-density plasma etching of carbon-based low-k materials in a integrated circuit |
KR100317583B1 (ko) * | 1998-12-28 | 2002-05-13 | 박종섭 | 반도체소자의제조방법 |
JP3454234B2 (ja) * | 1999-09-27 | 2003-10-06 | 日産自動車株式会社 | 分割コアモータ |
KR100349375B1 (ko) * | 1999-12-17 | 2002-08-21 | 주식회사 하이닉스반도체 | 레지스트 플로우 공정과 전자 빔 주사 공정을 병용한콘택홀 형성방법 |
KR100599446B1 (ko) * | 2000-08-31 | 2006-07-12 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
JP4269544B2 (ja) * | 2000-09-14 | 2009-05-27 | 株式会社デンソー | 複数ロータ型同期機 |
KR20020043958A (ko) * | 2000-12-05 | 2002-06-12 | 박종섭 | 반도체소자의 콘택홀 제조방법 |
US6504285B2 (en) * | 2001-02-08 | 2003-01-07 | Jae Shin Yun | Vector motor |
US6809456B2 (en) * | 2001-02-08 | 2004-10-26 | Jae Shin Yun | Vector motor |
JP4057807B2 (ja) * | 2001-12-03 | 2008-03-05 | 東京応化工業株式会社 | 微細レジストパターン形成方法 |
US6645851B1 (en) * | 2002-09-17 | 2003-11-11 | Taiwan Semiconductor Manufacturing Company | Method of forming planarized coatings on contact hole patterns of various duty ratios |
-
2002
- 2002-12-13 KR KR10-2002-0079606A patent/KR100498716B1/ko not_active IP Right Cessation
-
2003
- 2003-07-08 US US10/614,182 patent/US6998351B2/en not_active Expired - Fee Related
- 2003-11-14 JP JP2003385309A patent/JP4574976B2/ja not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61271840A (ja) * | 1985-05-27 | 1986-12-02 | Toshiba Corp | 半導体装置の製造方法 |
JPS6236827A (ja) * | 1985-08-10 | 1987-02-17 | Nippon Gakki Seizo Kk | 選択エツチング方法 |
JPH01307228A (ja) * | 1988-06-06 | 1989-12-12 | Hitachi Ltd | パターン形成法 |
JPH05267254A (ja) * | 1992-03-17 | 1993-10-15 | Oki Electric Ind Co Ltd | 半導体素子のパターン形成方法 |
JPH0697128A (ja) * | 1992-07-31 | 1994-04-08 | Internatl Business Mach Corp <Ibm> | 多層金属構造の製造中におけるポリイミド皮膜のパターン形成方法 |
JP2001326153A (ja) * | 2000-05-12 | 2001-11-22 | Nec Corp | レジストパターンの形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US6998351B2 (en) | 2006-02-14 |
KR20040051912A (ko) | 2004-06-19 |
KR100498716B1 (ko) | 2005-07-01 |
US20040127056A1 (en) | 2004-07-01 |
JP2004200659A (ja) | 2004-07-15 |
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