TWI304226B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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TWI304226B
TWI304226B TW095131540A TW95131540A TWI304226B TW I304226 B TWI304226 B TW I304226B TW 095131540 A TW095131540 A TW 095131540A TW 95131540 A TW95131540 A TW 95131540A TW I304226 B TWI304226 B TW I304226B
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Taiwan
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pattern
reflection
film
mask
photoresist
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TW095131540A
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Chinese (zh)
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TW200725735A (en
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Sung Koo Lee
Jae Chang Jung
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Materials For Photolithography (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Description

1304226 九、發明說明： 【發明所屬之技術領域】 概括而言，揭示的内容乃關於製造半導體元件的方法。 :特定而t，揭示的内容乃關於形成圖案的方法，复可以 克服製造半導體元件之蝕印法的解析限制。 【先前技術】 最近已進行雙重曝光法來形成半導體元件的精細圖 案，以克服曝光設備的解析限制。此傳統方法描述如下。 —參見圖，於半導體基板h依序形成底層12、 弟—硬遮罩層13、第-抗反射膜14、第—光賴15。使 用弟-曝光遮i 16將整個表面的第—區域加以曝光，並 且將曝光的光阻膜1 5顯吾彡L7游#餘 , 兀,朕U顯衫以形成第一光阻圖案15，。硬遮 罩層13通常是非晶形碳層和無機硬遮罩層所構成的雙層。 ^參見圖1。和ld，以第一光阻圖案15，做為遮罩來二刻 弟抗反射膜14，藉此形成第一抗反射圖案14，。再以第 反射圖案14’做為遮罩來#刻第—硬遮罩| 13，遂形 成第一硬遮罩圖案13，。 _參見圖16和lf，於第一硬遮罩圖案13,上依序形成第 :硬遮罩I 17、第二抗反射膜18、第二光阻膜19。使用 第一曝光遮罩20將整個表面的第二區域以與第一區域交 =的方式加以曝光，並且將曝光的光阻臈19冑影以形成 第二光阻圖案19’。第二硬遮罩層17最好具有不同於第一 硬遮罩層13的蝕刻選擇性。 簽見圖lg和lh，以第二光阻圖案19，做為遮罩來蝕刻 1304226 第二抗反射膜1 8，藉此形成第二抗反射圖案18，。再以第 二抗反射圖案18,做為遮罩來蝕刻第二硬遮罩層17，遂形 成第二硬遮罩圖案17,。 參見圖li，以第一和第二硬遮罩圖案13，、17，做為遮 罩來餘刻底層12，藉以獲得精細的圖案12,。 然而’在上述的傳統方法中，光阻膜、抗反射膜、硬 遮罩層必須分別彼覆和蝕刻二次，以便形成精細的圖案。 因此’整體製程變得複雜，導致總生產率下降。 . 【發明内容】 在此揭示的是製造半導體元件的方法，其包括於包含 石夕（Si)的抗反射膜上進行ο:電漿處理步驟。揭示之方法的 4點在於製備硬遮罩層的彼覆和姓刻步驟只須要進行一 次’故簡化和減少了傳統製程的整體時間和成本。 為了更完全地了解本發明，應該參考以下詳細說明和 所附圖式。雖然揭示的方法容許有各種形式的具體態樣， .但是圖式所示範的（之後將會敘述）是本發明的特定具體態 樣；要理解的是本揭示内容乃示範性的，而並非要將本發 明限制於在此所述和示範的特定具體態樣。 【實施方式】 在此揭示的是製造半導體元件的方法，其包括於半導 體基板上依序形成底層、硬遮罩層、包含Si的第一抗反射 膜、第一光阻膜。此方法也包括使用第一曝光遮罩將第一 光阻膜加以曝光和顯影而形成第一光阻圖案，以及以第一 光阻圖案做為遮罩來蝕刻第一抗反射膜，藉此形成第一抗 6 1304226 反射圖案。此方法進一步包括於第一抗反射圖案上進行〇, 電漿處理，然後於〇2電漿處理的第一抗反射圖案上依序形 成第二抗反射膜和第二光阻膜，以及使用第二曝光遮罩將 相對於第一抗反射圖案的交錯區域加以曝光和顯影，而形 成第二光阻圖案。此方法也包括以第二光阻圖案做為遮罩 來蝕刻第二抗反射膜，藉此形成第二抗反射圖案，並且以 第一和第二抗反射圖案做為遮罩來蝕刻硬遮罩層而形成硬 遮罩圖案’以及以硬遮罩圖案做為遮罩來蝕刻底層，藉此 鲁形成底圖案。 根據所揭示的方法，第一抗反射圖案是使用包含矽元 素的抗反射膜所形成。然後，進行02電漿處理以氧化第一 抗反射圖案裡的矽，如此則第一抗反射圖案就不會在形成 第一抗反射膜之後的後續顯影步驟中顯影。矽存在的含量 - 範圍佔第一抗反射膜總重量的大約3〇重量％到大約40重 量％。 在揭示的方法中，第二抗反射膜可以使用與第一抗反 射膜相同或不同的材料來形成。不同的材料意指任何不含 矽70素的抗反射組成物，而不像第一抗反射膜。第二抗反 射膜可以使用傳統的抗反射組成物來形成而無限制。 同時，對於包含矽元素的抗反射組成物而言，可以使 用任何傳統的有機抗反射組成物，其包括能夠交聯的聚合 物、吸光劑、有機溶液，而無限制。包含以的抗反射組成 物可以進一步包括交聯劑，以便於熱處理時活化交聯反 應0 1304226 2a1304226 IX. Description of the Invention: [Technical Field to Which the Invention Is Applicable] In summary, the disclosure relates to a method of manufacturing a semiconductor element. : Specific and t, the disclosure is about the method of forming a pattern, which can overcome the analytical limitations of the lithography method for manufacturing semiconductor components. [Prior Art] A double exposure method has recently been carried out to form a fine pattern of a semiconductor element to overcome the resolution limitation of the exposure apparatus. This conventional method is described below. - Referring to the figure, the underlayer 12, the smear-hard mask layer 13, the first anti-reflection film 14, and the first-light ray 15 are sequentially formed on the semiconductor substrate h. The first region of the entire surface is exposed by using the mask-exposure mask 16, and the exposed photoresist film 15 is exposed to form a first photoresist pattern 15. The hard mask layer 13 is typically a double layer of an amorphous carbon layer and an inorganic hard mask layer. ^ See Figure 1. And ld, the first anti-reflection film 14 is formed by using the first photoresist pattern 15 as a mask, thereby forming the first anti-reflection pattern 14. Then, the first reflective mask pattern 13 is formed by using the first reflective pattern 14' as a mask. Referring to FIGS. 16 and 1f, a first hard mask I 17, a second anti-reflection film 18, and a second photoresist film 19 are sequentially formed on the first hard mask pattern 13. The second region of the entire surface is exposed in a manner to intersect the first region using the first exposure mask 20, and the exposed photoresist 胄 19 is patterned to form the second photoresist pattern 19'. The second hard mask layer 17 preferably has an etch selectivity different from that of the first hard mask layer 13. Referring to the figures lg and lh, the second photoresist pattern 19 is used as a mask to etch 1304226 the second anti-reflection film 18, thereby forming a second anti-reflection pattern 18. Further, the second anti-reflective pattern 18 is used as a mask to etch the second hard mask layer 17, and the second hard mask pattern 17 is formed. Referring to Fig. Li, the first and second hard mask patterns 13, 17, are used as masks to engrave the bottom layer 12 to obtain a fine pattern 12. However, in the above conventional method, the photoresist film, the antireflection film, and the hard mask layer must be separately coated and etched twice to form a fine pattern. Therefore, the overall process becomes complicated, resulting in a decrease in total productivity. SUMMARY OF THE INVENTION Disclosed herein is a method of fabricating a semiconductor device comprising performing a plasma processing step on an antireflective film comprising Shi Xi (Si). The four points of the disclosed method are that the process of preparing the hard mask layer and the surname step only need to be performed once, thus simplifying and reducing the overall time and cost of the conventional process. For a fuller understanding of the invention, reference should be made to Although the disclosed methods are to be construed as being in a variety of specific forms, the embodiments of the present invention, which will be described hereinafter, are specific embodiments of the present invention; it is understood that the present disclosure is exemplary and not intended The invention is limited to the specific embodiments described and exemplified herein. [Embodiment] Disclosed herein is a method of fabricating a semiconductor device comprising sequentially forming a bottom layer, a hard mask layer, a first anti-reflective film containing Si, and a first photoresist film on a semiconductor substrate. The method also includes exposing and developing the first photoresist film to form a first photoresist pattern using a first exposure mask, and etching the first anti-reflection film with the first photoresist pattern as a mask, thereby forming First anti- 6 1304226 reflective pattern. The method further includes performing a ruthenium, a plasma treatment on the first anti-reflection pattern, and then sequentially forming the second anti-reflection film and the second photoresist film on the first anti-reflection pattern of the 〇2 plasma treatment, and using the The second exposure mask exposes and develops the interlaced area with respect to the first anti-reflection pattern to form a second photoresist pattern. The method also includes etching the second anti-reflective film with the second photoresist pattern as a mask, thereby forming a second anti-reflective pattern, and etching the hard mask with the first and second anti-reflective patterns as masks The layer forms a hard mask pattern and the hard mask pattern is used as a mask to etch the underlayer, thereby forming a bottom pattern. According to the disclosed method, the first anti-reflection pattern is formed using an anti-reflection film comprising an element. Then, 02 plasma treatment is performed to oxidize the ruthenium in the first anti-reflection pattern, so that the first anti-reflection pattern is not developed in the subsequent development step after the formation of the first anti-reflection film. The content of cerium is present in a range of from about 3% by weight to about 40% by weight based on the total weight of the first antireflective film. In the disclosed method, the second anti-reflection film may be formed using the same or different material as the first anti-reflection film. Different materials mean any anti-reflective composition that does not contain 矽70, unlike the first anti-reflective film. The second anti-reflective film can be formed using a conventional anti-reflective composition without limitation. Meanwhile, for the antireflection composition containing a ruthenium element, any conventional organic antireflection composition including a polymer capable of crosslinking, a light absorbing agent, and an organic solution can be used without limitation. The antireflective composition comprising may further comprise a crosslinking agent to facilitate activation of the crosslinking reaction during heat treatment 0 1304226 2a

在此之後，揭示之製造半導體元件的方法會參考圖 2i詳細描述，圖2a到2i是示範本方法的截面圖解。 參見圖2a和2b，於半導體基板11〇 120、硬遮罩層130、第一抗反射膜14〇、第 上依序形成底層 一光阻臈15〇。Hereinafter, a method of manufacturing a semiconductor element will be described in detail with reference to Fig. 2i, which are schematic cross-sectional views illustrating the method. Referring to Figures 2a and 2b, a bottom layer of photoresist 15 is formed sequentially on the semiconductor substrate 11A, the hard mask layer 130, the first anti-reflective film 14A, and the first.

使用第一曝光遮罩160將整個表面的第一區域加以曝光， 以及將曝光的光阻膜150顯影以形成第一光阻圖案^〇，。 第一抗反射膜140包含矽（Si)，其含量範圍最好佔第一抗 反射膜140總重量的大約30重量％到大約4〇重量％。= 遮罩層1 30通常是非晶形碳層和無機硬遮罩層所構成的雙 層。此夕卜’曝光步㈣光源可以是任何能夠⑹共光線波長 小於400奈米的來源。特定而言，光源最好是選自由 奈米）、KrF(248 奈米）、EUV(ext麵e ultravi〇let、極度紫 外線）、VUV(vacuum ultraviolet、真空紫外線）、電子束、 X射線、離子束所構成的群組。在這些之中，較佳為ArF、 KrF或VUV，最佳則是ArF。曝光步驟通常是以大約每平 方公分70毫焦耳到大約每平方公分15〇毫焦耳的曝光能 量範圍來進行，最好大約每平方公分1〇〇毫焦耳，此視光 阻膜的類型而定。 參見圖2c和2d，以第一光阻圖案15〇,做為遮罩將第 一抗反射膜140加以蝕刻，藉此形成第一抗反射圖案14〇,。 在此之後，於第一抗反射圖案14〇，上進行〇2電漿處理， 以氧化當中包含的石夕，藉此形成包含Si〇2的第一抗反射圖 案 145。 麥見圖2e和2f，於包含Si〇2的第一抗反射圖案145 1304226 上形成第一抗反射膜1 80和第二光阻膜i 90。使用第二曝 光遮罩200將整個表面的第二區域加以曝光（其交錯於第一 區域），以及將曝光的光阻膜19〇顯影以形成第二光阻圖案 190,。 參見圖2g和2h，以第二光阻圖案19〇，做為遮罩來蝕 刻第二抗反射膜180,藉此形成第二抗反射圖案18〇，。儘 管有此蝕刻步驟，由於Si因〇2電漿處理而氧化成Si〇2， 故第一抗反射圖案145仍在。再以第一和第二抗反射圖案 145、180’做為遮罩來蝕刻硬遮罩層13〇，遂形成硬遮罩圖 案 130,。 參見圖2l，以硬遮罩圖案130,做為遮罩來蝕刻底層 12〇,以及移除硬遮罩圖案13〇，，藉以獲得精細的圖案 120,。 如上所述，揭示的製造半導體元件的方法包括在形成 包含Si的抗反射膜之後進行〇2電漿處理步驟。 【圖式簡單說明】 圖la到li疋不範形成半導體元件之傳統方法的截面 圖解。 圖2a到2i是示銘职+ + $ & t 乾$成+導體凡件之本發明方法的截 面圖解。 【主要元件符號說明】 11 半導體基板 12 底層 12， 底層圖案 1304226 13 第一硬遮罩層 13? 第一硬遮罩圖 14 第一抗反射膜 14’ 第一抗反射圖 15 第一光阻膜 159 第一光阻圖案 16 第一曝光遮罩 17 第二硬遮罩層 175 第二硬遮罩圖 18 第二抗反射膜 185 第二抗反射圖 19 第二光阻膜 195 第二光阻圖案 20 第二曝光遮罩 110 半導體基板 120 底層 1209 底層圖案 130 第一硬遮罩層 130’ 第一硬遮罩圖 140 第一抗反射膜 140? 第一抗反射圖 145 包含Si02的第 150 第一光阻膜 150’ 第一光阻圖案 抗反射圖案 10 1304226 160 第一曝光遮罩 180 第二抗反射膜 1809 第二抗反射圖案 190 第二光阻膜 1905 第二光阻圖案 200 第二曝光遮罩The first area of the entire surface is exposed using the first exposure mask 160, and the exposed photoresist film 150 is developed to form a first photoresist pattern. The first anti-reflection film 140 contains bismuth (Si) in an amount preferably ranging from about 30% by weight to about 4,000% by weight based on the total weight of the first anti-reflection film 140. = Mask layer 1 30 is typically a double layer of amorphous carbon layer and inorganic hard mask layer. Further, the exposure step (four) light source can be any source capable of (6) a common light wavelength of less than 400 nm. In particular, the light source is preferably selected from the group consisting of nanometers, KrF (248 nm), EUV (ext surface e ultravi〇let, extreme ultraviolet light), VUV (vacuum ultraviolet, vacuum ultraviolet light), electron beam, X-ray, ion A group of bundles. Among these, ArF, KrF or VUV is preferred, and ArF is the best. The exposure step is typically carried out at an exposure energy level of from about 70 millijoules per square centimeter to about 15 millijoules per square centimeter, preferably about one millijoule per square centimeter, depending on the type of photoresist. Referring to Figures 2c and 2d, the first anti-reflective film 140 is etched as a mask with the first photoresist pattern 15A, thereby forming a first anti-reflection pattern 14?. Thereafter, a 〇2 plasma treatment is performed on the first anti-reflection pattern 14A to oxidize the cerium contained therein, thereby forming a first anti-reflection pattern 145 containing Si〇2. Referring to Figures 2e and 2f, a first anti-reflective film 180 and a second photoresist film i 90 are formed on a first anti-reflective pattern 145 1304226 comprising Si〇2. The second area of the entire surface is exposed (interlaced to the first area) using the second exposure mask 200, and the exposed photoresist film 19 is developed to form the second photoresist pattern 190. Referring to Figures 2g and 2h, the second anti-reflective film 180 is etched by the second photoresist pattern 19, as a mask, thereby forming a second anti-reflection pattern 18?. Despite this etching step, the first anti-reflection pattern 145 is still present because Si is oxidized to Si〇2 due to the plasma treatment of 〇2. The hard mask layer 13 is then etched by using the first and second anti-reflective patterns 145, 180' as a mask to form a hard mask pattern 130. Referring to Fig. 21, the hard mask pattern 130 is used as a mask to etch the underlying layer 12, and the hard mask pattern 13 is removed to obtain a fine pattern 120. As described above, the disclosed method of fabricating a semiconductor device includes performing a 〇2 plasma treatment step after forming an anti-reflection film containing Si. BRIEF DESCRIPTION OF THE DRAWINGS Fig. la to li is a cross-sectional illustration of a conventional method of forming a semiconductor device. Figures 2a through 2i are cross-sectional illustrations of the method of the present invention showing the inscription + + $ & t dry + + conductor. [Main component symbol description] 11 Semiconductor substrate 12 Underlayer 12, underlying pattern 1304226 13 First hard mask layer 13? First hard mask Figure 14 First anti-reflection film 14' First anti-reflection pattern 15 First photoresist film 159 first photoresist pattern 16 first exposure mask 17 second hard mask layer 175 second hard mask pattern 18 second anti-reflection film 185 second anti-reflection pattern 19 second photoresist film 195 second photoresist pattern 20 second exposure mask 110 semiconductor substrate 120 bottom layer 1209 bottom layer pattern 130 first hard mask layer 130' first hard mask pattern 140 first anti-reflection film 140? first anti-reflection pattern 145 contains the first 150th of SiO2 Photoresist film 150' first photoresist pattern anti-reflection pattern 10 1304226 160 first exposure mask 180 second anti-reflection film 1809 second anti-reflection pattern 190 second photoresist film 1905 second photoresist pattern 200 second exposure mask cover

Claims (1)

1304226 十、申請專利範圍： i一種製造半導體元件的方法，此方法包括： ))於半導體基板上依序形成底層、硬遮罩層、包含Si 的第一抗反射膜、第一光阻膜； ,使用第一曝光遮罩將第一光阻膜加以曝光和顯影而 7成第-光阻圖案，並且以第一光阻圖案做為遮罩來蝕刻 弟抗反射膜，藉此形成第一抗反射圖案； (C)於第一抗反射圖案上進行&電漿處理； ’ ⑷於〇2電漿處理的第一抗反射圖案上依序形成第二 2反射膜和第二光阻膜，以及使用第二曝光遮罩將相對於 第一抗反射圖案的交錯區域加以曝光和顯影，而形成第二 光阻圖案； (e)以第二光阻圖案做為遮罩來蝕刻第二抗反射膜，藉 此形成第二抗反射圖案；以及 (0以第一和第二抗反射圖案做為遮罩來蝕刻硬遮罩層 而形成硬遮罩圖案，並且以硬遮罩圖案做為遮罩來蝕刻底 .層，藉此形成底圖案。 2·根據申請專利範圍第1項的方法，其中第一抗反射 膜包括石夕，其含量範圍佔第一抗反射膜總重量的3〇重量％ 到40重量％。 3 ·根據申請專利範圍第1項的方法，其中光源是選自 由 ArF(193 奈米）、KrF(248 奈米）、EUV(extreme ultraviolet、 極度紫外線）、VUV(vacuum ultraviolet、真空紫外線）、電 子束、X射線、離子束所構成的群組。 12 1304226 3項的方法，其中光源是 4·根據申請專利範圍第 ArF(193 奈米）。 曰/根據申清專利範圍第1項的方法，其中硬遮罩層是 非晶形碳層和無機硬遮罩層所構成的雙層。 以斤、，據申明專利範圍第1項的方法，其中曝光步驟是 曰=方A分7〇晕焦耳到每平方公分150毫焦耳的曝光 能量來進行。 —7·根據申請專利範圍第6項的方法，其中曝光能量是 母平方公分100毫焦耳。 +曰 據申明專利範圍第1項的方法，其中第二抗反射 膜疋使用與第一抗反射膜相同或不同的材料所形成。 9·種製造半導體元件的方法，此方法包括： (a)於半導體基板上依序形成底層、包含Si的第一抗 反射膜、第一光阻膜； ^ 、2)使用第一曝光遮罩將第一光阻膜加以曝光和顯影而 =成第一光阻圖案，並且以第一光阻圖案做為遮罩來蝕刻 第一抗反射膜，藉此形成第一抗反射圖案； (C)於第一抗反射圖案上進行02電漿處理； (d)於〇2電漿處理的第一抗反射圖案上依序形成第二 抗反射膜和第二光阻膜，並且使用第二曝光遮罩將相對於 第一抗反射圖案的交錯區域加以曝光和顯影，而形成第二 (e)以第二光阻圖案做為遮罩來蝕刻第二抗反射膜，藉 此形成第二抗反射圖案；以及 曰 13 1304226 (〇以第一和第二抗反射圖案做為遮罩來蝕刻底層，而 形成底圖案。 十一、圖式： 如次頁1304226 X. Patent Application Range: i A method for manufacturing a semiconductor device, the method comprising:)) sequentially forming a bottom layer, a hard mask layer, a first anti-reflection film containing Si, and a first photoresist film on a semiconductor substrate; The first photoresist film is exposed and developed using a first exposure mask to form a first photoresist pattern, and the first photoresist pattern is used as a mask to etch the anti-reflection film, thereby forming a first anti-reflection film. (C) performing & plasma treatment on the first anti-reflection pattern; '(4) sequentially forming the second 2 reflection film and the second photoresist film on the first anti-reflection pattern of the 电2 plasma treatment, And exposing and developing the staggered area with respect to the first anti-reflective pattern using a second exposure mask to form a second photoresist pattern; (e) etching the second anti-reflection with the second photoresist pattern as a mask a film, thereby forming a second anti-reflection pattern; and (0 using the first and second anti-reflection patterns as a mask to etch the hard mask layer to form a hard mask pattern, and using the hard mask pattern as a mask To etch the bottom layer, thereby forming a bottom pattern. According to the method of claim 1, wherein the first anti-reflection film comprises Shi Xi, and the content thereof ranges from 3% by weight to 40% by weight based on the total weight of the first anti-reflection film. The method, wherein the light source is selected from the group consisting of ArF (193 nm), KrF (248 nm), EUV (extreme ultraviolet), VUV (vacuum ultraviolet, vacuum ultraviolet), electron beam, X-ray, ion beam 12 1304226 The method of item 3, wherein the light source is 4· according to the patent application scope ArF (193 nm). 曰 / according to the method of claim 1, wherein the hard mask layer is an amorphous carbon layer And a double layer composed of an inorganic hard mask layer. In the method of claim 1, wherein the exposure step is 曰 = square A, 7 〇 halo, to 150 mJ per square centimeter of exposure energy. In accordance with the method of claim 6, wherein the exposure energy is 100 mJ of the square centimeter. + The method according to claim 1 of the patent scope, wherein the second anti-reflection film is used and The antireflection film is formed of the same or different materials. 9. A method for manufacturing a semiconductor device, the method comprising: (a) sequentially forming a bottom layer, a first anti-reflection film containing Si, and a first photoresist film on a semiconductor substrate ^, 2) using the first exposure mask to expose and develop the first photoresist film to become the first photoresist pattern, and etching the first anti-reflection film with the first photoresist pattern as a mask, Forming a first anti-reflection pattern; (C) performing 02 plasma treatment on the first anti-reflection pattern; (d) sequentially forming a second anti-reflection film on the first anti-reflection pattern of the 〇2 plasma treatment a second photoresist film, and exposing and developing the interlaced area with respect to the first anti-reflection pattern using a second exposure mask to form a second (e) etching the second anti-etching with the second photoresist pattern as a mask Reflecting the film, thereby forming a second anti-reflective pattern; and 曰13 1304226 (the first and second anti-reflective patterns are used as a mask to etch the underlayer to form a bottom pattern. XI. Schema: as the next page 1414
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