KR100772801B1 - Method of Manufacturing Semiconductor Device - Google Patents

Method of Manufacturing Semiconductor Device Download PDF

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KR100772801B1
KR100772801B1 KR1020060069759A KR20060069759A KR100772801B1 KR 100772801 B1 KR100772801 B1 KR 100772801B1 KR 1020060069759 A KR1020060069759 A KR 1020060069759A KR 20060069759 A KR20060069759 A KR 20060069759A KR 100772801 B1 KR100772801 B1 KR 100772801B1
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pattern
reflection film
photoresist
film
layer
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KR1020060069759A
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Korean (ko)
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KR20070070035A (en
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이성구
정재창
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주식회사 하이닉스반도체
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Priority to TW095131540A priority Critical patent/TWI304226B/en
Priority to US11/468,080 priority patent/US7807336B2/en
Priority to JP2006243018A priority patent/JP5174335B2/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Abstract

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 실리콘이 함유된 반사방지막을 형성한 후 02 플라즈마 공정을 수행함으로써 하드마스크층의 코팅 및 식각 공정은 1회만 수행하도록 하여 공정을 단순화시키며 시간 및 비용을 감소시키는 기술을 나타낸다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by forming a anti-reflective film containing silicon and then performing a 0 2 plasma process to simplify the process of coating and etching the hard mask layer only once. Represents a technique to reduce time and cost.

Description

반도체 소자의 제조 방법{Method of Manufacturing Semiconductor Device}Method of manufacturing semiconductor device {Method of Manufacturing Semiconductor Device}

도 1a 내지 도 1i는 종래 반도체 소자의 제조 방법을 도시한 공정 단면도이다.1A to 1I are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

도 2a 내지 도 2i는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 공정 단면도이다.2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

11, 110 : 반도체 기판, 12, 120 : 피식각층,11 and 110: semiconductor substrate, 12 and 120: etching target layer,

13,17,130 : 하드마스크층, 14,18,140,180 : 반사방지막,13,17,130: hard mask layer, 14,18,140,180: antireflection film,

15,19,150,190 : 감광막, 16,160,20,200 : 노광 마스크,15,19,150,190: photosensitive film, 16,160,20,200: exposure mask,

12',120' : 피식각층 패턴, 13',17',130' : 하드마스크 패턴,12 ', 120': Etch layer pattern, 13 ', 17', 130 ': Hard mask pattern,

14',18',140',180' : 반사방지막 패턴,14 ', 18', 140 ', 180': antireflection film pattern,

15',19',150',190' : 감광막 패턴,15 ', 19', 150 ', 190': photoresist pattern,

145 : O2 플라즈마 처리된 SiO2 포함 반사방지막 패턴145: O 2 plasma treated anti-reflection film pattern containing SiO 2

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 보다 상세하게는 반도체 공정 중 리소그래피(Lithography) 공정의 해상 한계를 뛰어 넘는 패턴 형성을 가능하게 하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that enables pattern formation exceeding a resolution limit of a lithography process during a semiconductor process.

최근 반도체 소자의 제조시 노광 장비의 한계를 극복하기 위해 이중 노광 공정으로 미세 패턴을 형성하고 있으며, 그 공정 과정은 다음과 같다.In order to overcome the limitations of exposure equipment in the manufacture of semiconductor devices in recent years, fine patterns are formed by a double exposure process, and the process is as follows.

도 1a 및 도 1b를 참조하면, 반도체 기판(11)의 피식각층(12) 상부에 제1 하드마스크층(13), 제1 반사방지막(14) 및 제1 감광막(15)을 순차적으로 형성한 후, 제1 노광마스크(16)를 이용하여 전체 표면의 제1 영역을 노광하고, 노광된 제1 감광막(15)을 현상하여 제1 감광막 패턴(15')을 형성한다. 이때, 상기 하드마스크층은 통상 비정질 탄소층 및 무기계 하드마스크층의 2중층으로 구성되어 있다.1A and 1B, the first hard mask layer 13, the first antireflection film 14, and the first photoresist film 15 are sequentially formed on the etched layer 12 of the semiconductor substrate 11. Subsequently, the first area of the entire surface is exposed using the first exposure mask 16, and the exposed first photosensitive film 15 is developed to form the first photosensitive film pattern 15 ′. At this time, the hard mask layer is usually composed of a double layer of an amorphous carbon layer and an inorganic hard mask layer.

도 1c 및 도 1d를 참조하면, 상기 제1 감광막 패턴(15')을 식각마스크로 하부 제1 반사방지막(14)을 식각하여 제1 반사방지막 패턴(14')을 형성한 후, 상기 제1 반사방지막 패턴(14')을 식각마스크로 제1 하드마스크층(13)을 식각하여 제1 하드마스크 패턴(13')을 형성한다.1C and 1D, the first anti-reflection film 14 is etched using the first photoresist pattern 15 ′ as an etch mask to form a first anti-reflection film pattern 14 ′, and then the first anti-reflection film pattern 14 ′ is formed. The first hard mask layer 13 is etched using the anti-reflection film pattern 14 ′ as an etch mask to form the first hard mask pattern 13 ′.

도 1e 및 도 1f를 참조하면, 제1 하드마스크 패턴(13') 상부에 제2 하드마스크층(17), 제2 반사방지막(18) 및 제2 감광막(19)을 순차적으로 형성한 후, 제2 노광마스크(20)를 이용하여 상기 제1 영역과 겹치지 않도록 교번으로 전체 표면의 제2 영역을 노광하고 상기 제2 감광막(19)을 현상하여 제2 감광막 패턴(19')을 형성한다. 이때, 상기 제2 하드마스크층(17)은 제1 하드마스크층(13)과 식각선택비가 다른 물질을 사용하는 것이 바람직하다.1E and 1F, after the second hard mask layer 17, the second anti-reflection film 18, and the second photoresist film 19 are sequentially formed on the first hard mask pattern 13 ′, The second photoresist layer 19 is formed by exposing a second region of the entire surface in alternating manner so as not to overlap with the first region by using a second exposure mask 20. In this case, the second hard mask layer 17 may be formed of a material having a different etching selectivity from the first hard mask layer 13.

도 1g 및 도 1h를 참조하면, 상기 제2 감광막 패턴(19')을 식각마스크로 하부 제2 반사방지막(18)을 식각하여 제2 반사방지막 패턴(18')을 형성한 후, 상기 제2 반사방지막 패턴(18')을 식각마스크로 제2 하드마스크층(17)을 식각하여 제2 하드마스크 패턴(17')을 형성한다.1G and 1H, the second anti-reflection film 18 is etched using the second photoresist pattern 19 ′ as an etch mask to form a second anti-reflection film pattern 18 ′, and then the second anti-reflection film pattern 18 ′ is formed. The second hard mask layer 17 is etched using the anti-reflection film pattern 18 ′ as an etch mask to form the second hard mask pattern 17 ′.

도 1i를 참조하면, 제1 및 제2 하드마스크 패턴(13',17')을 식각마스크로 하부 피식각층을 식각한 후, 상기 제1 및 제2 하드마스크 패턴(13',17')을 제거하여 원하는 미세패턴을 형성한다.Referring to FIG. 1I, after etching the lower etched layer using the first and second hard mask patterns 13 ′ and 17 ′ as an etch mask, the first and second hard mask patterns 13 ′ and 17 ′ are etched. To form a desired micropattern.

그러나, 상술한 종래 기술에 따른 반도체 소자의 미세 패턴 형성 방법의 경우, 감광막, 반사방지막 및 하드마스크층에 대하여 각각 2차례 코팅 및 식각공정을 수행하여야 하므로, 공정이 복잡하여 수율이 감소되는 문제점이 있었다.However, in the aforementioned method of forming a fine pattern of a semiconductor device according to the related art, since the coating and etching processes are performed twice on the photoresist, the antireflection film, and the hard mask layer, the process is complicated and the yield is reduced. there was.

상기 문제점을 해결하기 위하여, 본 발명은 실리콘이 함유된 반사방지막을 형성한 후 O2 플라즈마 공정을 수행하여 하드마스크층의 코팅 및 식각 공정을 1회만 수행함으로써 공정을 단순화시켜 시간 및 비용을 감소시키는 반도체 소자의 제조 방법을 제공하는 것을 그 목적으로 한다.In order to solve the above problems, the present invention simplifies the process by reducing the time and cost by performing only one coating and etching of the hard mask layer by performing an O 2 plasma process after forming the anti-reflective film containing silicon. An object thereof is to provide a method for manufacturing a semiconductor device.

본 발명에 따른 반도체 소자의 제조 방법은Method for manufacturing a semiconductor device according to the present invention

(1) 반도체 기판 상부에 피식각층, 하드마스크층, 실리콘을 포함하는 제1 반사방지막 및 제1 감광막을 순차적으로 형성하는 단계;(1) sequentially forming an etched layer, a hard mask layer, a first antireflection film including silicon and a first photoresist film on the semiconductor substrate;

(2) 상기 제1 감광막을 제1 노광마스크를 이용하여 노광한 후 현상하여 제1 감광막 패턴을 형성하고, 상기 제1 감광막 패턴을 식각마스크로 상기 제1 반사방지막을 식각하여 제1 반사방지막 패턴을 형성하는 단계;(2) exposing the first photoresist film using a first exposure mask and then developing it to form a first photoresist pattern, and etching the first antireflection film by using the first photoresist pattern as an etch mask to form a first antireflection film pattern. Forming a;

(3) 상기 제1 반사방지막 패턴에 02 플라즈마를 처리하는 단계;(3) treating the first anti-reflection film pattern with a 0 2 plasma;

(4) 상기 결과물 상부에 제2 반사방지막 및 제2 감광막을 순차적으로 형성하고, 제2 노광마스크를 이용하여 제1 감광막 패턴과 겹치지 않는 제2 감광막 패턴을 형성하는 단계;(4) sequentially forming a second anti-reflection film and a second photoresist film on the resultant, and forming a second photoresist pattern that does not overlap the first photoresist pattern using a second exposure mask;

(5) 상기 제2 감광막 패턴을 식각마스크로 제2 반사방지막을 식각한 후 상기 제2 감광막 패턴을 제거하여 제2 반사방지막 패턴을 형성하는 단계; 및(5) forming a second anti-reflection film pattern by etching the second anti-reflection film using the second photoresist pattern as an etching mask and then removing the second photoresist pattern; And

(6) 상기 제1 및 제2 반사방지막 패턴을 식각마스크로 상기 하드마스크층을 식각하여 하드마스크 패턴을 형성한 후, 상기 하드마스크 패턴을 식각마스크로 상기 피식각층을 식각하여 피식각층 패턴을 형성하는 단계를 포함한다.(6) etching the hard mask layer using the first and second anti-reflection film patterns as an etch mask to form a hard mask pattern, and then etching the etching target layer using the hard mask pattern as an etch mask to form an etched layer pattern. It includes a step.

본 발명에서는 소정 함량의 실리콘을 함유하는 반사방지막 조성물을 사용하여 제1 반사방지막 패턴을 형성하고, 이후 02 플라즈마를 처리하여 제1 반사방지막 패턴 내의 실리콘을 산화시킴으로써 후속 식각 공정에서 상기 제1 반사방지막 패턴이 식각되지 않도록 하여 공정 단계를 줄일 수 있다는 것을 특징으로 한다. 상기에서, 실리콘은 전체 반사방지막 조성물에 대해 30 내지 40 중량%의 함량으로 포함된다. 또한, 상기 제2 반사방지막 조성물은 상기 제1 반사방지막 조성물과 동일하거나 또는 상이한 물질로 형성해도 무방하며, 통상적으로 사용되는 임의의 반사방 지막 조성물을 제한없이 사용할 수 있다. 이때, '상이한 물질'이란 제1 반사방지막 조성물과는 달리 실리콘을 함유하지 않는 임의의 반사방지막 조성물을 의미하는 것으로서, 특정한 반사방지막 조성물에 한정되는 것은 아니다.In the present invention, the first antireflection film pattern is formed using an antireflection film composition containing a predetermined amount of silicon, and then the 0 2 plasma is treated to oxidize the silicon in the first antireflection film pattern, thereby performing the first reflection in a subsequent etching process. It is possible to reduce the process step by preventing the protective film pattern is etched. In the above, the silicon is included in an amount of 30 to 40% by weight based on the total antireflective coating composition. In addition, the second anti-reflective coating composition may be formed of the same or different material as the first anti-reflective coating composition, and any conventional anti-reflective coating composition may be used without limitation. In this case, 'different material' refers to any antireflection film composition that does not contain silicon, unlike the first antireflection film composition, and is not limited to a specific antireflection film composition.

한편, 실리콘을 함유하는 상기 반사방지막 조성물로는 종래의 유기 반사방지막 조성물과 마찬가지로 가교 결합이 이루어지도록 설계된 폴리머, 노광 광원의 파장대에서 큰 흡광도를 갖는 광흡수제 및 열산발생제를 포함하는 조성물이 제한없이 사용될 수 있다. 이러한 실리콘-함유 반사방지막 조성물은 가교 반응을 활성화시키기 위해 열처리시 가교가 될 수 있는 가교제를 더 함유해도 무방하다.On the other hand, the anti-reflective coating composition containing silicon, like the conventional organic anti-reflective coating composition, polymers designed to be cross-linked, a composition comprising a light absorbing agent and a thermal acid generator having a large absorbance in the wavelength range of the exposure light source without limitation Can be used. Such a silicon-containing antireflective coating composition may further contain a crosslinking agent that can be crosslinked during heat treatment to activate a crosslinking reaction.

이하, 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

도 2a 내지 도 2i는 본 발명에 따른 반도체 소자의 미세 패턴 형성 방법을 도시한 단면도들이다.2A to 2I are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the present invention.

도 2a 및 도 2b를 참조하면, 반도체 기판(110) 상부에 피식각층(120), 하드마스크층(130), 제1 반사방지막(140) 및 제1 감광막(150)을 순차적으로 형성한 후, 제1 노광마스크(160)를 이용하여 전체 표면의 제1 영역을 노광하고 상기 제1 감광막(150)을 현상하여 제1 감광막 패턴(150')을 형성한다. 이때, 제1 반사방지막(140)은 30 내지 40 중량%의 실리콘이 함유된 물질로 형성하는 것이 바람직하며, 또한 상기 하드마스크층(130)은 비정질 탄소층 및 무기계 하드마스크층의 2중층으로 구성되어 있는 것이 바람직하다. 아울러, 상기 노광원으로는 400 nm 이하의 파장을 가지는 모든 광원, 구체적으로는 ArF (193 nm), KrF (248 nm), EUV (Extreme Ultra Violet), VUV (Vacuum Ultra Violet, 157 nm), E-빔, X-선 및 이온빔으로 구 성된 군으로부터 선택되는 광원이 제한없이 사용될 수 있으며, 노광 공정은 사용되는 감광제의 종류에 따라 다르지만 통상적으로 70 내지 150 mJ/㎠, 바람직하게는 100 mJ/㎠의 노광에너지로 수행되는 것이 바람직하다. 이중에서 노광원으로는 ArF, KrF 또는 VUV를 사용하는 것이 바람직하고, ArF를 사용하는 것이 더욱 바람직하다.2A and 2B, after the etched layer 120, the hard mask layer 130, the first anti-reflection film 140, and the first photoresist film 150 are sequentially formed on the semiconductor substrate 110, The first region of the entire surface is exposed using the first exposure mask 160, and the first photoresist film 150 is developed to form a first photoresist pattern 150 ′. In this case, the first anti-reflection film 140 is preferably formed of a material containing 30 to 40% by weight of silicon, and the hard mask layer 130 is composed of a double layer of an amorphous carbon layer and an inorganic hard mask layer. It is preferable that it is done. In addition, all the light sources having a wavelength of 400 nm or less, specifically ArF (193 nm), KrF (248 nm), EUV (Extreme Ultra Violet), VUV (Vacuum Ultra Violet, 157 nm), E A light source selected from the group consisting of -beams, X-rays and ion beams can be used without limitation, and the exposure process is usually 70 to 150 mJ / cm 2, preferably 100 mJ / cm 2, depending on the type of photosensitive agent used. It is preferably carried out with an exposure energy of. Among them, it is preferable to use ArF, KrF or VUV as the exposure source, and more preferably ArF.

도 2c 및 도 2d를 참조하면, 제1 감광막 패턴(150')을 마스크로 제1 반사방지막(140)을 식각한 후 제1 감광막 패턴(150')을 제거하여 제1 반사방지막 패턴(140')을 형성한다. 이후, 02 플라즈마 처리 공정을 수행하여 제1 반사방지막 패턴(140') 내의 실리콘을 산화시킴으로써, SiO2로 변형된 제1 반사방지막 패턴(145)을 형성한다.2C and 2D, after etching the first anti-reflection film 140 using the first photoresist pattern 150 ′ as a mask, the first anti-reflection film pattern 150 ′ is removed to remove the first anti-reflection film pattern 140 ′. ). Thereafter, the first anti-reflection film pattern 145 transformed into SiO 2 is formed by oxidizing silicon in the first anti-reflection film pattern 140 ′ by performing a 0 2 plasma treatment process.

도 2e 및 도 2f를 참조하면, 상기 SiO2-포함 제1 반사방지막 패턴(145)을 포함하는 전체 표면 상부에 제2 반사방지막(180) 및 제2 감광막(190)을 형성한 후, 제2 노광마스크(200)를 이용하여 제1 반사방지막 패턴(140)과 겹치지 않도록 상호 교번적으로 전체 표면의 제2 영역을 노광 후 현상하여 제2 감광막 패턴(190')을 형성한다. 이때, 상기 제2 반사방지막(180)은 제1 반사방지막(140)과는 달리 실리콘을 함유하는 반사방지막 조성물을 사용하지 않아도 무방하며, 통상의 반사방지막 조성물을 제한없이 사용할 수 있다. 한편, 상기 제1 및 제2 감광막은 통상의 감광제 조성물을 제한없이 사용해도 무방하다.2E and 2F, after forming the second anti-reflection film 180 and the second photoresist layer 190 on the entire surface including the SiO 2 -containing first anti-reflection film pattern 145, the second The second photoresist layer pattern 190 ′ is formed by exposing and developing the second region of the entire surface alternately so as not to overlap the first antireflection layer pattern 140 using the exposure mask 200. In this case, unlike the first anti-reflection film 140, the second anti-reflection film 180 may not use an anti-reflection film composition containing silicon, and a conventional anti-reflection film composition may be used without limitation. In addition, the said 1st and 2nd photosensitive film may use a normal photosensitive agent composition without a restriction | limiting.

도 2g 및 도 2h를 참조하면, 제2 감광막 패턴(190')을 마스크로 상기 제2 반 사방지막(180)을 식각한 후 제2 감광막 패턴(190')을 제거하여 제2 반사방지막 패턴(180')을 형성한다. 이때, 상기 제1 반사방지막 패턴(145)은 O2 플라즈마 처리에 의해 내부에 포함된 실리콘이 SiO2로 변형되기 때문에 식각 공정시 제거되지 않고 남아 있게 된다. 이후, 상기 제1 및 제2 반사방지막 패턴(145,180')을 마스크로 하드마스크층(130)을 식각한 후, 제1 및 제2 반사방지막 패턴(145,180')을 제거하여 하드마스크 패턴(130')을 형성한다.2G and 2H, the second anti-reflection film 180 is etched using the second photoresist pattern 190 ′ as a mask, and then the second anti-reflection film pattern 190 ′ is removed to remove the second anti-reflection film pattern ( 180 '). At this time, the first anti-reflection film pattern 145 is not removed during the etching process because the silicon contained therein is deformed into SiO 2 by O 2 plasma treatment. Thereafter, the hard mask layer 130 is etched using the first and second anti-reflection film patterns 145 and 180 ′ as a mask, and then the hard mask pattern 130 ′ is removed by removing the first and second anti-reflection film patterns 145 and 180 ′. ).

도 2i를 참조하면, 하드마스크 패턴(130')을 마스크로 피식각층(120)을 식각한 후 하드마스크 패턴(130')을 제거하여 원하는 미세패턴(120')을 형성한다.Referring to FIG. 2I, the etching target layer 120 is etched using the hard mask pattern 130 ′ as a mask to remove the hard mask pattern 130 ′ to form a desired fine pattern 120 ′.

본 발명에 따른 반도체 소자의 제조 방법은 실리콘이 함유된 반사방지막을 형성한 후 02 플라즈마 공정을 수행함으로써 하드마스크층의 코팅 및 식각 공정을 1회만 수행하도록 하여 공정을 단순화시키며 시간 및 비용을 감소시키는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention simplifies the process by reducing the time and cost by performing the coating and etching of the hard mask layer only once by forming the anti-reflective film containing silicon and then performing a 0 2 plasma process. It is effective to let.

Claims (7)

(1) 반도체 기판 상부에 피식각층, 하드마스크층, 실리콘을 포함하는 제1 반사방지막 및 제1 감광막을 순차적으로 형성하는 단계;(1) sequentially forming an etched layer, a hard mask layer, a first antireflection film including silicon and a first photoresist film on the semiconductor substrate; (2) 상기 제1 감광막을 제1 노광마스크를 이용하여 노광한 후 현상하여 제1 감광막 패턴을 형성하고, 상기 제1 감광막 패턴을 마스크로 상기 제1 반사방지막을 식각하여 제1 반사방지막 패턴을 형성하는 단계;(2) the first photoresist film is exposed using a first exposure mask and then developed to form a first photoresist pattern, and the first antireflection film is etched using the first photoresist pattern as a mask to form a first antireflection film pattern. Forming; (3) 상기 제1 반사방지막 패턴에 02 플라즈마를 처리하는 단계;(3) treating the first anti-reflection film pattern with a 0 2 plasma; (4) 상기 결과물 상부에 제2 반사방지막 및 제2 감광막을 순차적으로 형성하고, 제2 노광마스크를 이용하여 제1 감광막 패턴과 겹치지 않는 제2 감광막 패턴을 형성하는 단계;(4) sequentially forming a second anti-reflection film and a second photoresist film on the resultant, and forming a second photoresist pattern that does not overlap the first photoresist pattern using a second exposure mask; (5) 상기 제2 감광막 패턴을 식각마스크로 제2 반사방지막을 식각한 후 상기 제2 감광막 패턴을 제거하여 제2 반사방지막 패턴을 형성하는 단계; 및(5) forming a second anti-reflection film pattern by etching the second anti-reflection film using the second photoresist pattern as an etching mask and then removing the second photoresist pattern; And (6) 상기 제1 및 제2 반사방지막 패턴을 식각마스크로 상기 하드마스크층을 식각하여 하드마스크 패턴을 형성한 후, 상기 하드마스크 패턴을 식각마스크로 상기 피식각층을 식각하여 피식각층 패턴을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.(6) etching the hard mask layer using the first and second anti-reflection film patterns as an etch mask to form a hard mask pattern, and then etching the etching target layer using the hard mask pattern as an etch mask to form an etched layer pattern. Method for manufacturing a semiconductor device comprising the step. 제1항에 있어서,The method of claim 1, 상기 제1 반사방지막은 30 내지 40 중량% 함량의 실리콘을 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The first anti-reflection film is a semiconductor device manufacturing method, characterized in that containing 30 to 40% by weight of silicon. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2 반사방지막은 상기 제1 반사방지막과 동일하거나 또는 상이한 물질로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.And the second anti-reflection film is formed of the same or different material as the first anti-reflection film. 제1항에 있어서,The method of claim 1, 상기 노광원은 ArF (193 nm), KrF (248 nm), EUV (Extreme Ultra Violet), VUV (Vacuum Ultra Violet, 157 nm), E-빔, X-선 및 이온빔으로 구성된 군으로부터 선택되는 것을 특징으로 하는 반도체 소자의 제조 방법.The exposure source is selected from the group consisting of ArF (193 nm), KrF (248 nm), EUV (Extreme Ultra Violet), VUV (Vacuum Ultra Violet, 157 nm), E-beam, X-ray and ion beam The manufacturing method of the semiconductor element made into. 제1항에 있어서,The method of claim 1, 상기 하드마스크층은 피식각층 상부에 비정질 탄소층 및 무기계 하드마스크층의 2중층으로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The hard mask layer is a semiconductor device manufacturing method, characterized in that formed on the upper layer of the etching layer of the amorphous carbon layer and the inorganic hard mask layer. 제1항에 있어서,The method of claim 1, 상기 제1 반사방지막 패턴 및 제2 반사방지막 패턴은 상호 교번적으로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The first anti-reflection film pattern and the second anti-reflection film pattern is a method of manufacturing a semiconductor device, characterized in that formed alternately with each other. (1) 반도체 기판 상부에 피식각층, 실리콘을 포함하는 제1 반사방지막 및 제1 감광막을 순차적으로 형성하는 단계;(1) sequentially forming an etched layer, a first anti-reflection film containing silicon and a first photoresist film on the semiconductor substrate; (2) 상기 제1 감광막을 제1 노광마스크를 이용하여 노광한 후 현상하여 제1 감광막 패턴을 형성하고, 상기 제1 감광막 패턴을 마스크로 상기 제1 반사방지막을 식각하여 제1 반사방지막 패턴을 형성하는 단계;(2) the first photoresist film is exposed using a first exposure mask and then developed to form a first photoresist pattern, and the first antireflection film is etched using the first photoresist pattern as a mask to form a first antireflection film pattern. Forming; (3) 상기 제1 반사방지막 패턴에 02 플라즈마를 처리하는 단계;(3) treating the first anti-reflection film pattern with a 0 2 plasma; (4) 상기 결과물 상부에 제2 반사방지막 및 제2 감광막을 순차적으로 형성한 후, 제2 노광마스크를 이용하여 제1 감광막 패턴과 겹치지 않는 제2 감광막 패턴을 형성하는 단계;(4) sequentially forming a second anti-reflection film and a second photoresist film on the resultant, and then forming a second photoresist pattern that does not overlap the first photoresist pattern using a second exposure mask; (5) 상기 제2 감광막 패턴을 식각마스크로 제2 반사방지막을 식각한 후 상기 제2 감광막 패턴을 제거하여 제2 반사방지막 패턴을 형성하는 단계; 및(5) forming a second anti-reflection film pattern by etching the second anti-reflection film using the second photoresist pattern as an etching mask and then removing the second photoresist pattern; And (6) 상기 제1 및 제2 반사방지막 패턴을 식각마스크로 상기 피식각층을 식각하여 피식각층 패턴을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.And (6) forming the etched layer pattern by etching the etched layer using the first and second anti-reflection film patterns as an etch mask.
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CN103681251B (en) * 2012-09-20 2018-02-09 中国科学院微电子研究所 Hybrid optical and electronic beam photetching process
CN104051241A (en) * 2013-03-11 2014-09-17 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device
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