KR20030070658A - A method for forming pattern of semiconductor device - Google Patents
A method for forming pattern of semiconductor device Download PDFInfo
- Publication number
- KR20030070658A KR20030070658A KR1020020010133A KR20020010133A KR20030070658A KR 20030070658 A KR20030070658 A KR 20030070658A KR 1020020010133 A KR1020020010133 A KR 1020020010133A KR 20020010133 A KR20020010133 A KR 20020010133A KR 20030070658 A KR20030070658 A KR 20030070658A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- etching
- photoresist
- forming
- hard mask
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims description 53
- 230000008569 process Effects 0.000 claims description 16
- ODIGIKRIUKFKHP-UHFFFAOYSA-N (n-propan-2-yloxycarbonylanilino) acetate Chemical compound CC(C)OC(=O)N(OC(C)=O)C1=CC=CC=C1 ODIGIKRIUKFKHP-UHFFFAOYSA-N 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000007261 regionalization Effects 0.000 claims description 2
- 206010010071 Coma Diseases 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 6
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 24
- 230000018109 developmental process Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000003821 2-(trimethylsilyl)ethoxymethyl group Chemical group [H]C([H])([H])[Si](C([H])([H])[H])(C([H])([H])[H])C([H])([H])C(OC([H])([H])[*])([H])[H] 0.000 description 1
- -1 NH 3 Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- FPYJFEHAWHCUMM-UHFFFAOYSA-N maleic anhydride Chemical compound O=C1OC(=O)C=C1 FPYJFEHAWHCUMM-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
본 발명은 반도체 소자의 미세 패턴 형성방법에 관한 것으로, 특히 ArF 전용 감광막 패턴을 사용한 식각 공정시 감광막 변형을 방지할 수 있는 반도체 소자의 미세 패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device capable of preventing photosensitive film deformation during an etching process using an ArF-specific photosensitive film pattern.
반도체 소자의 제조에 있어서 패턴 크기가 작아짐에 따라 더욱 미세한 감광막 마스크 형성이 필요하다. 반도체 소자의 최소 패턴 크기를 0.10㎛이하로 제조시 KrF DUV(λ=248nm) 파장을 사용하여 미세 패턴을 형성하기가 매우 어려워 KrF 파장보다 단파장인 ArF DUV(λ=193nm)을 사용한다.As the pattern size becomes smaller in the manufacture of semiconductor devices, finer photoresist mask formation is required. When manufacturing the minimum pattern size of the semiconductor device to 0.10㎛ or less, it is very difficult to form a fine pattern using the KrF DUV (λ = 248nm) wavelength, ArF DUV (λ = 193nm) shorter than the KrF wavelength is used.
그러나 ArF 파장으로 감광막 마스크에 노광 및 현상을 통해 마스크 패턴을 형성하기 위해서는 ArF 파장에 반응하는 ArF 전용 감광막을 사용하여야 한다.However, in order to form a mask pattern through exposure and development to the photoresist mask at the ArF wavelength, an ArF photoresist that responds to the ArF wavelength should be used.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 미세 패턴 형성방법에 대하여 설명하기로 한다.Hereinafter, a method of forming a fine pattern of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1b는 종래의 반도체 소자의 미세 패턴 형성방법을 나타낸 공정 단면도이고, 도 2a 내지 도 2b는 도 1a 내지 도 1b의 SEM 평면도이다.1A to 1B are cross-sectional views illustrating a method of forming a fine pattern of a conventional semiconductor device, and FIGS. 2A to 2B are plan views of SEMs of FIGS. 1A to 1B.
도 1a 및 도 2a에 도시한 바와 같이 반도체 기판(도면에 도시하지 않았음)상에 피식각층(11)을 형성한 후, 상기 피식각층(11)상에 반사방지막(12)을 형성한다. 이때, 상기 피식각층(11)은 절연막 또는 금속층이다.As shown in FIGS. 1A and 2A, after forming an etched layer 11 on a semiconductor substrate (not shown), an anti-reflection film 12 is formed on the etched layer 11. In this case, the etched layer 11 is an insulating film or a metal layer.
그리고 상기 반사방지막(12)상에 ArF 전용 감광막(13)을 증착한 후, 노광 및 현상공정을 이용하여 선택적으로 패터닝한다.After the ArF photosensitive film 13 is deposited on the anti-reflection film 12, it is selectively patterned using an exposure and development process.
도 1b 및 도 2b에 도시한 바와 같이 상기 패터닝된 감광막(13)을 마스크로 하여 CxFy, CxHyFz, SxFy등 F가 포함된 절연막 식각가스 또는 Cl2, BCl3, SxFy, HBr 등 금속 식각 가스와 O2가스를 혼합하여 상기 반사방지막(12)을 식각한다.Figure 1b and described above with the patterned photoresist 13 as a mask, C x F y, as shown in Figure 2b, C x H y F z, S x F y, such as the F includes the insulating layer etching gas, or Cl 2, BCl The anti-reflection film 12 is etched by mixing a metal etching gas such as 3 , S x F y , HBr, and O 2 gas.
그리고 상기 패터닝된 감광막(13) 및 반사방지막(12)을 마스크로 하여 CxFy,CxHyFz, SxFy등 F가 포함된 절연막 식각가스 또는 Cl2, BCl3, SxFy, HBr 등 금속 식각 가스를 이용하여 상기 피식각층(11)을 선택적으로 식각하여 미세 패턴을 형성한다.And using the patterned photosensitive film 13 and the anti-reflection film 12 as a mask, an insulating film etching gas containing F, such as C x F y , C x H y F z , S x F y or Cl 2 , BCl 3 , S The etching target layer 11 is selectively etched using a metal etching gas such as x F y and HBr to form a fine pattern.
그러나 상기와 같은 종래의 반도체 소자의 미세 패턴 형성방법에 있어서는 다음과 같은 문제점이 있었다.However, the conventional method of forming a fine pattern of a semiconductor device as described above has the following problems.
ArF 전용 감광막은 KrF 전용 감광막과는 달리 식각 공정시 내성이 약하므로 마스크 패턴이 모양을 유지하지 못하고 변형되어 ArF 전용 감광막을 마스크로 하여 식각공정을 진행할 때 피식각층의 식각된 패턴 모양이 도 1b의 A 및 도 2b와 같이 변형된다.Unlike the KrF-specific photoresist film, the ArF-specific photoresist film is weak in the etching process, so the mask pattern does not maintain its shape and is deformed. A and as shown in Figure 2b.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 TLP(Tri-Level Resist) 구조를 사용하여 ArF 전용 감광막을 사용한 미세 패턴 형성시 감광막의 패턴 모양이 변형되는 방지할 수 있는 반도체 소자의 미세 패턴 형성방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems, a fine pattern of the semiconductor device that can prevent the pattern shape of the photosensitive film is deformed when forming a fine pattern using an ArF photosensitive film using a TLP (Tri-Level Resist) structure The purpose is to provide a formation method.
도 1a 내지 도 1b는 종래의 반도체 소자의 미세 패턴 형성방법을 나타낸 공정 단면도1A to 1B are cross-sectional views illustrating a method of forming a fine pattern of a conventional semiconductor device.
도 2a 내지 도 2b는 도 1a 내지 도 1b의 SEM 평면도2A-2B are SEM top views of FIGS. 1A-1B.
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 반도체 소자의 미세 패턴 형성방법을 나타낸 공정 단면도3A to 3D are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 피식각층 102 : 제 1 감광막101: etching target layer 102: first photosensitive film
103 : 하드 마스크용 산화막 104 : 반사방지막103: oxide film for hard mask 104: antireflection film
105 : 제 2 감광막105: second photosensitive film
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 미세 패턴 형성방법은 피식각층상에 제 1 감광막을 형성한 후, 상기 제 1 감광막상에 하드 마스크용 절연막을 형성하는 단계와, 상기 하드 마스크용 절연막상에 반사방지막을 형성한 후, 상기 반사방지막상에 선택적으로 ArF 전용 제 2 감광막 패턴을 형성하는 단계와, 상기 제 2 감광막 패턴을 마스크로 하여 상기 반사방지막 및 하드 마스크용 절연막을 선택적으로 식각함과 동시에 상기 제 2 감광막 패턴이 제거되는 단계와,상기 하드 마스크용 절연막을 마스크로 하여 상기 제 1 감광막을 선택적으로 식각하는 단계와, 상기 식각된 제 1 감광막을 마스크로 하여 상기 피식각층을 선택적으로 식각하는 단계와, 상기 하드 마스크용 절연막과 제 1 감광막을 제거하여 미세 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a fine pattern of a semiconductor device according to the present invention includes forming a first photoresist film on an etched layer, and then forming an insulating film for a hard mask on the first photoresist film; Forming an antireflection film on the antireflection film, and selectively forming an ArF-only second photoresist pattern on the antireflection film, and selectively selecting the antireflection film and the hard mask insulation film using the second photoresist pattern as a mask Etching and simultaneously removing the second photoresist layer pattern; selectively etching the first photoresist layer using the hard mask insulating layer as a mask; and using the etched first photoresist layer as a mask. Selectively etching, and removing the hard mask insulating film and the first photosensitive film to form a fine pattern. Characterized in that it also.
또한, 상기 제 1 감광막은 i-line 노광용 감광막, DUV 노광용 감광막, ArF 노광용 감광막중 어느 하나를 사용하는 것이 바람직하다.In addition, it is preferable to use any one of the photosensitive film for i-line exposure, the photosensitive film for DUV exposure, and the ArF exposure photosensitive film as said 1st photosensitive film.
또한, 상기 하드 마스크용 절연막의 두께는 50∼1000Å이고, 증착 온도는 300∼350℃인 것이 바람직하다.In addition, it is preferable that the thickness of the said insulating film for hard masks is 50-1000 GPa, and deposition temperature is 300-350 degreeC.
또한, 상기 하드 마스크용 절연막은 PE-TEOS, APL, SiON, Al2O3중 어느 하나인 것이 바람직하다.In addition, the hard mask insulating film is preferably any one of PE-TEOS, APL, SiON, Al 2 O 3 .
또한, 상기 제 2 감광막은 아실레이트(Acylate)계 및 COMA계이며, 그 두께는 0.3∼0.6㎛인 것이 바람직하다.In addition, it is preferable that the said 2nd photosensitive film is an acylate type | system | group and a COMA type | system | group, and the thickness is 0.3-0.6 micrometer.
또한, 상기 반사방지막 및 하드 마스크용 절연막 식각공정은 CF4/O2/Ar 가스, CHF3/O2/Ar 가스를 사용하여 수직의 식각 단면을 갖도록 진행하는 것이 바람직하다.In addition, the anti-reflection film and the hard mask insulating film etching process may be performed to have a vertical etching cross section using CF 4 / O 2 / Ar gas, CHF 3 / O 2 / Ar gas.
또한, 상기 제 1 감광막 식각 공정시 사용되는 식각가스는 제 1 식각 가스로 O2, NO2, NO, CO, CO2, SO2가스를 이용하고, 제 2 식각 가스로 NH3, N2H2, CH4, C2H2, C2H4가스를 이용하며, 제 3 식각 가스로 N2그리고 제 4 식각 가스로 He, Ne, Ar, Xe를 이용하는 것이 바람직하다.In addition, the etching gas used in the first photoresist film etching process uses O 2 , NO 2 , NO, CO, CO 2 , SO 2 gas as the first etching gas, and NH 3 , N 2 H as the second etching gas. 2 , CH 4 , C 2 H 2 , C 2 H 4 gas is used, and it is preferable to use N 2 as the third etching gas and He, Ne, Ar, Xe as the fourth etching gas.
또한, 상기 제 1 감광막 제거는 O2, NO2, NO, CO, CO2, SO2를 이용한 등방성 건식식각 공정을 이용하는 것이 바람직하다.In addition, the first photosensitive film is removed, it is preferable to use an isotropic dry etching process using O 2 , NO 2 , NO, CO, CO 2 , SO 2 .
또한, 상기 제 1 감광막 제거시 H2SO4: H2O2:DI의 혼합용액을 사용하는 것이 바람직하다.In addition, it is preferable to use a mixed solution of H 2 SO 4 : H 2 O 2 : DI when removing the first photosensitive film.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 미세 패턴 형성방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method for forming a fine pattern of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 반도체 소자의 미세 패턴 형성방법을 나타낸 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
도 3a에 도시한 바와 같이 반도체 기판(도면에 도시하지 않았음)상에 피식각층(101)을 형성한 후, 상기 피식각층(101)상에 제 1 감광막(102)을 증착한다. 이때, 상기 제 1 감광막(102)은 i-line 노광용 감광막, DUV 노광용 감광막, ArF 노광용 감광막중 어느 하나를 사용한다.As shown in FIG. 3A, after the etching target layer 101 is formed on a semiconductor substrate (not shown), a first photosensitive film 102 is deposited on the etching target layer 101. In this case, the first photoresist layer 102 may be any one of an i-line exposure photoresist film, a DUV exposure photoresist film, and an ArF exposure photoresist film.
그리고 상기 제 1 감광막(102)상에 하드 마스크용 산화막(103)을 증착하고, 상기 하드 마스크용 산화막(103)상에 반사방지막(104)을 형성한다. 이때, 상기 하드 마스크용 산화막(103)은 PE-TEOS(Plasma Enhanced-Tetra Ethyl Ortho Silicate), APL(Advanced Planarization Layer), SiON 중 어느 하나이고, 증착온도는 300∼350℃ 이하의 저온이며, 그 두께는 50∼1000Å이다. 한편, 상기 하드 마스크용 산화막(103)은 Al2O3을 ALD(Atomic Layer Deposition) 방법으로 300∼350℃ 이하로 증착한다.An oxide film 103 for a hard mask is deposited on the first photoresist film 102, and an antireflection film 104 is formed on the hard mask oxide film 103. In this case, the hard mask oxide film 103 is any one of Plasma Enhanced-Tetra Ethyl Ortho Silicate (PE-TEOS), Advanced Planarization Layer (APL), and SiON, and the deposition temperature is a low temperature of 300 to 350 ° C or lower. The thickness is 50-1000 mm. On the other hand, the hard film oxide film 103 is deposited Al 2 O 3 to 300 ~ 350 ℃ or less by the ALD (Atomic Layer Deposition) method.
이어, 상기 반사방지막(104)상에 ArF 전용 제 2 감광막(105)을 증착한 후, 노광 및 현상공정을 이용하여 상기 제 2 감광막(105)을 선택적으로 패터닝한다. 이때, 상기 제 2 감광막(105)은 아실레이트(Acylate)계 또는 COMA(Cyclo-Olefin Maleic Anhydride)계이며, 그 두께는 상기 제 1 감광막(102)의 두께보다 1/3이하 즉, 0.3∼0.6㎛이다.Subsequently, an ArF-only second photosensitive film 105 is deposited on the antireflection film 104, and then the second photosensitive film 105 is selectively patterned using an exposure and development process. In this case, the second photosensitive film 105 is an acylate-based or cyclo-oleic maleic anhydride (COMA) -based, the thickness is 1/3 or less than the thickness of the first photosensitive film 102, that is, 0.3 to 0.6 [Mu] m.
한편, 상기 패터닝된 제 2 감광막(105)에 100∼250℃ 사이에서 열처리 공정을 실하여 상기 제 2 감광막(105) 자체를 단단한 구조로 바꿔 후 공정의 식각 공정시 변형을 방지한다.On the other hand, the patterned second photosensitive film 105 is subjected to a heat treatment process between 100 to 250 ° C. to change the second photosensitive film 105 itself into a rigid structure to prevent deformation during the etching process of the subsequent process.
도 3b에 도시한 바와 같이 상기 패터닝된 제 2 감광막(105)을 마스크로 이용하여 상기 반사방지막(104)을 식각한 후, 상기 하드 마스크용 산화막(103)을 식각한다. 이때, 상기 반사방지막(104) 및 하드 마스크용 산화막(103) 식각 공정은 CF4/O2/Ar 가스, CHF3/O2/Ar 가스를 사용하여 수직의 식각 단면을 갖도록 진행한다.As shown in FIG. 3B, the anti-reflection film 104 is etched using the patterned second photoresist film 105 as a mask, followed by etching the hard mask oxide film 103. At this time, the etching process of the anti-reflection film 104 and the oxide film 103 for hard mask proceeds to have a vertical etching cross section using CF 4 / O 2 / Ar gas, CHF 3 / O 2 / Ar gas.
여기서, 상기 패터닝된 제 2 감광막(105)은 제거된다.Here, the patterned second photosensitive film 105 is removed.
즉, 상기 ArF 전용 제 2 감광막(105)을 마스크로 하여 식각 공정 진행시 식각 시간이 길지 않으므로 상기 제 2 감광막(105)은 변형되지 않는다.That is, since the etching time is not long during the etching process using the ArF-only second photosensitive film 105 as a mask, the second photosensitive film 105 is not deformed.
한편, 상기 반사방지막(104) 및 하드 마스크용 산화막(103) 식각시 식각 기구에서 반도체 기판의 온도를 20℃이하로 낮추고, 압력을 30mT 이하로 낮추어 제 2 감광막(105)의 변형을 방지한다. 그리고 상기 식각 기구내의 바이어스 파워를 1400W 이하로 낮춘다.Meanwhile, during the etching of the anti-reflection film 104 and the hard mask oxide film 103, the etching mechanism lowers the temperature of the semiconductor substrate to 20 ° C. or lower, and lowers the pressure to 30 mT or less to prevent deformation of the second photoresist layer 105. The bias power in the etching apparatus is lowered to 1400W or less.
도 3c에 도시한 바와 같이 상기 하드 마스크용 산화막(103)을 마스크로 이용하여 상기 제 1 감광막(102)을 선택적으로 식각한다. 이때, 상기 제 1 감광막(102) 식각시 상기 하드 마스크용 산화막(103)과 고선택적 식각이 가능하도록 제 1 식각 가스로 O2, NO2, NO, CO, CO2, SO2등 O를 포함한 가스를 이용하고, 식각 단면 개선 등을 위해 제 2 식각 가스로 NH3, N2H2, CH4, C2H2, C2H4등 수소를 포함하는 가스를 이용한다. 그리고 플라즈마의 균일도를 향상시키고 식각 단면을 조절하거나 식각 속도를 조절하기 위해 제 3 식각 가스로 N2를 사용하고, 플라즈마의 균일도를 향상시키고 식각 단면을 조절하거나 식각 속도를 조절하기 위해 불활성 가스인 He, Ne, Ar, Xe 등의 제 4 식각 가스를 이용한다.As shown in FIG. 3C, the first photosensitive layer 102 is selectively etched using the hard mask oxide layer 103 as a mask. In this case, when etching the first photoresist layer 102, the first etching gas may include O 2 , NO 2 , NO, CO, CO 2 , SO 2, and the like as the first etching gas to enable highly selective etching with the hard mask oxide layer 103. Gas is used, and a gas containing hydrogen, such as NH 3 , N 2 H 2 , CH 4 , C 2 H 2 , C 2 H 4 , is used as the second etching gas for etching cross-sectional improvement. In addition, N 2 is used as the third etching gas to improve the uniformity of the plasma, control the etching cross-section, or control the etching rate, and He, an inert gas, is used to improve the uniformity of the plasma, to control the etching cross-section, or to control the etching rate. And a fourth etching gas such as Ne, Ar, or Xe.
도 3d에 도시한 바와 같이 상기 식각된 제 1 감광막(102)을 마스크로 이용하여 상기 피식각층(101)을 선택적으로 식각한 후, 상기 하드 마스크용 산화막(103)과 제 1 감광막(102)을 제거하여 미세 패턴을 형성한다.As shown in FIG. 3D, the etched layer 101 is selectively etched using the etched first photoresist layer 102 as a mask, and then the oxide film 103 for hard mask 103 and the first photoresist layer 102 are To form a fine pattern.
이때, 상기 제 1 감광막(102) 제거는 O2, NO2, NO, CO, CO2, SO2등 O를 포함한 가스를 이용하여 등방성 건식식각 공정을 한다.At this time, the first photosensitive film 102 is removed isotropic dry etching process using a gas containing O, such as O 2 , NO 2 , NO, CO, CO 2 , SO 2 .
또는 상기 제 1 감광막(102) 제거시 H2SO4: H2O2:DI의 혼합용액을 사용한다.Alternatively, when the first photosensitive layer 102 is removed, a mixed solution of H 2 SO 4 : H 2 O 2 : DI is used.
이상에서 설명한 바와 같이 본 발명의 반도체 소자의 미세 패턴 형성방법에 의하면, TLR 구조를 갖도록 마스크 패턴을 형성하므로 ArF 파장에 반응하는 ArF 전용 감광막 패턴을 형성할 수 있다.As described above, according to the method for forming a micropattern of the semiconductor device of the present invention, since a mask pattern is formed to have a TLR structure, an ArF photosensitive film pattern responding to an ArF wavelength can be formed.
즉, 종래에 ArF 파장에 반응하는 ArF 전용 감광막 사용시 발생되는 패턴의 변형을 방지하므로 패턴 형성불량에 의한 소자 특성 저하 및 수율 저하 등의 문제점을 방지할 수 있는 효과가 있다.That is, since the deformation of the pattern generated when the ArF photosensitive film is conventionally used in response to the ArF wavelength is prevented, there is an effect of preventing problems such as deterioration of device characteristics and yield due to poor pattern formation.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0010133A KR100451509B1 (en) | 2002-02-26 | 2002-02-26 | A method for forming pattern of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0010133A KR100451509B1 (en) | 2002-02-26 | 2002-02-26 | A method for forming pattern of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030070658A true KR20030070658A (en) | 2003-09-02 |
| KR100451509B1 KR100451509B1 (en) | 2004-10-06 |
Family
ID=32222598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2002-0010133A KR100451509B1 (en) | 2002-02-26 | 2002-02-26 | A method for forming pattern of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100451509B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100710085B1 (en) * | 2006-01-13 | 2007-04-20 | 세메스 주식회사 | Method of stripping a photoresist |
| KR100772801B1 (en) * | 2005-12-28 | 2007-11-01 | 주식회사 하이닉스반도체 | Method of Manufacturing Semiconductor Device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100202183B1 (en) * | 1996-10-14 | 1999-06-15 | 구본준 | Method for forming a contact hole of a semiconductor device |
| KR20000045368A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming contact hole of semiconductor device |
-
2002
- 2002-02-26 KR KR10-2002-0010133A patent/KR100451509B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772801B1 (en) * | 2005-12-28 | 2007-11-01 | 주식회사 하이닉스반도체 | Method of Manufacturing Semiconductor Device |
| KR100710085B1 (en) * | 2006-01-13 | 2007-04-20 | 세메스 주식회사 | Method of stripping a photoresist |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100451509B1 (en) | 2004-10-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20110124196A1 (en) | Method for forming fine pattern in semiconductor device | |
| KR100861212B1 (en) | Method for forming fine patterns of semiconductor devices | |
| JP2004152784A (en) | Method for manufacturing fine pattern and method for manufacturing semiconductor device | |
| CN105190840A (en) | Optically tuned hardmask for multi-patterning applications | |
| JP2009076661A (en) | Method for manufacturing semiconductor device | |
| WO2004061916B1 (en) | Method of forming a low-k dual damascene interconnect structure | |
| JP2003051495A (en) | Forming method for contact hole of semiconductor element | |
| KR100720481B1 (en) | Method for manufacturing semiconductor device | |
| JPH10199864A (en) | Method of etching antireflection film | |
| JP2001308076A (en) | Method of manufacturing semiconductor device | |
| KR100685903B1 (en) | Method for manufacturing the semiconductor device | |
| US6303477B1 (en) | Removal of organic anti-reflection coatings in integrated circuits | |
| KR100835486B1 (en) | Method for forming fine patterns of semiconductor devices | |
| CN107799402A (en) | The forming method of secondary figure | |
| KR100451509B1 (en) | A method for forming pattern of semiconductor device | |
| CN101335184A (en) | Method for forming fine pattern in semiconductor device | |
| JP2012174976A (en) | Method of forming pattern | |
| JP5164446B2 (en) | Method for forming fine pattern of semiconductor element | |
| KR20050065745A (en) | Method for fabricating patterns of shallow trench isolation | |
| US20100105207A1 (en) | Method for forming fine pattern of semiconductor device | |
| KR100851922B1 (en) | Method for fabricating semiconductor device | |
| US7199034B1 (en) | Flash memory device and method for fabricating the same | |
| US20060138085A1 (en) | Plasma etching method with reduced particles production | |
| JP2004158538A (en) | Method for manufacturing semiconductor device | |
| TWI249202B (en) | Dielectric etching method to prevent photoresist damage and bird's beak |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |