JP4535730B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP4535730B2 JP4535730B2 JP2003560978A JP2003560978A JP4535730B2 JP 4535730 B2 JP4535730 B2 JP 4535730B2 JP 2003560978 A JP2003560978 A JP 2003560978A JP 2003560978 A JP2003560978 A JP 2003560978A JP 4535730 B2 JP4535730 B2 JP 4535730B2
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- H—ELECTRICITY
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- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Description
この出願は、Martin StandingとAndrew N.Sawleにより、2001年12月21日に出願された、”支持ボードから所定間隔をおいて配置されたダイ底部を具備する表面実装パッケージ”と題する米国仮特許出願第60/342,333号と、Martin StandingとHazel Deborah Schofieldにより、2001年3月28日に出願された、”チップスケール表面実装デバイス及び製造方法”と題する米国特許出願第09/819,774号の一部継続出願と、に基づき、かつ優先権を主張する。両出願の主題及び開示内容は本願明細書に参考文献として援用する。
12 容器
14 銀を加えた導電性エポキシ樹脂
16 低応力高付着性エポキシ樹脂
18 ソース接点
22 ゲート接点
24 半導体パッケージ
Claims (8)
- 半導体デバイスパッケージであって、前記半導体デバイスパッケージは、
第1のハンダ付可能な平坦な金属製電極を備える第1表面、及び、第2の平坦な金属で被覆した電極を備え、前記第1表面と平行な第2表面とを備える半導体デバイスダイと、
第1表面、及び、前記半導体デバイスダイの前記第1表面と電気的に接続される第2表面を備える平坦なウェブ部分を備える、金属製クリップと、
平坦な前記ウェブ部分の端縁から延在し、且つ前記半導体デバイスダイの端縁から接触面まで配置される、少なくとも1つのハンダ付可能な平坦な金属製後成形電極と、を有し、
前記半導体デバイスダイの、前記第2の平坦な金属で被覆した電極が前記接触面と面一でないように、前記半導体デバイスダイは前記クリップの内部に内向きに0.0254〜0.127(mm)凹み、前記接触面は、支持面の金属で被覆したパターンに取付けられるように構成される半導体パッケージ。 - 半導体デバイスパッケージであって、前記半導体デバイスパッケージは、
半導体デバイスと、
前記半導体デバイスを受容し、かつ第1のハンダ付可能な平坦な金属製電極を備える第1表面、及び、第2の平坦な金属で被覆した電極を備え、前記第1表面と平行な第2表面とを備える半導体デバイスダイと、
第1表面、及び、前記半導体デバイスダイの前記第1表面と電気的に接続される第2表面を備える平坦なウェブ部分を備える、金属製クリップと、
平坦な前記ウェブ部分の端縁から延在し、且つ前記半導体デバイスダイの端縁から接触面まで配置される、少なくとも1つのハンダ付可能な平坦な金属製後成形電極と、を有し、
前記半導体デバイスダイによって受容された前記半導体デバイスの端縁が該半導体デバイスダイの壁から所定の間隔を置いて配置されており、前記半導体デバイスの前記端縁と前記半導体デバイスダイの前記壁との間の空間が、前記パッケージを密封し且つ該パッケージに規格より大きな構造上の強度を加えるために前記半導体デバイスの周りにリングを構成する、絶縁層である低応力高付着エポキシ樹脂で充填されており、及び
前記半導体デバイスダイの、前記第2の平坦な金属で被覆した電極が前記接触面と面一でないように、前記半導体デバイスダイは前記クリップの内部に内向きに0.0254〜0.127(mm)凹み、前記接触面は、支持面の金属で被覆したパターンに取付けられるように構成される半導体パッケージ。 - 前記クリップはカップ形状構造体であり、かつ少なくとも1つの外周リム部分を具備し、少なくとも1つの前記外周リム部分が前記ダイの外部を包囲しかつ該外部から所定間隔をおいて配置される、請求項1または請求項2に記載の半導体パッケージ。
- 前記ダイと前記外周リムの間の前記空間は絶縁ビーズで充填される、請求項3に記載の半導体パッケージ。
- 前記半導体デバイスダイはMOSFET、IGBT、電力ダイオード及びサイリスターの1つである、請求項1または請求項2に記載の半導体パッケージ。
- 前記クリップは単一であり、かつカップ形状をしている、請求項1または請求項2に記載の半導体パッケージ。
- 前記クリップは銅合金から作られ、かつ銀めっきが施される、請求項1または請求項2に記載の半導体パッケージ。
- 第1のハンダ付可能な平坦な前記金属製電極は、銀が加えられた導電性エポキシ樹脂によって、平坦な前記ウェブ部分の前記第2表面に電気的に接続される、請求項1または請求項2に記載の半導体パッケージ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US34233301P | 2001-12-21 | 2001-12-21 | |
US10/327,270 US6930397B2 (en) | 2001-03-28 | 2002-12-20 | Surface mounted package with die bottom spaced from support board |
PCT/US2002/041477 WO2003060984A1 (en) | 2001-12-21 | 2002-12-23 | Surface mounted package with die bottom spaced from support board |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007212938A Division JP2007295014A (ja) | 2001-12-21 | 2007-08-17 | 支持ポートから所定間隔を置いて配置されたダイ底部を具備する表面実装パッケージ |
Publications (2)
Publication Number | Publication Date |
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JP2005515635A JP2005515635A (ja) | 2005-05-26 |
JP4535730B2 true JP4535730B2 (ja) | 2010-09-01 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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JP2003560978A Expired - Fee Related JP4535730B2 (ja) | 2001-12-21 | 2002-12-23 | 半導体パッケージ |
JP2007212938A Pending JP2007295014A (ja) | 2001-12-21 | 2007-08-17 | 支持ポートから所定間隔を置いて配置されたダイ底部を具備する表面実装パッケージ |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007212938A Pending JP2007295014A (ja) | 2001-12-21 | 2007-08-17 | 支持ポートから所定間隔を置いて配置されたダイ底部を具備する表面実装パッケージ |
Country Status (6)
Country | Link |
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US (2) | US6930397B2 (ja) |
EP (1) | EP1466357B1 (ja) |
JP (2) | JP4535730B2 (ja) |
CN (1) | CN100559557C (ja) |
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Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930397B2 (en) * | 2001-03-28 | 2005-08-16 | International Rectifier Corporation | Surface mounted package with die bottom spaced from support board |
JP3879688B2 (ja) * | 2003-03-26 | 2007-02-14 | 株式会社デンソー | 半導体装置 |
US7786558B2 (en) * | 2005-10-20 | 2010-08-31 | Infineon Technologies Ag | Semiconductor component and methods to produce a semiconductor component |
US7723830B2 (en) * | 2006-01-06 | 2010-05-25 | International Rectifier Corporation | Substrate and method for mounting silicon device |
US20070215997A1 (en) * | 2006-03-17 | 2007-09-20 | Martin Standing | Chip-scale package |
US7663212B2 (en) * | 2006-03-21 | 2010-02-16 | Infineon Technologies Ag | Electronic component having exposed surfaces |
US7768075B2 (en) | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
US7541681B2 (en) * | 2006-05-04 | 2009-06-02 | Infineon Technologies Ag | Interconnection structure, electronic component and method of manufacturing the same |
US7910992B2 (en) | 2008-07-15 | 2011-03-22 | Maxim Integrated Products, Inc. | Vertical MOSFET with through-body via for gate |
JP5343574B2 (ja) * | 2009-01-20 | 2013-11-13 | トヨタ自動車株式会社 | ヒートシンクのろう付け方法 |
US8222718B2 (en) * | 2009-02-05 | 2012-07-17 | Fairchild Semiconductor Corporation | Semiconductor die package and method for making the same |
US8563360B2 (en) * | 2009-06-08 | 2013-10-22 | Alpha And Omega Semiconductor, Inc. | Power semiconductor device package and fabrication method |
US20110075392A1 (en) | 2009-09-29 | 2011-03-31 | Astec International Limited | Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets |
US7939370B1 (en) * | 2009-10-29 | 2011-05-10 | Alpha And Omega Semiconductor Incorporated | Power semiconductor package |
US8906747B2 (en) * | 2012-05-23 | 2014-12-09 | Freescale Semiconductor, Inc. | Cavity-type semiconductor package and method of packaging same |
CN203223777U (zh) * | 2012-08-22 | 2013-10-02 | 华夏光股份有限公司 | 照明装置 |
US9536800B2 (en) | 2013-12-07 | 2017-01-03 | Fairchild Semiconductor Corporation | Packaged semiconductor devices and methods of manufacturing |
US9214419B2 (en) * | 2014-02-28 | 2015-12-15 | Alpha And Omega Semiconductor Incorporated | Power semiconductor device and preparation method thereof |
US9117809B1 (en) * | 2014-03-09 | 2015-08-25 | Alpha & Omega Semiconductor (Cayman), Ltd. | Ultra-thin semiconductor device and preparation method thereof |
CN104979220B (zh) * | 2014-04-02 | 2017-09-01 | 万国半导体股份有限公司 | 功率半导体器件及制备方法 |
JP6905958B2 (ja) * | 2018-06-27 | 2021-07-21 | 京セラ株式会社 | 接着構造、撮像装置、および移動体 |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3403438A (en) | 1964-12-02 | 1968-10-01 | Corning Glass Works | Process for joining transistor chip to printed circuit |
US3871014A (en) | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform solder wettable areas on the substrate |
US3972062A (en) | 1973-10-04 | 1976-07-27 | Motorola, Inc. | Mounting assemblies for a plurality of transistor integrated circuit chips |
GB1487945A (en) | 1974-11-20 | 1977-10-05 | Ibm | Semiconductor integrated circuit devices |
JPS6020943Y2 (ja) * | 1979-08-29 | 1985-06-22 | 三菱電機株式会社 | 半導体装置 |
US4604644A (en) | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
JPH01132142A (ja) * | 1987-08-05 | 1989-05-24 | Mitsubishi Electric Corp | 半導体装置のパツケージ構造 |
US5047833A (en) | 1990-10-17 | 1991-09-10 | International Rectifier Corporation | Solderable front metal contact for MOS devices |
JP2984068B2 (ja) | 1991-01-31 | 1999-11-29 | 株式会社日立製作所 | 半導体装置の製造方法 |
JPH05506545A (ja) * | 1991-02-28 | 1993-09-22 | ゼネラル・エレクトリック・カンパニイ | パワー半導体チップ用の高密度気密パッケージのバッチ式組立 |
JPH05129516A (ja) | 1991-11-01 | 1993-05-25 | Hitachi Ltd | 半導体装置 |
CA2089435C (en) | 1992-02-14 | 1997-12-09 | Kenzi Kobayashi | Semiconductor device |
JP2833326B2 (ja) | 1992-03-03 | 1998-12-09 | 松下電器産業株式会社 | 電子部品実装接続体およびその製造方法 |
JPH0637143A (ja) | 1992-07-15 | 1994-02-10 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
US5394490A (en) | 1992-08-11 | 1995-02-28 | Hitachi, Ltd. | Semiconductor device having an optical waveguide interposed in the space between electrode members |
US5313366A (en) | 1992-08-12 | 1994-05-17 | International Business Machines Corporation | Direct chip attach module (DCAM) |
JPH06244231A (ja) | 1993-02-01 | 1994-09-02 | Motorola Inc | 気密半導体デバイスおよびその製造方法 |
US5371404A (en) | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
JP2795788B2 (ja) | 1993-02-18 | 1998-09-10 | シャープ株式会社 | 半導体チップの実装方法 |
US5703405A (en) | 1993-03-15 | 1997-12-30 | Motorola, Inc. | Integrated circuit chip formed from processing two opposing surfaces of a wafer |
US5510758A (en) | 1993-04-07 | 1996-04-23 | Matsushita Electric Industrial Co., Ltd. | Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps |
JP3258764B2 (ja) | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法 |
US5397921A (en) | 1993-09-03 | 1995-03-14 | Advanced Semiconductor Assembly Technology | Tab grid array |
US5734201A (en) | 1993-11-09 | 1998-03-31 | Motorola, Inc. | Low profile semiconductor device with like-sized chip and mounting substrate |
US5367435A (en) | 1993-11-16 | 1994-11-22 | International Business Machines Corporation | Electronic package structure and method of making same |
US5454160A (en) | 1993-12-03 | 1995-10-03 | Ncr Corporation | Apparatus and method for stacking integrated circuit devices |
JPH07193184A (ja) | 1993-12-27 | 1995-07-28 | Fujitsu Ltd | マルチチップモジュールの製造方法及びマルチチップモジュール |
US5446316A (en) * | 1994-01-06 | 1995-08-29 | Harris Corporation | Hermetic package for a high power semiconductor device |
US5578869A (en) | 1994-03-29 | 1996-11-26 | Olin Corporation | Components for housing an integrated circuit device |
JP3377867B2 (ja) | 1994-08-12 | 2003-02-17 | 京セラ株式会社 | 半導体素子収納用パッケージ |
JP2546192B2 (ja) | 1994-09-30 | 1996-10-23 | 日本電気株式会社 | フィルムキャリア半導体装置 |
US5532512A (en) | 1994-10-03 | 1996-07-02 | General Electric Company | Direct stacked and flip chip power semiconductor device structures |
JP3138159B2 (ja) | 1994-11-22 | 2001-02-26 | シャープ株式会社 | 半導体装置、半導体装置実装体、及び半導体装置の交換方法 |
US5904499A (en) | 1994-12-22 | 1999-05-18 | Pace; Benedict G | Package for power semiconductor chips |
JPH08335653A (ja) | 1995-04-07 | 1996-12-17 | Nitto Denko Corp | 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア |
US5655703A (en) | 1995-05-25 | 1997-08-12 | International Business Machines Corporation | Solder hierarchy for chip attachment to substrates |
US5674785A (en) | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
US5726502A (en) | 1996-04-26 | 1998-03-10 | Motorola, Inc. | Bumped semiconductor device with alignment features and method for making the same |
CN1169235C (zh) * | 1996-05-24 | 2004-09-29 | 埃普科斯股份有限公司 | 电子部件、尤其是利用声表面波工作的电子部件-ofw部件 |
US5814884C1 (en) | 1996-10-24 | 2002-01-29 | Int Rectifier Corp | Commonly housed diverse semiconductor die |
US6133634A (en) | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6396127B1 (en) * | 1998-09-25 | 2002-05-28 | International Rectifier Corporation | Semiconductor package |
KR20000057810A (ko) * | 1999-01-28 | 2000-09-25 | 가나이 쓰토무 | 반도체 장치 |
US6262489B1 (en) | 1999-11-08 | 2001-07-17 | Delphi Technologies, Inc. | Flip chip with backside electrical contact and assembly and method therefor |
US6744124B1 (en) | 1999-12-10 | 2004-06-01 | Siliconix Incorporated | Semiconductor die package including cup-shaped leadframe |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US6391687B1 (en) | 2000-10-31 | 2002-05-21 | Fairchild Semiconductor Corporation | Column ball grid array package |
US6777786B2 (en) * | 2001-03-12 | 2004-08-17 | Fairchild Semiconductor Corporation | Semiconductor device including stacked dies mounted on a leadframe |
US6930397B2 (en) * | 2001-03-28 | 2005-08-16 | International Rectifier Corporation | Surface mounted package with die bottom spaced from support board |
US6469398B1 (en) * | 2001-03-29 | 2002-10-22 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
US6784540B2 (en) * | 2001-10-10 | 2004-08-31 | International Rectifier Corp. | Semiconductor device package with improved cooling |
US6841865B2 (en) * | 2002-11-22 | 2005-01-11 | International Rectifier Corporation | Semiconductor device having clips for connecting to external elements |
-
2002
- 2002-12-20 US US10/327,270 patent/US6930397B2/en not_active Expired - Lifetime
- 2002-12-23 AU AU2002361873A patent/AU2002361873A1/en not_active Abandoned
- 2002-12-23 WO PCT/US2002/041477 patent/WO2003060984A1/en active Application Filing
- 2002-12-23 EP EP02797504.4A patent/EP1466357B1/en not_active Expired - Lifetime
- 2002-12-23 JP JP2003560978A patent/JP4535730B2/ja not_active Expired - Fee Related
- 2002-12-23 CN CNB028252802A patent/CN100559557C/zh not_active Expired - Fee Related
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2005
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Also Published As
Publication number | Publication date |
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US20050224960A1 (en) | 2005-10-13 |
CN1605121A (zh) | 2005-04-06 |
US6930397B2 (en) | 2005-08-16 |
JP2007295014A (ja) | 2007-11-08 |
EP1466357B1 (en) | 2017-12-13 |
US20030132531A1 (en) | 2003-07-17 |
WO2003060984A1 (en) | 2003-07-24 |
JP2005515635A (ja) | 2005-05-26 |
EP1466357A4 (en) | 2007-08-15 |
CN100559557C (zh) | 2009-11-11 |
AU2002361873A1 (en) | 2003-07-30 |
EP1466357A1 (en) | 2004-10-13 |
US7285866B2 (en) | 2007-10-23 |
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