1278076 玖、發明說明 I：發明戶斤屬之技術領域3 相關申請案之對照春者 [0001] 這一個申請案係以 Martin Standing與 Andrew Ν· Sawle在2001年十二月21日提出申請之標 5 題為” SURFACE MOUNTED PACKAGE WITH DIE BOTTOM SFACED FROM SUPPORT BOARD” 的美國暫日夺 申請案第60 /342,333，號為基礎並請求該案之優先權，同 時本案係以 Martin Standing 與 Hazel Deborah Schofield 提出申請之標題為” CHIP SCALE SURFACE MOUNTED 10 DEVICE AND PROCESS OF MANUFACTURE” 的美國專 利申請案第〇9/819,774號為基礎並請求該案之優先權， 這兩件申請案的標的與揭示内容均在此併入以供參考。 發明領域 [0002] 本發明係與一半導體封裝有關，更特別地係與 15 一用於容納具有減少週期性溫度變化失效之結構的功率半 導體晶粒之半導體封裝有關。 I：先前技術3 發明背景 [0003] 通常，熱週期會在層合結構中造成常見且重複 20 的應力，而因為例如金屬疲勞導致碎裂。因此，週期性溫 度變化是引起層合結構失效的一個重要原因。 [0004] 在半導體裝置封裝中，溫度的週期變化會引起 在晶粒-底層填料黏接、底層填料-基材黏接、焊接點以及 1278076 玫、發明說明 在其他的區域中之被動層的失效。這會降低封裝的可靠度 。因此，需要提供一減少由於週期性溫度變化所引起的失 效之方法。 [0005]現在參照該等圖式，其中類似的元件標號係代 5表類似的元件，在第i和2圖中係顯示一完全被描述在 2001年二月28日提出申請的美國專利申請案第 09/819,774之半導體封裝，其係被讓度給本案的受讓人且 係在此被併入以供參考。第丨和2圖顯示一半導體封裝 5，其包含一裡面具有M0SFET 1〇的杯形密封外殼12。 10密封外殼12係較佳地以一銅合金製成且係鍍銀的。密封 外设12具有比MOSFET 10的更大的内部尺寸；因此 MOSFET 10可被輕易地收容在密封外殼12的内部。 MOSFET 10的汲極接觸係藉著一層充滿銀導電性環氧樹 脂14而連接到密封外殼12的底部。一圈的低應力高黏 15附性環氧樹脂16係被施加在MOSFET 10的邊緣周圍以 密封並將該封裝增加額外的結構強度。設置在m〇sfet 10的表面上相對於汲極接觸處的MOSFET 10中的源極 接觸18與閘極接觸20，係如第1圖所示的暴露出來。 密封外殼12包含有二列設置在其之相對的二個邊緣上的 20突出物22。突出物係被提供以與在例如絕緣金屬基材或 般的電路板之電路板（未顯示）上的各別連接區形成電 氣接觸，藉此將MOSFET 10中汲極的電氣地連接到其在 電路板裡面的位置。如第1圖所示，MOSFET 10的源極 1278076 玖、發明說明 的接觸表面齊平 接觸18是與密封外殼12的突出物22 的0 因此，當封裝 被安裝在電路板上的時候， 5 MOSFET 10中的源極接觸18與閘極接觸 板的表面齊平。 20將與電路 [0006] |述的封裝可能會因為如上述的週期性溫度 變化而導致可能的失效。因此，需要生產一種與上述相: 結構的封裝體設計，以使得由於熱週期性變化所導致的基 材失效降低。 10 【發明内容】 發明摘要 [0007] 舉例來說，為了要減少由熱的週期變化所導致 之基材失效，本發明揭示了一種半導體裝置封裝，其包含 具有一貫質與第二表面平行之一第一表面的半導體裝置晶 15粒，且該第一表面和第二表面每個都有一可施以焊接的平 面電極。更進-步的說，一具有平板部分的金屬失係被揭 露，其包含有有-第-和第二表面，該第二表面係與該半 導體裝置晶粒的第一表面電氣連接。 [0008] 自該金屬夾的平板部分之邊緣，至少一可焊接 20的平面金屬後成形電極係從該半導體裝置晶粒的一邊緣 延伸並與之分離。該晶粒係設置在該金屬夾之内以使得該 晶粒係在該金屬夾的内部向内嵌合，而該晶粒的第二表面 並不是與該至少一該可焊接的後成形平面金屬電極齊平 1278076 玖、發明說明 或共平面）。可焊接的平面金屬後成形電極係被移至一在 忒晶粒第二表面之上的平行平面上。 [0009]忒至少一可焊接平面金屬後成形電極係可安裝 於一例如電路板之支持表面上的金屬化圖案上，而該晶粒 5的第二表面係與該支持表面上的金屬化圖案分離的。 [0010]因此，依據本發明的半導體封裝可以減少由 於…、週期f生變化失效數目，並因此增加封裝的可靠度。此 外，依據本發明的半導體封裝包含有一例如M0SFET垂 直傳導MOS閘控晶粒，其具有在其上設置有一主要的電 10極和一控制電極的第一主要表面，以及在其上設置有另外 一主要電極之相對於該第一主要表面的另一主要的表面。 一般來說，被用於依照本發明的封裝之垂直傳導 MOSFET的第-主要電極是源極；然而其之第二主要電 極疋汲極。一垂直傳導M〇SFET的控制電極通常係為閘 15 極〇 [0011]雖然在此處係以功率M〇SFET來描述晶粒， 明顯地該晶粒可以是任何所需要的晶粒，其包括任何的 MOS-閘控裝置（例如IGBT)、閘流體或二極體或其之類 似物。 20 置式簡要說明 [0012]第1圖係為依據習知技藝的半導體封裝之頂 視圖； 1278076 玖、發明說明 [0013] 第2圖顯示第1圖的半導體封裝在線1-1 的方向上的截面圖；與 [0014] 第3圖顯示依據第1和2圖進行修改的半 導體封裝之截面圖。 5 【實施方式】 較佳具體例的詳細描述 [0015] 現在參照第3圖，依據本發明，半導體封裝 24包含被安置的比第1圖和第2圖中所示習知技藝還 要深入密封外殼 12 内部的 MOSFET 10。因此， 10 MOSFET 10中的源極接觸18與閘極接觸20 (未在第3 圖中顯示）不再是與密封外殼12的突出物22齊平。這 種結構在第3圖中係以在虛線A，A’之間的間隙來顯示 。已經發現當MOSFET 10以較深約0.001-0.005吋來安 置在密封外殼12裡面以使得源極18與電路板的平面並 15 列時，在將之向下焊接或以一環氧基樹脂固定至基材時， 由於熱週期性變化所導致失效部分將會減少。 [0016] 換句話說，依據本發明的半導體封裝包含一在 其内部空間中收容一 MOSFET或其他的相似的半導體類 型裝置晶粒的金屬密封外殼。被如此收容的MOSFET係 20 在密封外殼中向内嵌合，並被設置成使得該MOSFET的 汲極係面對該密封外殼的的底部，且係藉由一層導電性環 氧基樹脂或一漢料或是其等之類似物而與其電氣連接。如 此設置之該MOSFET的邊緣係與密封外殼壁被分離。介 10 1278076 玖、發明說明 於MOSFET的邊緣和密封外殼壁之間的空間可充滿一絕 緣層。該密封外殼係較佳地在其二相對邊緣上包含二列的 焊接柱。該等焊接柱係被連接至例如一電路板的基材上之 傳導墊，以將MOSFET的汲極連接到在電路裡面的適當 5 的位置。此外在本發明另一個具體例中，該等焊接柱可能 是一個全部或一部分的密封外殼的邊緣的部分。1278076 玖, invention description I: the technical field of the invention of the households 3 The relevant application of the spring [0001] This application was filed on December 21, 2001 by Martin Standing and Andrew S Sawle. 5 SURFACE MOUNTED PACKAGE WITH DIE BOTTOM SFACED FROM SUPPORT BOARD's US Temporary Application No. 60 / 342, 333, based on and requesting the priority of the case, and the case was filed by Martin Standing and Hazel Deborah Schofield U.S. Patent Application Serial No. 9/819,774, entitled "CHIP SCALE SURFACE MOUNTED 10 DEVICE AND PROCESS OF MANUFACTURE", which is based on and claims priority, the subject matter and disclosure of both of which are incorporated herein by reference. For reference. FIELD OF THE INVENTION The present invention relates to a semiconductor package, and more particularly to a semiconductor package for accommodating power semiconductor dies having structures that reduce periodic temperature variation failure. I: Prior Art 3 Background of the Invention [0003] In general, a thermal cycle causes a common and repeated 20 stress in a laminated structure, and is broken due to, for example, metal fatigue. Therefore, periodic temperature changes are an important cause of failure of the laminated structure. [0004] In semiconductor device packages, periodic variations in temperature can cause failure of the passive layer in the die-underfill bonding, underfill-substrate bonding, solder joints, and 1278076, in other areas of the invention. . This will reduce the reliability of the package. Therefore, there is a need to provide a method of reducing the failure caused by periodic temperature changes. [0005] Reference is now made to the drawings, in which like reference numerals refer to the The semiconductor package of U.S. Patent Application Serial No. 09/819,774, the disclosure of which is incorporated herein by reference. Figures 2 and 2 show a semiconductor package 5 comprising a cup-shaped sealed housing 12 having a MOSFET 1 里面 therein. The sealed casing 12 is preferably made of a copper alloy and is silver plated. The sealed peripheral 12 has a larger internal dimension than the MOSFET 10; therefore, the MOSFET 10 can be easily housed inside the sealed casing 12. The drain contact of the MOSFET 10 is connected to the bottom of the hermetic envelope 12 by a layer of silver-filled epoxy resin 14. A loop of low stress, high viscosity 15 attachment epoxy 16 is applied around the edges of the MOSFET 10 to seal and add additional structural strength to the package. The source contact 18 and the gate contact 20 in the MOSFET 10 disposed on the surface of the m〇sfet 10 with respect to the drain contact are exposed as shown in Fig. 1. The sealed outer casing 12 includes two rows of 20 projections 22 disposed on opposite edges thereof. The protrusions are provided to make electrical contact with respective connection regions on a circuit board (not shown) such as an insulative metal substrate or a circuit board, thereby electrically connecting the drains of the MOSFET 10 to them. The position inside the board. As shown in FIG. 1, the source 1278076 of the MOSFET 10, the contact surface flush contact 18 of the invention is 0 with the protrusion 22 of the sealed case 12. Therefore, when the package is mounted on the board, the 5 MOSFET The source contact 18 in 10 is flush with the surface of the gate contact plate. 20 The package described in [0006] may cause possible failure due to periodic temperature variations as described above. Therefore, there is a need to produce a package design that is structurally oriented as described above to reduce substrate failure due to thermal periodic variations. 10 SUMMARY OF THE INVENTION [0007] For example, in order to reduce substrate failure caused by thermal cycle variations, the present invention discloses a semiconductor device package including one having a consistent quality parallel to a second surface The first surface of the semiconductor device has 15 grains, and the first surface and the second surface each have a planar electrode to which solder can be applied. More incrementally, a metal loss system having a flat portion is disclosed that includes a -first and second surface that is electrically coupled to the first surface of the semiconductor device die. [0008] From the edge of the flat portion of the metal clip, at least one solderable 20 planar metal post-form electrode extends from and is separated from an edge of the semiconductor device die. The die is disposed within the metal clip such that the die is inwardly fitted within the metal clip, and the second surface of the die is not associated with the at least one solderable post-formed planar metal The electrode is flush 1278076 玖, invention description or coplanar). The solderable planar metal post-forming electrode is moved to a parallel plane above the second surface of the germanium die. [0009] 忒 at least one solderable planar metal post-formed electrode system can be mounted on a metallization pattern on a support surface such as a circuit board, and the second surface of the die 5 is bonded to a metallization pattern on the support surface Detached. [0010] Therefore, the semiconductor package according to the present invention can reduce the number of failures due to ..., period f, and thus increase the reliability of the package. Further, a semiconductor package in accordance with the present invention includes, for example, a MOSFET vertical conduction MOS gate die having a first major surface having a main electrical 10 and a control electrode disposed thereon, and another one disposed thereon The other major surface of the primary electrode relative to the first major surface. In general, the first primary electrode of a vertically conductive MOSFET used in a package in accordance with the present invention is a source; however, its second primary electrode is a drain. The control electrode of a vertical conducting M〇SFET is typically a gate 15 pole [0011] although a power M〇SFET is used herein to describe the die, it is apparent that the die can be any desired die, including Any MOS-gate device (such as IGBT), thyristor or diode or the like. BRIEF DESCRIPTION OF THE DRAWINGS [0012] Fig. 1 is a top view of a semiconductor package according to the prior art; 1278076 发明, invention description [0013] Fig. 2 shows a cross section of the semiconductor package of Fig. 1 in the direction of line 1-1 Figure 3 and [0014] Figure 3 shows a cross-sectional view of a semiconductor package modified in accordance with Figures 1 and 2. [Embodiment] Detailed Description of Preferred Embodiments [0015] Referring now to FIG. 3, in accordance with the present invention, the semiconductor package 24 includes a deeper seal that is disposed than the conventional techniques shown in FIGS. 1 and 2. MOSFET 10 inside the housing 12. Thus, the source contact 18 and the gate contact 20 (not shown in FIG. 3) in the 10 MOSFET 10 are no longer flush with the protrusions 22 of the sealed enclosure 12. This structure is shown in Fig. 3 by the gap between the broken lines A, A'. It has been found that when the MOSFET 10 is placed inside the hermetic envelope 12 at a depth of about 0.001-0.005 Torr so that the source 18 and the plane of the board are 15 columns, it is soldered down or fixed with an epoxy resin. In the case of a substrate, the failure portion will be reduced due to thermal cyclical changes. In other words, the semiconductor package in accordance with the present invention includes a metal hermetic housing that houses a MOSFET or other similar semiconductor type device die in its internal space. The MOSFET system 20 thus housed is fitted inwardly in the sealed casing, and is disposed such that the MOSFET of the MOSFET faces the bottom of the sealed casing, and is made of a layer of conductive epoxy resin or a han. The material or its analog is electrically connected thereto. The edge of the MOSFET thus disposed is separated from the wall of the sealed casing. 10 1278076 发明Inventive Description The space between the edge of the MOSFET and the wall of the sealed enclosure can be filled with an insulating layer. The sealed outer casing preferably includes two columns of welded posts on opposite sides thereof. The solder posts are connected to a conductive pad on a substrate such as a circuit board to connect the drain of the MOSFET to the appropriate 5 locations inside the circuit. Further in another embodiment of the invention, the welded posts may be part of an edge of a sealed enclosure that is wholly or partially.
[0017] 由於這種結構的結果，當該密封外殼被安置在 其上的時候，MOSFET的源極與閘極會面對基體。已經 發現如果MOSFET被安置在密封外殼裡以使得MOSFET 10 的源極與閘極變成與基材的表面下齊平的話，因為熱週期 性變化所造成的失效會改善。因此，依據本發明的一個態 樣，MOSFET的底部表面係齊平在基材平面下0.001-0.005吋處以減少溫度週期變化失效。該下方齊平的體積 部份係充滿例如焊料、環氧基樹脂和其等之類似物之導電 15 性附接材料。 [0018] 所揭露之發明可以在不更改其之範圍和精神下 加以變化。習於此藝者將會瞭解，除了參照本發明的較佳 具體例所描述的事物之外的事物，也可以用來完成本發明 所欲的有利結果。舉例來說，除了 MOSFET 10，IGBT、 20 閘流體、二極體或任何其他適當的半導體裝置都可能被用 於依據本發明的封裝中。在進一步的具體例中，其他的合 金可以用來形成密封外殼12,並且/或示除了充滿銀的環 11 1278076 玖、發明說明 氧樹脂14之外，其他的導電性方式也可以用來將一半導 體晶粒連接到密封外殼12。 [0019]因此，雖然本發明已經依據特別的具體例來描 述但是终多其他的變化和修改和其他的用途對於習於此 5藝者而言將是很明顯的。因此，本發明係較佳地不被在此 之特疋揭示内容所限制，而只是被隨附加的申請專利範圍 所限制。 【囷式簡單說明】 [0012] 第1圖係為依據習知技藝的半導體封裝之頂 !〇 視圖； [0013] 第2圖顯示第i圖的半導體封裝在線M 的方向上的截面圖；與 [0014] 第3圖顯示依據第1和2圖進行修改的半 導體封裝之截面圖。 15【圖式之主要元件代表符號表】[0017] As a result of this configuration, when the sealed housing is placed thereon, the source and gate of the MOSFET will face the substrate. It has been found that if the MOSFET is placed in a hermetic enclosure such that the source and gate of MOSFET 10 become flush with the surface of the substrate, failure due to thermal cycling changes can be improved. Thus, in accordance with one aspect of the invention, the bottom surface of the MOSFET is flushed at 0.001-0.005 Å below the plane of the substrate to reduce temperature cycle failure. The flushed volume portion below is filled with a conductive attachment material such as solder, epoxy, and the like. [0018] The disclosed invention may be varied without departing from the scope and spirit of the invention. Those skilled in the art will appreciate that other things besides those described in connection with the preferred embodiments of the present invention can be used to accomplish the desired results of the present invention. For example, in addition to MOSFET 10, an IGBT, a thyristor, a diode, or any other suitable semiconductor device may be used in the package in accordance with the present invention. In a further embodiment, other alloys may be used to form the sealed outer casing 12, and/or other than the silver-filled ring 11 1278076 玖, the inventive description of the oxy-resin 14, other conductive means may also be used to The semiconductor die is connected to the hermetic envelope 12. [0019] Accordingly, while the invention has been described in terms of a particular embodiment, many other variations and modifications and other uses will be apparent to those skilled in the art. Therefore, the present invention is preferably not limited by the scope of the disclosure, but is limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a top view of a semiconductor package in accordance with the prior art; [0013] FIG. 2 is a cross-sectional view showing the direction of the semiconductor package line M of the second embodiment; [0014] FIG. 3 is a cross-sectional view showing a semiconductor package modified in accordance with FIGS. 1 and 2. 15 [The main component representative symbol table of the drawing]
10 MOSFET 12密封外殼 W充滿銀的環氧樹脂 16低應力高黏附性環氧樹脂 20 18源極接觸 20閘極接觸 22突出物 24半導體封襞 1210 MOSFET 12 sealed housing W silver filled epoxy 16 low stress high adhesion epoxy 20 18 source contact 20 gate contact 22 protrusion 24 semiconductor package 12