JP4525866B2 - 回路モジュール及びその製造方法 - Google Patents
回路モジュール及びその製造方法 Download PDFInfo
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- JP4525866B2 JP4525866B2 JP2010506753A JP2010506753A JP4525866B2 JP 4525866 B2 JP4525866 B2 JP 4525866B2 JP 2010506753 A JP2010506753 A JP 2010506753A JP 2010506753 A JP2010506753 A JP 2010506753A JP 4525866 B2 JP4525866 B2 JP 4525866B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 41
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- 230000002950 deficient Effects 0.000 description 11
- 230000004048 modification Effects 0.000 description 6
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- 230000000737 periodic effect Effects 0.000 description 2
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- 239000003990 capacitor Substances 0.000 description 1
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- 230000011218 segmentation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Description
以下に、本発明の一実施形態に係る回路モジュールの構成について図面を参照しながら説明する。図1は、本発明の一実施形態に係る回路モジュール10の外観斜視図である。ただし、図1は、その内部構造を理解できるように一部透視して記載した。図2は、図1の回路モジュール10のA−Aにおける断面構造図である。以下では、略直方体状をなす回路モジュール10において、高さ方向をz軸方向と定義する。また、z軸方向から平面視したときの短辺方向をx軸方向と定義し、長辺方向をy軸方向と定義する。x軸、y軸、z軸は、互いに直交している。
次に、回路モジュール10の製造方法について図面を参照しながら説明する。図4ないし図6、図8及び図10は、回路モジュール10の作製時の外観斜視図である。図7、図9及び図11は、回路モジュール10の工程断面図である。
以上のような回路モジュール10及びその製造方法によれば、シールド層18において導電性樹脂が塗布されない欠陥領域が発生することを低減できる。より詳細には、特許文献1に記載の回路モジュール500の製造方法では、図14に示すように、シールド層510が形成される絶縁層506の主面は、平坦である。このような平坦な絶縁層506上にペースト状の導電性樹脂を塗布すると、薄く伸びすぎてしまう。その結果、回路モジュール500の製造方法では、シールド層510において、導電性樹脂が塗布されない欠陥領域が発生するおそれがある。
以下に、変形例に係る回路モジュール及びその製造方法について図面を参照しながら説明する。図12は、変形例に係る回路モジュール10aの断面構造図である。図13は、変形例に係る回路モジュール10aの工程断面図である。
F1 凸部
F2 凹部
G グランド導体
S1〜S3 主面
10,10a 回路モジュール
12 回路基板
14a,14b 電子部品
16,116 絶縁体層
18,118 シールド層
20,42,120 溝
22,122 突起
D1,D1',D2 ダイサー
112 マザー基板
Claims (12)
- マザー基板を準備する工程と、
前記マザー基板の主面上に、複数の電子部品を実装する工程と、
前記マザー基板の主面及び前記複数の電子部品を覆うように絶縁体層を形成する工程と、
前記絶縁体層の主面に凹凸が形成され、かつ、該絶縁体層の厚みが所定の厚みとなるように、該絶縁体層を切削する工程と、
前記絶縁体層の主面上に導電性樹脂を塗布して、シールド層を形成する工程と、
前記絶縁体層及び前記シールド層が形成された前記マザー基板を分割して、複数の回路モジュールを得る工程と、
を備えていること、
を特徴とする回路モジュールの製造方法。 - 前記絶縁体層を切削する工程では、第1の方向に延在する複数本の溝又は複数本の突起を該絶縁体層の主面に形成すること、
を特徴とする請求項1に記載の回路モジュールの製造方法。 - 前記複数本の溝の間隔又は前記複数本の突起の間隔は、前記第1の方向に直交する第2の方向における前記回路モジュールの幅よりも狭いこと、
を特徴とする請求項2に記載の回路モジュールの製造方法。 - 前記絶縁体層を切削する工程では、該絶縁体層の主面上において、前記第1の方向にダイサーを移動させた後、該第1の方向に直交する第2の方向に該ダイサーをずらして該第1の方向に移動させることを繰り返すこと、
を特徴とする請求項2又は請求項3のいずれかに記載の回路モジュールの製造方法。 - 前記ダイサーの前記第2の方向における幅は、前記回路モジュールの該第2の方向における幅よりも小さいこと、
を特徴とする請求項4に記載の回路モジュールの製造方法。 - 前記絶縁体層を切削する工程において、前記第2の方向に前記ダイサーをずらす幅は、該ダイサーの前記第2の方向における幅よりも小さいこと、
を特徴とする請求項4又は請求項5のいずれかに記載の回路モジュールの製造方法。 - 前記ダイサーの切削面は、凹凸を有していること、
を特徴とする請求項4ないし請求項6のいずれかに記載の回路モジュールの製造方法。 - 前記シールド層を形成する工程では、スピンコート法により、前記絶縁体層の主面上に導電性樹脂を塗布すること、
を特徴とする請求項1ないし請求項7のいずれかに記載の回路モジュールの製造方法。 - 基板と、
前記基板の主面上に実装されている電子部品と、
前記基板の主面及び前記電子部品を覆い、かつ、主面に凹凸が設けられている絶縁体層と、
前記絶縁体層の主面上に設けられている導電性樹脂からなるシールド層と、
を備えていること、
を特徴とする回路モジュール。 - 前記凹凸は、第1の方向に延在する溝又は突起であること、
を特徴とする請求項9に記載の回路モジュール。 - 前記溝又は前記突起は、所定間隔で複数設けられていること、
を特徴とする請求項10に記載の回路モジュール。 - 前記絶縁体層の主面の凹凸に倣った凹凸が、前記シールド層の主面に形成されていること、
を特徴とする請求項9ないし請求項11に記載の回路モジュール。
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EP (1) | EP2320718A4 (ja) |
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CN102077700B (zh) | 2014-03-26 |
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US8724334B2 (en) | 2014-05-13 |
CN102077700A (zh) | 2011-05-25 |
US20120281370A1 (en) | 2012-11-08 |
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