JP4419025B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4419025B2 JP4419025B2 JP2006238628A JP2006238628A JP4419025B2 JP 4419025 B2 JP4419025 B2 JP 4419025B2 JP 2006238628 A JP2006238628 A JP 2006238628A JP 2006238628 A JP2006238628 A JP 2006238628A JP 4419025 B2 JP4419025 B2 JP 4419025B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- porous
- mask
- layer
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000000034 method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 16
- 239000011148 porous material Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 89
- 238000005530 etching Methods 0.000 description 43
- 239000010949 copper Substances 0.000 description 19
- 239000003361 porogen Substances 0.000 description 17
- 229920000090 poly(aryl ether) Polymers 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 229960001730 nitrous oxide Drugs 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
なお、上記実施形態においては、第2絶縁膜9が被覆絶縁膜として機能する例について説明したが、図7に示すように、第1絶縁膜8と第2絶縁膜9との間に、被覆絶縁膜20が設けられていてもよい。ここで、被覆絶縁膜20としては、非多孔質性の低誘電率材料膜であることが好ましく、5nmから15nmの膜厚で設けられることとでする。ここでは、例えばSiOCからなる被覆絶縁膜20が15nmの膜厚で設けられることとする。このように、被覆絶縁膜20を介在させた場合には、被覆絶縁膜20が第1絶縁膜8の上層側からのポロジェンAの分解除去を防止するため、第2絶縁膜9を例えばSiOC或いは、PAE等の多孔質性の絶縁膜で形成することが好ましい。
Claims (2)
- 基板上に、空孔形成材料を含有する非多孔質性の絶縁膜を形成する工程と、
前記絶縁膜の上層側から前記空孔形成材料が分解除去されるのを防ぐように、前記絶縁膜上に被覆絶縁膜を形成する工程と、
前記被覆絶縁膜および前記絶縁膜に、前記基板に達する溝パターンを形成する工程と、
熱処理を行なうことにより、前記溝パターン側から、前記絶縁膜中の前記空孔形成材料を分解除去することで、前記絶縁膜を多孔質化する工程と、
前記溝パターンに導電材料を埋め込むことで、導電層パターンを形成する工程とを有し、
前記絶縁膜には、前記溝パターンが疎に形成された領域と、この領域よりも当該溝パターンが密に形成された領域とが設けられ、
前記絶縁膜を多孔質化する工程では、前記溝パターンが疎に形成された領域における当該溝パターン間の中央に前記空孔形成材料が残存した状態の非多孔質領域を形成する
半導体装置の製造方法。 - 前記溝パターンを形成する工程では、前記基板に達する状態で前記絶縁膜に設けられた接続孔と、当該接続孔の上部に連通する状態で前記被覆絶縁膜に設けられた配線溝とを形成する
請求項1に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006238628A JP4419025B2 (ja) | 2006-09-04 | 2006-09-04 | 半導体装置の製造方法 |
TW096130768A TWI351074B (en) | 2006-09-04 | 2007-08-20 | Semiconductor device and method for manufacturing semiconductor device |
US11/846,807 US7602061B2 (en) | 2006-09-04 | 2007-08-29 | Semiconductor device and method for manufacturing semiconductor device |
KR1020070088353A KR101354126B1 (ko) | 2006-09-04 | 2007-08-31 | 반도체 장치 및 반도체 장치의 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006238628A JP4419025B2 (ja) | 2006-09-04 | 2006-09-04 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008060498A JP2008060498A (ja) | 2008-03-13 |
JP4419025B2 true JP4419025B2 (ja) | 2010-02-24 |
Family
ID=39150356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006238628A Expired - Fee Related JP4419025B2 (ja) | 2006-09-04 | 2006-09-04 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7602061B2 (ja) |
JP (1) | JP4419025B2 (ja) |
KR (1) | KR101354126B1 (ja) |
TW (1) | TWI351074B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009194072A (ja) * | 2008-02-13 | 2009-08-27 | Toshiba Corp | 半導体装置の製造方法 |
JP5391594B2 (ja) * | 2008-07-02 | 2014-01-15 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2010129950A (ja) * | 2008-12-01 | 2010-06-10 | Panasonic Corp | 半導体装置及びその製造方法 |
US8252192B2 (en) * | 2009-03-26 | 2012-08-28 | Tokyo Electron Limited | Method of pattern etching a dielectric film while removing a mask layer |
JP5487469B2 (ja) * | 2010-03-29 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8916051B2 (en) * | 2010-12-23 | 2014-12-23 | United Microelectronics Corp. | Method of forming via hole |
US8552540B2 (en) * | 2011-05-10 | 2013-10-08 | Conexant Systems, Inc. | Wafer level package with thermal pad for higher power dissipation |
US8932934B2 (en) * | 2013-05-28 | 2015-01-13 | Global Foundries Inc. | Methods of self-forming barrier integration with pore stuffed ULK material |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002334873A (ja) | 2001-05-10 | 2002-11-22 | Toshiba Corp | 半導体装置およびその製造方法 |
US7018918B2 (en) * | 2002-11-21 | 2006-03-28 | Intel Corporation | Method of forming a selectively converted inter-layer dielectric using a porogen material |
JP2004235548A (ja) | 2003-01-31 | 2004-08-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US6774053B1 (en) * | 2003-03-07 | 2004-08-10 | Freescale Semiconductor, Inc. | Method and structure for low-k dielectric constant applications |
JP4578816B2 (ja) | 2004-02-02 | 2010-11-10 | Okiセミコンダクタ株式会社 | 半導体装置およびその製造方法 |
JP4194508B2 (ja) * | 2004-02-26 | 2008-12-10 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2006024811A (ja) * | 2004-07-09 | 2006-01-26 | Sony Corp | 半導体装置の製造方法 |
-
2006
- 2006-09-04 JP JP2006238628A patent/JP4419025B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-20 TW TW096130768A patent/TWI351074B/zh not_active IP Right Cessation
- 2007-08-29 US US11/846,807 patent/US7602061B2/en not_active Expired - Fee Related
- 2007-08-31 KR KR1020070088353A patent/KR101354126B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2008060498A (ja) | 2008-03-13 |
KR101354126B1 (ko) | 2014-01-22 |
KR20080021553A (ko) | 2008-03-07 |
TW200816380A (en) | 2008-04-01 |
TWI351074B (en) | 2011-10-21 |
US7602061B2 (en) | 2009-10-13 |
US20080054454A1 (en) | 2008-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4177993B2 (ja) | 半導体装置及びその製造方法 | |
US7304386B2 (en) | Semiconductor device having a multilayer wiring structure | |
JP4419025B2 (ja) | 半導体装置の製造方法 | |
JP2007173511A (ja) | 半導体装置の製造方法 | |
JP2006041039A (ja) | 半導体装置の製造方法 | |
JP2007281114A (ja) | 半導体装置の製造方法および半導体装置 | |
JP2007294625A (ja) | 半導体装置の製造方法 | |
JP2007165428A (ja) | 半導体装置の製造方法 | |
JP2009141334A (ja) | 半導体装置 | |
JP2005203672A (ja) | 半導体装置の製造方法 | |
JP5613272B2 (ja) | 半導体装置 | |
JP5200436B2 (ja) | 半導体装置の製造方法 | |
JP4525534B2 (ja) | 半導体装置の製造方法 | |
JP2006196642A (ja) | 半導体装置およびその製造方法 | |
JP2006351732A (ja) | 半導体装置の製造方法 | |
JP2010080607A (ja) | 半導体装置の製造方法 | |
JP2006319116A (ja) | 半導体装置およびその製造方法 | |
JP2004311477A (ja) | 半導体装置の製造方法 | |
JP4797821B2 (ja) | 半導体装置の製造方法 | |
JP2010080606A (ja) | 半導体装置の製造方法 | |
JP2005217223A (ja) | 半導体装置の製造方法 | |
KR100483838B1 (ko) | 금속배선의 듀얼 다마신 방법 | |
JPWO2005024935A1 (ja) | 半導体装置 | |
JP2006332408A (ja) | 半導体装置の製造方法 | |
JP2005109343A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081117 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081125 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090122 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090512 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090617 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20091009 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091104 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20091106 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091117 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121211 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121211 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131211 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |