JP4417962B2 - 超接合デバイスの製造での平坦化方法 - Google Patents

超接合デバイスの製造での平坦化方法 Download PDF

Info

Publication number
JP4417962B2
JP4417962B2 JP2006545758A JP2006545758A JP4417962B2 JP 4417962 B2 JP4417962 B2 JP 4417962B2 JP 2006545758 A JP2006545758 A JP 2006545758A JP 2006545758 A JP2006545758 A JP 2006545758A JP 4417962 B2 JP4417962 B2 JP 4417962B2
Authority
JP
Japan
Prior art keywords
doped region
conductivity type
mesa
region
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006545758A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007515080A (ja
JP2007515080A5 (enExample
Inventor
イュアン シィー、フュー
Original Assignee
サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド filed Critical サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド
Publication of JP2007515080A publication Critical patent/JP2007515080A/ja
Publication of JP2007515080A5 publication Critical patent/JP2007515080A5/ja
Application granted granted Critical
Publication of JP4417962B2 publication Critical patent/JP4417962B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/837—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs
    • H10D84/839—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs comprising VDMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
JP2006545758A 2003-12-19 2004-12-10 超接合デバイスの製造での平坦化方法 Expired - Fee Related JP4417962B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53146703P 2003-12-19 2003-12-19
PCT/US2004/041375 WO2005065144A2 (en) 2003-12-19 2004-12-10 Planarization method of manufacturing a superjunction device

Publications (3)

Publication Number Publication Date
JP2007515080A JP2007515080A (ja) 2007-06-07
JP2007515080A5 JP2007515080A5 (enExample) 2008-09-25
JP4417962B2 true JP4417962B2 (ja) 2010-02-17

Family

ID=34748767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006545758A Expired - Fee Related JP4417962B2 (ja) 2003-12-19 2004-12-10 超接合デバイスの製造での平坦化方法

Country Status (6)

Country Link
US (1) US7199006B2 (enExample)
EP (1) EP1706899A4 (enExample)
JP (1) JP4417962B2 (enExample)
KR (1) KR100879588B1 (enExample)
TW (1) TWI353621B (enExample)
WO (1) WO2005065144A2 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
JP4417962B2 (ja) * 2003-12-19 2010-02-17 サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド 超接合デバイスの製造での平坦化方法
US7041560B2 (en) * 2003-12-19 2006-05-09 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device with conventional terminations
TWI401749B (zh) 2004-12-27 2013-07-11 ３Ｄ半導體股份有限公司 用於高電壓超接面終止之方法
US7439583B2 (en) * 2004-12-27 2008-10-21 Third Dimension (3D) Semiconductor, Inc. Tungsten plug drain extension
EP1710843B1 (en) * 2005-04-04 2012-09-19 STMicroelectronics Srl Integrated power device
TW200727367A (en) * 2005-04-22 2007-07-16 Icemos Technology Corp Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches
US7446018B2 (en) 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
US7429772B2 (en) * 2006-04-27 2008-09-30 Icemos Technology Corporation Technique for stable processing of thin/fragile substrates
US8580651B2 (en) * 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US7723172B2 (en) 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US8012806B2 (en) 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices
US8159039B2 (en) 2008-01-11 2012-04-17 Icemos Technology Ltd. Superjunction device having a dielectric termination and methods for manufacturing the device
US7795045B2 (en) * 2008-02-13 2010-09-14 Icemos Technology Ltd. Trench depth monitor for semiconductor manufacturing
US7846821B2 (en) 2008-02-13 2010-12-07 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US8030133B2 (en) * 2008-03-28 2011-10-04 Icemos Technology Ltd. Method of fabricating a bonded wafer substrate for use in MEMS structures
US7807576B2 (en) * 2008-06-20 2010-10-05 Fairchild Semiconductor Corporation Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices
US20110198689A1 (en) * 2010-02-17 2011-08-18 Suku Kim Semiconductor devices containing trench mosfets with superjunctions
US9490372B2 (en) 2011-01-21 2016-11-08 Semiconductor Components Industries, Llc Method of forming a semiconductor device termination and structure therefor
US8598654B2 (en) 2011-03-16 2013-12-03 Fairchild Semiconductor Corporation MOSFET device with thick trench bottom oxide
JP2013175655A (ja) * 2012-02-27 2013-09-05 Toshiba Corp 電力用半導体装置及びその製造方法
US8946814B2 (en) 2012-04-05 2015-02-03 Icemos Technology Ltd. Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates
US9576842B2 (en) 2012-12-10 2017-02-21 Icemos Technology, Ltd. Grass removal in patterned cavity etching
US9391135B1 (en) 2015-03-23 2016-07-12 Semiconductor Components Industries, Llc Semiconductor device
CN106158955A (zh) 2015-03-30 2016-11-23 中芯国际集成电路制造(上海)有限公司 功率半导体器件及其形成方法
US10115790B2 (en) 2015-09-17 2018-10-30 Semiconductor Components Industries, Llc Electronic device including an insulating structure
US10497602B2 (en) 2016-08-01 2019-12-03 Semiconductor Components Industries, Llc Process of forming an electronic device including forming an electronic component and removing a portion of a substrate
FR3061357B1 (fr) * 2016-12-27 2019-05-24 Aledia Procede de realisation d’un dispositif optoelectronique comportant une etape de gravure de la face arriere du substrat de croissance

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158206A (en) * 1977-02-07 1979-06-12 Rca Corporation Semiconductor device
JPS5553462A (en) * 1978-10-13 1980-04-18 Int Rectifier Corp Mosfet element
US5045903A (en) * 1988-05-17 1991-09-03 Advanced Power Technology, Inc. Topographic pattern delineated power MOSFET with profile tailored recessed source
US5019522A (en) * 1986-03-21 1991-05-28 Advanced Power Technology, Inc. Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US5677867A (en) * 1991-06-12 1997-10-14 Hazani; Emanuel Memory with isolatable expandable bit lines
US5472888A (en) * 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
CN1019720B (zh) * 1991-03-19 1992-12-30 电子科技大学 半导体功率器件
JPH05190663A (ja) * 1992-01-07 1993-07-30 Iwatsu Electric Co Ltd 半導体集積回路の製造方法
JPH05304297A (ja) * 1992-01-29 1993-11-16 Nec Corp 電力用半導体装置およびその製造方法
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
CN1035294C (zh) * 1993-10-29 1997-06-25 电子科技大学 具有异形掺杂岛的半导体器件耐压层
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5665633A (en) * 1995-04-06 1997-09-09 Motorola, Inc. Process for forming a semiconductor device having field isolation
JP3402043B2 (ja) * 1996-01-22 2003-04-28 日産自動車株式会社 電界効果トランジスタ
JP4047384B2 (ja) * 1996-02-05 2008-02-13 シーメンス アクチエンゲゼルシヤフト 電界効果により制御可能の半導体デバイス
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5744994A (en) * 1996-05-15 1998-04-28 Siliconix Incorporated Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
KR0183886B1 (ko) * 1996-06-17 1999-04-15 김광호 반도체장치의 트렌치 소자분리 방법
JP3327135B2 (ja) * 1996-09-09 2002-09-24 日産自動車株式会社 電界効果トランジスタ
JP3607016B2 (ja) * 1996-10-02 2005-01-05 株式会社半導体エネルギー研究所 半導体装置およびその作製方法、並びに携帯型の情報処理端末、ヘッドマウントディスプレイ、ナビゲーションシステム、携帯電話、カメラおよびプロジェクター
JP3618517B2 (ja) * 1997-06-18 2005-02-09 三菱電機株式会社 半導体装置およびその製造方法
US5976947A (en) * 1997-08-18 1999-11-02 Micron Technology, Inc. Method for forming dielectric within a recess
US6239463B1 (en) * 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US6337499B1 (en) * 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
US6081009A (en) * 1997-11-10 2000-06-27 Intersil Corporation High voltage mosfet structure
DE19909282A1 (de) * 1998-03-06 1999-11-11 Nat Semiconductor Corp Verfahren zum Bilden einer Oxidisolationsstruktur in Silicium
KR100363530B1 (ko) * 1998-07-23 2002-12-05 미쓰비시덴키 가부시키가이샤 반도체 장치 및 그 제조 방법
US6291856B1 (en) * 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
DE19854915C2 (de) * 1998-11-27 2002-09-05 Infineon Technologies Ag MOS-Feldeffekttransistor mit Hilfselektrode
EP1011146B1 (en) * 1998-12-09 2006-03-08 STMicroelectronics S.r.l. Method of manufacturing an integrated edge structure for high voltage semiconductor devices
US6452230B1 (en) * 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
US6190970B1 (en) * 1999-01-04 2001-02-20 Industrial Technology Research Institute Method of making power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6222229B1 (en) * 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
EP1058303A1 (en) * 1999-05-31 2000-12-06 STMicroelectronics S.r.l. Fabrication of VDMOS structure with reduced parasitic effects
JP3851744B2 (ja) * 1999-06-28 2006-11-29 株式会社東芝 半導体装置の製造方法
DE19964214C2 (de) * 1999-09-07 2002-01-17 Infineon Technologies Ag Verfahren zur Herstellung einer Driftzone eines Kompensationsbauelements
GB9929613D0 (en) * 1999-12-15 2000-02-09 Koninkl Philips Electronics Nv Manufacture of semiconductor material and devices using that material
US6214698B1 (en) * 2000-01-11 2001-04-10 Taiwan Semiconductor Manufacturing Company Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer
US6392273B1 (en) * 2000-01-14 2002-05-21 Rockwell Science Center, Llc Trench insulated-gate bipolar transistor with improved safe-operating-area
GB0012138D0 (en) * 2000-05-20 2000-07-12 Koninkl Philips Electronics Nv A semiconductor device
US6399998B1 (en) * 2000-09-29 2002-06-04 Rockwell Technologies, Llc High voltage insulated-gate bipolar switch
JP4088033B2 (ja) * 2000-11-27 2008-05-21 株式会社東芝 半導体装置
US6509220B2 (en) * 2000-11-27 2003-01-21 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US6608350B2 (en) * 2000-12-07 2003-08-19 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6424007B1 (en) * 2001-01-24 2002-07-23 Power Integrations, Inc. High-voltage transistor with buried conduction layer
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
WO2002069394A1 (en) * 2001-02-27 2002-09-06 Fairchild Semiconductor Corporation Process for depositing and planarizing bpsg for dense trench mosfet application
US6512267B2 (en) * 2001-04-12 2003-01-28 International Rectifier Corporation Superjunction device with self compensated trench walls
US6551881B1 (en) * 2001-10-01 2003-04-22 Koninklijke Philips Electronics N.V. Self-aligned dual-oxide umosfet device and a method of fabricating same
ITTO20011038A1 (it) * 2001-10-30 2003-04-30 St Microelectronics Srl Procedimento per la fabbricazione di una fetta semiconduttrice integrante dispositivi elettronici e una struttura per il disaccoppiamento el
JP3993458B2 (ja) * 2002-04-17 2007-10-17 株式会社東芝 半導体装置
US7041560B2 (en) * 2003-12-19 2006-05-09 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device with conventional terminations
EP1721344A4 (en) * 2003-12-19 2009-06-10 Third Dimension 3D Sc Inc METHOD FOR PRODUCING A SUPERSHIP LAYERING COMPONENT
JP4999464B2 (ja) * 2003-12-19 2012-08-15 サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド 広いメサを備えた超接合ディバイスの製造方法
JP4417962B2 (ja) * 2003-12-19 2010-02-17 サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド 超接合デバイスの製造での平坦化方法
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
ES2710250T3 (es) * 2012-08-24 2019-04-23 Hoffmann La Roche Bomba de insulina y métodos de funcionamiento de la bomba de insulina

Also Published As

Publication number Publication date
US20050176192A1 (en) 2005-08-11
TW200535913A (en) 2005-11-01
US7199006B2 (en) 2007-04-03
JP2007515080A (ja) 2007-06-07
WO2005065144A2 (en) 2005-07-21
TWI353621B (en) 2011-12-01
WO2005065144A3 (en) 2006-03-02
EP1706899A2 (en) 2006-10-04
KR20070029656A (ko) 2007-03-14
EP1706899A4 (en) 2008-11-26
KR100879588B1 (ko) 2009-01-21

Similar Documents

Publication Publication Date Title
JP4417962B2 (ja) 超接合デバイスの製造での平坦化方法
JP4928947B2 (ja) 超接合デバイスの製造方法
JP5154347B2 (ja) 超接合半導体ディバイスおよび超接合半導体ディバイスの製造方法
US8372717B2 (en) Method for manufacturing a super-junction trench MOSFET with resurf stepped oxides and trenched contacts
CN101471264B (zh) 具有优化的可制造性的垂直功率器件的高压结构及方法
US8525255B2 (en) Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
TWI469348B (zh) 自對準方法製備的半導體功率裝置以及更加可靠的電接觸
JP4949851B2 (ja) エッチングで形成された溝を用いて厚い誘電体領域を形成する方法
CN102544100B (zh) 带有集成二极管的自对准沟槽mosfet
US5648283A (en) High density power device fabrication process using undercut oxide sidewalls
US8373224B2 (en) Super-junction trench MOSFET with resurf stepped oxides and trenched contacts
US8399921B2 (en) Metal oxide semiconductor (MOS) structure and manufacturing method thereof
JP5551213B2 (ja) 半導体装置の製造方法
CN102468276B (zh) 功率半导体组件的终端结构及其制作方法
JP2007515071A (ja) 広いメサを備えた超接合ディバイスの製造方法
JP2005521259A (ja) 単一のイオン打込み工程によって形成されたドープされたコラムを含む電圧維持領域を有するパワー半導体デバイス
JP2000252468A (ja) 埋め込みゲートを有するｍｏｓゲート装置およびその製造方法
JP2008546216A (ja) 電荷平衡電界効果トランジスタ
JP2004342660A (ja) 半導体装置及びその製造方法
JP2005514794A (ja) ドープカラムを含む高電圧電力ｍｏｓｆｅｔ
CN105321824A (zh) 半导体装置的制造方法
US9431286B1 (en) Deep trench with self-aligned sinker
CN118280842A (zh) 超结-沟槽栅mosfet器件及其制备方法
US11296222B2 (en) Lateral double diffused metal oxide semiconductor and method of fabricating same
CN112531026B (zh) 横向扩散金属氧化物半导体器件及其制造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070829

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20080530

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20080530

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080804

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20080804

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20080819

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081002

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20081225

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090202

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090402

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090702

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090709

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090929

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091105

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091126

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121204

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131204

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees