JP4365911B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP4365911B2
JP4365911B2 JP32020598A JP32020598A JP4365911B2 JP 4365911 B2 JP4365911 B2 JP 4365911B2 JP 32020598 A JP32020598 A JP 32020598A JP 32020598 A JP32020598 A JP 32020598A JP 4365911 B2 JP4365911 B2 JP 4365911B2
Authority
JP
Japan
Prior art keywords
input
circuit
node
logic circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32020598A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000149570A5 (https=
JP2000149570A (ja
Inventor
一男 金谷
博昭 南部
枢 山崎
武志 楠
恵一 日下田
邦彦 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP32020598A priority Critical patent/JP4365911B2/ja
Priority to US09/437,268 priority patent/US6369617B1/en
Publication of JP2000149570A publication Critical patent/JP2000149570A/ja
Priority to US09/840,190 priority patent/US6677782B2/en
Priority to US10/230,295 priority patent/US20020196053A1/en
Priority to US10/754,596 priority patent/US6998878B2/en
Publication of JP2000149570A5 publication Critical patent/JP2000149570A5/ja
Application granted granted Critical
Publication of JP4365911B2 publication Critical patent/JP4365911B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP32020598A 1998-11-11 1998-11-11 半導体集積回路 Expired - Fee Related JP4365911B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP32020598A JP4365911B2 (ja) 1998-11-11 1998-11-11 半導体集積回路
US09/437,268 US6369617B1 (en) 1998-11-11 1999-11-10 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit
US09/840,190 US6677782B2 (en) 1998-11-11 2001-04-24 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit
US10/230,295 US20020196053A1 (en) 1998-11-11 2002-08-29 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit
US10/754,596 US6998878B2 (en) 1998-11-11 2004-01-12 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32020598A JP4365911B2 (ja) 1998-11-11 1998-11-11 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2000149570A JP2000149570A (ja) 2000-05-30
JP2000149570A5 JP2000149570A5 (https=) 2005-12-22
JP4365911B2 true JP4365911B2 (ja) 2009-11-18

Family

ID=18118894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32020598A Expired - Fee Related JP4365911B2 (ja) 1998-11-11 1998-11-11 半導体集積回路

Country Status (2)

Country Link
US (4) US6369617B1 (https=)
JP (1) JP4365911B2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4365911B2 (ja) * 1998-11-11 2009-11-18 株式会社日立製作所 半導体集積回路
KR100379542B1 (ko) * 2000-11-23 2003-04-10 주식회사 하이닉스반도체 반도체 메모리소자의 테스트장치
US6980843B2 (en) * 2003-05-21 2005-12-27 Stereotaxis, Inc. Electrophysiology catheter
WO2005066742A1 (ja) * 2003-12-26 2005-07-21 Rohm Co., Ltd. 監視回路
US7176725B2 (en) * 2005-02-04 2007-02-13 International Business Machines Corporation Fast pulse powered NOR decode apparatus for semiconductor devices
US7342846B2 (en) * 2005-07-22 2008-03-11 Lattice Semiconductor Corporation Address decoding systems and methods
JP5034233B2 (ja) * 2005-12-28 2012-09-26 富士通株式会社 アドレスデコーダ，記憶装置，処理装置及び記憶装置におけるアドレスデコード方法
US7848173B1 (en) 2006-10-17 2010-12-07 Marvell International Ltd. Address decoder
US8324932B2 (en) * 2010-11-23 2012-12-04 Oracle International Corporation High-speed static XOR circuit
US12260900B2 (en) * 2022-06-24 2025-03-25 Changxin Memory Technologies, Inc. In-memory computing circuit and method, and semiconductor memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843836B2 (ja) * 1979-12-21 1983-09-29 富士通株式会社 デコ−ダ回路
US5291076A (en) 1992-08-31 1994-03-01 Motorola, Inc. Decoder/comparator and method of operation
JP3192010B2 (ja) * 1992-11-27 2001-07-23 株式会社日立製作所 デコード回路
US5373203A (en) 1993-04-05 1994-12-13 Motorola, Inc. Decoder and latching circuit with differential outputs
US5640108A (en) * 1995-06-07 1997-06-17 International Business Machines Corporation Single stage dynamic receiver/decoder
JP3178383B2 (ja) 1996-09-20 2001-06-18 株式会社日立製作所 同期型半導体論理回路
TW373174B (en) * 1996-09-20 1999-11-01 Hitachi Ltd Simultaneous semiconductor logical circuit
JP4365911B2 (ja) * 1998-11-11 2009-11-18 株式会社日立製作所 半導体集積回路

Also Published As

Publication number Publication date
US6369617B1 (en) 2002-04-09
US6998878B2 (en) 2006-02-14
US20020017923A1 (en) 2002-02-14
US20020196053A1 (en) 2002-12-26
US20040169527A1 (en) 2004-09-02
US6677782B2 (en) 2004-01-13
JP2000149570A (ja) 2000-05-30

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