JP4274688B2 - インピーダンス制御回路 - Google Patents

インピーダンス制御回路 Download PDF

Info

Publication number
JP4274688B2
JP4274688B2 JP2000505524A JP2000505524A JP4274688B2 JP 4274688 B2 JP4274688 B2 JP 4274688B2 JP 2000505524 A JP2000505524 A JP 2000505524A JP 2000505524 A JP2000505524 A JP 2000505524A JP 4274688 B2 JP4274688 B2 JP 4274688B2
Authority
JP
Japan
Prior art keywords
impedance
output buffer
buffer
signal
interface circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000505524A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001512296A (ja
JP2001512296A5 (enExample
Inventor
ムーニー，スティーブン・アール
ヘイコック，マシュー・ビィ
ケネディ，ジョセフ・ティ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2001512296A publication Critical patent/JP2001512296A/ja
Publication of JP2001512296A5 publication Critical patent/JP2001512296A5/ja
Application granted granted Critical
Publication of JP4274688B2 publication Critical patent/JP4274688B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Networks Using Active Elements (AREA)
JP2000505524A 1997-07-29 1998-07-17 インピーダンス制御回路 Expired - Fee Related JP4274688B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/902,345 US6087847A (en) 1997-07-29 1997-07-29 Impedance control circuit
US08/902,345 1997-07-29
PCT/US1998/014846 WO1999006845A2 (en) 1997-07-29 1998-07-17 Impedance control circuit

Publications (3)

Publication Number Publication Date
JP2001512296A JP2001512296A (ja) 2001-08-21
JP2001512296A5 JP2001512296A5 (enExample) 2006-01-05
JP4274688B2 true JP4274688B2 (ja) 2009-06-10

Family

ID=25415727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000505524A Expired - Fee Related JP4274688B2 (ja) 1997-07-29 1998-07-17 インピーダンス制御回路

Country Status (8)

Country Link
US (1) US6087847A (enExample)
EP (1) EP1010013B1 (enExample)
JP (1) JP4274688B2 (enExample)
KR (1) KR20010022326A (enExample)
AU (1) AU8495298A (enExample)
DE (1) DE69822479T2 (enExample)
TW (1) TW461995B (enExample)
WO (1) WO1999006845A2 (enExample)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6393062B1 (en) * 1998-09-21 2002-05-21 Maxim Integrated Products, Inc. Methods and circuits for generating a preemphasis waveform
US6343738B1 (en) * 1999-05-15 2002-02-05 John W. L. Ogilvie Automatic broker tools and techniques
JP4101973B2 (ja) * 1999-05-21 2008-06-18 株式会社ルネサステクノロジ 出力バッファ回路
US6292407B1 (en) * 1999-10-12 2001-09-18 Micron Technolgy, Inc. Method and apparatus for circuit variable updates
US6300789B1 (en) * 1999-12-22 2001-10-09 Intel Corporation Dynamic termination for non-symmetric transmission line network topologies
US6566903B1 (en) * 1999-12-28 2003-05-20 Intel Corporation Method and apparatus for dynamically controlling the performance of buffers under different performance conditions
US6331785B1 (en) * 2000-01-26 2001-12-18 Cirrus Logic, Inc. Polling to determine optimal impedance
US6501292B1 (en) * 2000-03-02 2002-12-31 Intel Corporation CMOS circuit for maintaining a constant slew rate
US6462588B2 (en) * 2000-04-03 2002-10-08 Rambus, Inc. Asymmetry control for an output driver
US6329836B1 (en) * 2000-05-26 2001-12-11 Sun Microsystems, Inc. Resistive arrayed high speed output driver with pre-distortion
US6392441B1 (en) * 2000-06-13 2002-05-21 Ramtron International Corporation Fast response circuit
US6624659B1 (en) * 2000-06-30 2003-09-23 Intel Corporation Dynamically updating impedance compensation code for input and output drivers
US7222208B1 (en) 2000-08-23 2007-05-22 Intel Corporation Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port
US6424175B1 (en) 2000-09-11 2002-07-23 Intel Corporation Biased control loop circuit for setting impedance of output driver
KR100356576B1 (ko) * 2000-09-15 2002-10-18 삼성전자 주식회사 프로그래머블 온 칩 터미네이션 동작을 갖는 프로그래머블데이터 출력회로 및 그 제어방법
US6445245B1 (en) 2000-10-06 2002-09-03 Xilinx, Inc. Digitally controlled impedance for I/O of an integrated circuit device
US6445170B1 (en) 2000-10-24 2002-09-03 Intel Corporation Current source with internal variable resistance and control loop for reduced process sensitivity
KR100391148B1 (ko) * 2000-11-02 2003-07-16 삼성전자주식회사 프로그래머블 임피던스 제어회로 및 방법
US6420899B1 (en) 2000-12-29 2002-07-16 Intel Corporation Dynamic impedance matched driver for improved slew rate and glitch termination
US6396301B1 (en) * 2001-01-19 2002-05-28 Dell Products L.P. Ground bounce prediction methodology and use of same in data error reduction
US6529041B1 (en) 2001-03-23 2003-03-04 Xilinx, Inc. System power control output circuit for programmable logic devices
US6448807B1 (en) 2001-03-29 2002-09-10 Intel Corporation Dynamic impedance controlled driver for improved slew rate and glitch termination
US6448811B1 (en) 2001-04-02 2002-09-10 Intel Corporation Integrated circuit current reference
US6507225B2 (en) 2001-04-16 2003-01-14 Intel Corporation Current mode driver with variable equalization
US6522174B2 (en) * 2001-04-16 2003-02-18 Intel Corporation Differential cascode current mode driver
US6545522B2 (en) * 2001-05-17 2003-04-08 Intel Corporation Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting
US6535047B2 (en) * 2001-05-17 2003-03-18 Intel Corporation Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
US6597233B2 (en) 2001-05-25 2003-07-22 International Business Machines Corporation Differential SCSI driver rise time and amplitude control circuit
US6791356B2 (en) * 2001-06-28 2004-09-14 Intel Corporation Bidirectional port with clock channel used for synchronization
US6603329B1 (en) 2001-08-29 2003-08-05 Altera Corporation Systems and methods for on-chip impedance termination
US6798237B1 (en) 2001-08-29 2004-09-28 Altera Corporation On-chip impedance matching circuit
US6529037B1 (en) 2001-09-13 2003-03-04 Intel Corporation Voltage mode bidirectional port with data channel used for synchronization
US6525569B1 (en) * 2001-09-21 2003-02-25 International Business Machines Corporation Driver circuit having shapable transition waveforms
US6590413B1 (en) 2001-10-03 2003-07-08 Altera Corporation Self-tracking integrated differential termination resistance
US6597198B2 (en) 2001-10-05 2003-07-22 Intel Corporation Current mode bidirectional port with data channel used for synchronization
US6812732B1 (en) 2001-12-04 2004-11-02 Altera Corporation Programmable parallel on-chip parallel termination impedance and impedance matching
US6836144B1 (en) 2001-12-10 2004-12-28 Altera Corporation Programmable series on-chip termination impedance and impedance matching
US7109744B1 (en) 2001-12-11 2006-09-19 Altera Corporation Programmable termination with DC voltage level control
US6812734B1 (en) 2001-12-11 2004-11-02 Altera Corporation Programmable termination with DC voltage level control
US6642742B1 (en) * 2002-03-21 2003-11-04 Advanced Micro Devices, Inc. Method and apparatus for controlling output impedance
JP4212309B2 (ja) * 2002-07-01 2009-01-21 株式会社ルネサステクノロジ 半導体集積回路
KR100495660B1 (ko) * 2002-07-05 2005-06-16 삼성전자주식회사 온-다이 종결 회로를 구비한 반도체 집적 회로 장치
US6836142B2 (en) 2002-07-12 2004-12-28 Xilinx, Inc. Asymmetric bidirectional bus implemented using an I/O device with a digitally controlled impedance
US6963218B1 (en) 2002-08-09 2005-11-08 Xilinx, Inc. Bi-directional interface and communication link
US7194559B2 (en) * 2002-08-29 2007-03-20 Intel Corporation Slave I/O driver calibration using error-nulling master reference
US6930506B2 (en) * 2002-10-22 2005-08-16 International Business Machines Corporation Terminating resistor driver for high speed data communication
US20040212399A1 (en) * 2002-11-29 2004-10-28 Daniel Mulligan Programmable driver for use in a multiple function handheld device
US6998875B2 (en) * 2002-12-10 2006-02-14 Ip-First, Llc Output driver impedance controller
US6985008B2 (en) * 2002-12-13 2006-01-10 Ip-First, Llc Apparatus and method for precisely controlling termination impedance
US6949949B2 (en) * 2002-12-17 2005-09-27 Ip-First, Llc Apparatus and method for adjusting the impedance of an output driver
US6788100B2 (en) * 2003-01-31 2004-09-07 Blueheron Semiconductor Corporation Resistor mirror
US7129738B2 (en) * 2003-03-04 2006-10-31 Micron Technology, Inc. Method and apparatus for calibrating driver impedance
JP4428504B2 (ja) * 2003-04-23 2010-03-10 株式会社ルネサステクノロジ 半導体集積回路装置
US20040263203A1 (en) * 2003-06-27 2004-12-30 Intel Corporation Signal compensation
US6888369B1 (en) 2003-07-17 2005-05-03 Altera Corporation Programmable on-chip differential termination impedance
US6888370B1 (en) 2003-08-20 2005-05-03 Altera Corporation Dynamically adjustable termination impedance control techniques
US6859064B1 (en) 2003-08-20 2005-02-22 Altera Corporation Techniques for reducing leakage current in on-chip impedance termination circuits
US7330993B2 (en) * 2003-09-29 2008-02-12 Intel Corporation Slew rate control mechanism
JP4086757B2 (ja) * 2003-10-23 2008-05-14 Ｎｅｃエレクトロニクス株式会社 半導体集積回路の入出力インターフェース回路
JP4290537B2 (ja) * 2003-11-26 2009-07-08 株式会社ルネサステクノロジ 半導体装置
WO2005064796A1 (en) * 2003-12-23 2005-07-14 Koninklijke Philips Electronics N.V. Load-aware circuit arrangement
TWI304529B (en) * 2004-01-30 2008-12-21 Realtek Semiconductor Corp Impedance control circuit and method thereof
KR100640782B1 (ko) * 2004-04-16 2006-11-06 주식회사 하이닉스반도체 반도체 기억 장치
US7248636B2 (en) * 2004-04-20 2007-07-24 Hewlett-Packard Development Company, L.P. Systems and methods for adjusting an output driver
US7126394B2 (en) * 2004-05-17 2006-10-24 Micron Technology, Inc. History-based slew rate control to reduce intersymbol interference
JP4536449B2 (ja) * 2004-07-29 2010-09-01 富士通株式会社 ドライバ回路、半導体装置、及び電子機器
FR2878665B1 (fr) * 2004-11-30 2007-05-25 St Microelectronics Rousset Circuit amplificateur a transconductance a gain negatif
US7218155B1 (en) 2005-01-20 2007-05-15 Altera Corporation Techniques for controlling on-chip termination resistance using voltage range detection
US7221193B1 (en) 2005-01-20 2007-05-22 Altera Corporation On-chip termination with calibrated driver strength
KR100702838B1 (ko) * 2005-05-09 2007-04-03 삼성전자주식회사 반도체 장치에서의 임피던스 콘트롤러블 출력 구동회로 및그에 따른 임피던스 콘트롤 방법
US7679397B1 (en) 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit
KR100746200B1 (ko) 2005-10-21 2007-08-06 삼성전자주식회사 소스 드라이버, 소스 드라이버 모듈, 및 디스플레이 장치
US8213894B2 (en) * 2005-12-29 2012-07-03 Intel Corporation Integrated circuit passive signal distribution
US20070252638A1 (en) * 2006-04-26 2007-11-01 Farrukh Aquil Method and apparatus for temperature compensating off chip driver (OCD) circuit
US7486104B2 (en) * 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
KR100733449B1 (ko) 2006-06-30 2007-06-28 주식회사 하이닉스반도체 반도체메모리소자의 온 다이 터미네이션
JP4958719B2 (ja) * 2006-10-20 2012-06-20 ルネサスエレクトロニクス株式会社 半導体集積回路
TW200910373A (en) 2007-06-08 2009-03-01 Mosaid Technologies Inc Dynamic impedance control for input/output buffers
US7550993B2 (en) * 2007-08-21 2009-06-23 Texas Instruments Incorporated Glitch reduced compensated circuits and methods for using such
US7876123B2 (en) 2007-10-09 2011-01-25 Lsi Corporation High speed multiple memory interface I/O cell
JP5059580B2 (ja) * 2007-12-20 2012-10-24 ルネサスエレクトロニクス株式会社 終端回路
JP5109647B2 (ja) * 2007-12-25 2012-12-26 凸版印刷株式会社 ドライバ回路
US7969181B1 (en) * 2008-02-03 2011-06-28 Freescale Semiconductor, Inc. Device and method for adjusting an impedance of an output driver of an integrated circuit
US7653505B1 (en) * 2008-03-14 2010-01-26 Xilinx, Inc. Method and apparatus for testing a controlled impedance buffer
US7443194B1 (en) * 2008-04-24 2008-10-28 International Business Machines Corporation I/O driver for integrated circuit with output impedance control
JP5584401B2 (ja) * 2008-08-23 2014-09-03 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びこれを備えるデータ処理システム
US7821290B2 (en) * 2008-09-26 2010-10-26 Vitesse Semiconductor Corporation Differential voltage mode driver and digital impedance caliberation of same
US20100164471A1 (en) * 2008-12-30 2010-07-01 M2000 Calibration of programmable i/o components using a virtual variable external resistor
US7888968B2 (en) * 2009-01-15 2011-02-15 International Business Machines Corporation Configurable pre-emphasis driver with selective constant and adjustable output impedance modes
US8030968B1 (en) * 2010-04-07 2011-10-04 Intel Corporation Staged predriver for high speed differential transmitter
JP2014146409A (ja) * 2014-03-12 2014-08-14 Ps4 Luxco S A R L 半導体集積回路装置及びその試験方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134311A (en) * 1990-06-07 1992-07-28 International Business Machines Corporation Self-adjusting impedance matching driver
US5243229A (en) * 1991-06-28 1993-09-07 At&T Bell Laboratories Digitally controlled element sizing
US5254883A (en) * 1992-04-22 1993-10-19 Rambus, Inc. Electrical current source circuitry for a bus
FR2709217B1 (fr) * 1993-08-19 1995-09-15 Bull Sa Procédé et dispositif d'adaptation d'impédance pour un émetteur et/ou récepteur, circuit intégré et système de transmission les mettant en Óoeuvre.
US5457407A (en) * 1994-07-06 1995-10-10 Sony Electronics Inc. Binary weighted reference circuit for a variable impedance output buffer
JP3484825B2 (ja) * 1995-06-09 2004-01-06 株式会社デンソー ドライバ回路
US5872471A (en) * 1995-12-25 1999-02-16 Hitachi, Ltd. Simultaneous bidirectional transmission circuit
US5666078A (en) * 1996-02-07 1997-09-09 International Business Machines Corporation Programmable impedance output driver
US5726583A (en) * 1996-07-19 1998-03-10 Kaplinsky; Cecil H. Programmable dynamic line-termination circuit

Also Published As

Publication number Publication date
US6087847A (en) 2000-07-11
DE69822479D1 (de) 2004-04-22
EP1010013A4 (en) 2000-10-18
JP2001512296A (ja) 2001-08-21
EP1010013A2 (en) 2000-06-21
DE69822479T2 (de) 2004-08-19
EP1010013B1 (en) 2004-03-17
AU8495298A (en) 1999-02-22
TW461995B (en) 2001-11-01
WO1999006845A3 (en) 1999-09-10
WO1999006845A2 (en) 1999-02-11
HK1027398A1 (en) 2001-01-12
KR20010022326A (ko) 2001-03-15

Similar Documents

Publication Publication Date Title
JP4274688B2 (ja) インピーダンス制御回路
CN103547978B (zh) 可配置多维驱动器及接收器
US6570931B1 (en) Switched voltage adaptive slew rate control and spectrum shaping transmitter for high speed digital transmission
US5898321A (en) Method and apparatus for slew rate and impedance compensating buffer circuits
Toifl et al. A 2.6 mW/Gbps 12.5 Gbps RX with 8-tap switched-capacitor DFE in 32 nm CMOS
US5877634A (en) CMOS buffer with controlled slew rate
JP4724117B2 (ja) 共通モードアイドル状態および選択可能なスルーレートを有するＴｘラインドライバ
JP2002199030A (ja) プリント回路基板、集積回路上の回路及び送信ラインの終端方法
CN103582853A (zh) 单端可配置多模式驱动器
US7038512B2 (en) Closed-loop independent DLL-controlled rise/fall time control circuit
KR100266902B1 (ko) 수신 장치 및 통신 장치의 전송 라인 종단 회로
US7038513B2 (en) Closed-loop independent DLL-controlled rise/fall time control circuit
US8144726B2 (en) Structure for out of band signaling enhancement for high speed serial driver
WO1996008871A1 (en) Controlled slew rate output buffer
JP3864255B2 (ja) インピーダンス制御方法および回路
US6980019B2 (en) Output buffer apparatus capable of adjusting output impedance in synchronization with data signal
US7157931B2 (en) Termination circuits having pull-down and pull-up circuits and related methods
JPH11112325A (ja) 出力バッファ回路
US20080111580A1 (en) Suppressing ringing in high speed CMOS output buffers driving transmission line load
EP0882265A1 (en) Apparatus and method for signal handling on gtl-type buses
HK1027398B (en) Impedance control circuit
JP3052914B2 (ja) Ｌｓｉの入力回路およびデジタル電子装置
WO1996001008A1 (en) Termination circuit for high speed applications
Ukaegbu et al. Perspective Chapter: Chip I/O Design Fundamentals, Methodologies and Challenges
JP3550045B2 (ja) 入力装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050712

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050712

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080219

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080519

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080924

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090203

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090303

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120313

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120313

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130313

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130313

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140313

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees