US6292407B1 - Method and apparatus for circuit variable updates - Google Patents
Method and apparatus for circuit variable updates Download PDFInfo
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- US6292407B1 US6292407B1 US09/416,301 US41630199A US6292407B1 US 6292407 B1 US6292407 B1 US 6292407B1 US 41630199 A US41630199 A US 41630199A US 6292407 B1 US6292407 B1 US 6292407B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
Definitions
- the present invention relates to electronic circuitry.
- the present invention relates to methods and structures for providing updates for circuit variables.
- Impedance matching is one of the design challenges facing the electronics industry due to multiple reflections on transmission lines, e.g., traces on a printed circuit board (PCB). Not limiting these multiple reflections can cause problems that can have an impact at the digital level, including increased delays, increased overshoot and increased ringing (i.e., oscillations) in the signal response.
- PCB printed circuit board
- One approach for matching the impedance between a circuit and the transmission line to which the circuit is coupled is to have an onboard controller on the circuit control the impedance.
- the onboard controller periodically updates the impedance of the data output of the circuit to which the transmission line is connected.
- the data output may be driving data at the point in time when the onboard controller completes the computation of the impedance and is attempting to update the impedance
- changing of the impedance value at the data output of the circuit may be hazardous.
- the impedance value at the data output is changing while the data output is transmitting data, intermediate values of the impedance are completely random and could result in values that are not close to the intended impedance for the data output.
- improved methods and structures are provided that allow for the updating of output driver impedances for a circuit to match the impedance of the transmission line to which the circuit is coupled. Additionally, improved methods and structures are provided which allow for a reliable updating of the output driver impedance without requiring the output driver to be tristated in order to prevent data loss.
- Embodiments of a method of forming an integrated circuit include coupling a data line to an enable input of a holding device.
- the method also includes coupling at least one impedance line to a data input of the holding device.
- the at least one impedance line carries an impedance signal.
- an impedance of the data line at a data output of the memory device is capable of being updated to a value equal to the impedance update signal when the data line is quiescent.
- quiescent is defined as inactivity (e.g., when the data line is tristated or is in a high impedance mode).
- the present invention also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application.
- FIG. 1 is one embodiment of an integrated circuit according to the teachings of the present invention.
- FIG. 2 is a timing diagram illustrating timing of embodiments of the present invention.
- FIG. 3 is one embodiment of impedance matching circuitry according to the teachings of the present invention.
- FIG. 4 is another embodiment of an integrated circuit according to the teachings of the present invention.
- FIG. 5 is one embodiment of an output buffer of an integrated circuit according to the teachings of the present invention.
- FIG. 6 is one embodiment of latching circuitry according to the teachings of the present invention.
- FIGS. 7 a - 7 b are timing diagrams illustrating timing of embodiments of the present invention.
- FIG. 8 is another embodiment of impedance matching circuitry according to the teachings of the present invention.
- FIG. 9 is a flow chart of method embodiments for impedance matching according to the teachings of the present invention.
- FIG. 10 is a block diagram of a computer system suitable for use in connection with the present invention.
- conductor is understood to include semiconductors
- insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors.
- holding device is understood to include a latch or a register. Additionally, the following description includes the terms logic zero and logic one. Typical logic systems switch or alternate an output voltage between just two significant voltage levels, labeled logic zero and logic one. Most logic systems use positive logic, in which logic zero is represented by zero volts (V), or a low voltage, e.g., below 0.5 V; and logic one is represented by a higher voltage.
- V zero volts
- logic one is represented by a higher voltage.
- signal line is understood to include a data line an address line a clock line or any other type of signal transmission line.
- bus is understood to include one to any number of transmission lines.
- FIG. 1 is one embodiment of an integrated circuit according to the teachings of the present invention.
- FIG. 1 illustrates integrated circuit 100 which is coupled to clock bus 118 and transmission line 116 .
- integrated circuit 100 includes data circuitry 102 , impedance logic circuitry 104 , inverter 106 , latch 108 , impedance matching circuitry 110 , data bus 112 , impedance logic bus 114 , latched impedance bus 120 and output data bus 122 .
- Data circuitry 102 is coupled to the input of inverter 106 through data bus 112 and is also coupled to impedance matching circuitry 110 through data bus 112 .
- Impedance logic circuitry 104 is coupled to a data input of latch 108 through impedance logic bus 114 , while the output of inverter 106 is coupled to an enable input of latch 108 .
- a data output of latch 108 is coupled to impedance matching circuitry 110 through latched impedance bus 120 .
- impedance matching circuitry 110 is coupled to transmission line 116 through output data bus 122 at data output 124 .
- FIG. 1 illustrates one inverter 106 , one latch 108 , one impedance matching circuitry 110 along with one line for the buses connecting such devices.
- integrated circuit 100 can include multiple transmission lines within data bus 112 , impedance logic bus 114 , latched impedance bus 120 and output data bus 122 . Accordingly, for each transmission line within buses 112 , 114 , 120 and 122 , integrated circuit 100 includes a corresponding inverter 106 , latch 108 and impedance matching circuitry 110 .
- Data circuitry 102 is any type of circuit within integrated circuit 100 which generates data.
- data circuitry 102 is a memory array within a memory device.
- latch 108 is a circuit in which the outputs follow the inputs when the circuit is enabled and holds the last value when the circuit is disabled, as is well-known in the art.
- impedance logic circuitry 104 is an onboard controller within integrated circuit 100 , which is well-known in the art.
- the onboard controller determines the impedance value for output data bus 122 that matches the impedance of transmission line 116 and transmits this value as a set of binary values (i.e., a binary code) through impedance logic bus 114 and latched impedance bus 120 to impedance matching circuitry 110 .
- a binary code i.e., a binary code
- impedance logic circuitry 104 generates a new impedance value based on the resistance value of a resistor which is externally coupled to an impedance pin of integrated circuit 100 , as is well-known in the art.
- integrated circuit 100 is designed such that the intended impedance value is approximately equal to 1 ⁇ 5 of the resistance value of the resistor externally coupled to integrated circuit 100 .
- the resistor has a resistance equal to approximately five times the intended impedance value (i.e., the impedance value of the transmission line which integrated circuit 100 is coupled).
- FIG. 2 includes a timing diagram for clock signal 202 transmitted on clock bus 118 , data signal 204 transmitted on data bus 112 , impedance logic signal 206 transmitted on impedance logic bus 114 , latched impedance signal 208 transmitted on latched impedance bus 120 and data output signal 210 transmitted on output data bus 122 .
- clock signal 202 produces a rising edge at clock signal point 212
- data circuitry 102 generates data that is transmitted as data signal 204 through data bus 112 to inverter 106 , which is shown as data signal 204 transitioning from a logic zero to a logic one at data signal point 214 .
- data signal 204 is transmitted to impedance matching circuitry 110 , which causes data output signal 210 to be transmitted out to transmission line 116 through output data bus 122 , which is shown as data output signal point 222 .
- impedance logic circuitry 104 causes impedance logic circuitry 104 to generate a new impedance value that is transmitted as impedance logic signal 206 (e.g., a binary code) through impedance logic bus 114 at impedance logic signal point 216 .
- impedance logic circuitry 104 generates a new impedance value to be transmitted on impedance logic bus 114 approximately every 512 clock cycles.
- integrated circuit 100 is designed such that impedance logic signal point 216 occurs subsequently to data signal point 214 .
- this design enables data signal 204 to be inverted through inverter 106 and to disable latch 108 prior to the arrival of impedance logic signal 206 at the data input of latch 108 .
- disablement of latch 108 causes latch 108 to delay the transmitting of the new impedance value as impedance logic signal 206 (e.g., a binary code). In turn, this precludes impedance matching circuitry 110 from updating the impedance of output data pins with this new impedance value while data bus 112 is passing data as data signal 204 . In other words, latched impedance signal 208 is precluded from transitioning by latch 108 while data signal 204 is a logic one (i.e., active). Therefore, impedance matching circuitry 110 only updates the impedance at the output data pins when data bus 112 is inactive.
- impedance matching circuitry 110 only updates the impedance at the output data pins when data bus 112 is inactive.
- impedance matching circuitry 110 applies the impedance value to the output data pins that was set prior to data bus 112 moving from an inactive to an active state. In other words, impedance matching circuitry 110 uses the prior (i.e., old) impedance value when data bus 112 is in an active state.
- data bus 112 passes a logic zero to inverter 106 which in turn enables latch 108 . Accordingly, latch 108 then latches impedance logic signal 206 to its data output as latched impedance signal 208 on latched impedance bus 120 , which causes the transition of latched impedance signal 208 at latched impedance signal point 220 .
- impedance matching circuitry 110 updates the impedance at data output 124 to match the impedance of transmission line 116 .
- the impedance at data output 124 is updated when output data bus 122 is quiescent (i.e., inactive); not while the output data bus 122 is transmitting data.
- FIG. 3 is one embodiment of impedance matching circuitry 110 according to the teachings of the present invention.
- FIG. 3 illustrates impedance matching circuitry 110 which is coupled to latched impedance bus 120 (which includes latched impedance lines 120 a ⁇ c ), data bus 112 , output data bus 122 , and upper voltage source 320 .
- Latched impedance lines 120 a-c are each respectively coupled to the input of inverters 308 - 312 .
- the output of inverters 308 - 312 are respectively coupled to the gates of transistors 314 - 318 .
- the sources of transistors 314 - 318 are coupled to upper voltage source 320 while the drains of transistors 314 - 318 are coupled to the source of transistor 322 .
- impedance matching circuitry 110 includes inverter 324 whose input is coupled to data bus 112 .
- the output of inverter 324 is coupled to the gate of transistor 322 .
- the drain of transistor 322 is coupled to output data bus 122 .
- transistors 314 - 318 and 322 are p-type metal oxide semiconductor field effect transistors (p-MOSFETs).
- Impedance matching circuitry 110 is designed such that transistors 314 - 318 have varying impedances. Accordingly, the level of impedance at output data bus 122 is dependent on which and how many of transistors 314 - 318 are turned on. In particular, impedance matching circuitry 110 receives a binary code from latched impedance bus 120 . Latched impedances lines 120 a-c each transmit a logic one or a logic zero, which causes transistors 314 - 318 to turn on or off, respectively. Accordingly, when data bus 112 transitions high, output data bus 122 receives a current flow from voltage source 320 which is dependent on the impedance level which is set by which and how many of transistors 314 - 318 are turned on.
- the impedance level at output data bus 122 is set by the binary code transmitted on latched impedance lines 120 - a-c . Therefore, impedance logic circuitry 104 determines the impedance level at output data bus 122 that matches the impedance of transmission line 116 and transmits this impedance level as a binary code to impedance matching circuitry 110 along latched impedance bus 120 . Accordingly, impedance matching circuitry 110 matches the impedance level at the output data bus 122 to the impedance level of transmission line 116 .
- FIG. 4 is another embodiment of an integrated circuit according to the teachings of the present invention.
- FIG. 4 illustrates memory device 400 which is coupled to address bus 412 , clock bus 414 , read/write bus 416 , transmission line 418 and resistor 420 .
- Memory device 400 includes memory array 402 , decode/control circuitry 404 , input buffers 406 , impedance logic circuitry 408 and output buffers 410 .
- memory device 400 includes decode/control bus 422 , input bus 424 , pulldown data bus 426 , pullup data bus 428 , output pulldown data bus 430 , output pullup data bus 432 , pulldown impedance logic bus 434 , pullup impedance logic bus 436 , output impedance pin 438 and data output 440 .
- Address bus 412 , clock bus 414 and read/write bus 416 are coupled to decode/control circuitry 404 .
- decode/logic circuitry 404 is coupled to memory array 402 , input buffers 406 , impedance logic circuitry 408 and output buffers 410 through decode/control bus 422 .
- Input buffers 406 are coupled to memory array 402 through input bus 424 .
- memory array 402 is coupled to output buffers 410 through pulldown data bus 426 and pullup data bus 428
- impedance logic circuitry 408 is coupled to output buffers 410 through pulldown impedance logic bus 434 and pullup impedance logic bus 436 .
- impedance logic circuitry 408 is coupled to resistor 420 through output impedance pin 438
- output buffers 410 are coupled to transmission line 418 through output pulldown data bus 430 and output pullup data bus 432 at data output 440 .
- FIG. 5 includes latching circuitry 502 and impedance matching circuitry 504 .
- Latching circuitry 502 is coupled to memory array 402 through pulldown data bus 426 and pullup data bus 428 .
- latching circuitry 502 is coupled to impedance logic circuitry 408 through pulldown impedance logic bus 434 and pullup impedance logic bus 436 .
- Impedance matching circuitry 504 is coupled to latching circuitry 502 through pulldown data bus 426 , pullup data bus 428 as well as pulldown latched impedance bus 506 and pullup latched impedance bus 508 .
- impedance matching circuitry 504 is coupled to transmission line 418 through output pulldown data bus 430 and output pullup data bus 432 at data output 440 .
- FIG. 6 illustrates one embodiment of latching circuitry 502 of FIG. 5 .
- FIG. 6 includes pullup latch 602 , pulldown latch 604 and inverters 606 - 608 .
- the input of inverter 606 is coupled to memory array 402 through pullup data bus 428 , while the output of inverter 606 is coupled to the enable input of pullup latch 602 .
- the data input of pullup latch 602 is coupled to impedance logic circuitry 408 through pullup impedance logic bus 436 .
- the input of inverter 608 is coupled to memory array 402 through pulldown data bus 426 , while the output of inverter 608 is coupled to the enable input of pulldown latch 604 .
- pulldown latch 604 The data input of pulldown latch 604 is coupled to impedance logic circuitry 408 through pulldown impedance logic bus 434 . Furthermore, the output of latching circuitry 502 illustrated in FIG. 6 includes pullup data bus 428 , pulldown data bus 426 as well as pullup latched impedance bus 508 and pulldown latched impedance bus 506 , which are the coupled to the data output of pullup latch 602 and pulldown latch 604 , respectively.
- FIG. 7 a illustrates the timing sequences when a signal on pullup data bus 428 transitions to a logic one caused by a signal on clock bus 414 transitioning to a logic one.
- FIG. 7 b illustrates the timing sequences when a signal on pulldown data bus 426 transitions to a logic one causing a signal on clock bus 414 transitioning to a logic one.
- FIG. 7 a includes timing diagrams for (1) clock signal 702 transmitted on clock bus 414 , (2) pullup data signal 704 transmitted on pullup data bus 428 , (3) pulldown data signal 706 transmitted on pulldown data bus 426 , (4) pullup impedance logic signal 708 transmitted on pullup impedance logic bus 436 , (5) pulldown impedance logic signal 710 transmitted on pulldown impedance logic bus 434 , (6) pullup latched impedance signal 712 transmitted on pullup latched impedance bus 508 , (7) pulldown latched impedance signal 714 transmitted on pulldown latched impedance bus 506 and (8) data output signal 716 transmitted on output pulldown data bus 430 and output pullup data bus 432 at data output 440 .
- memory array 402 transmits data to output buffers 410 through pullup data bus 428 and pulldown data bus 426 , which corresponds to the data located at the address on address bus 412 .
- this causes pullup data signal 704 to transition from logic zero to logic one at pullup data signal point 720 and pulldown data signal 706 to transition from logic one to logic zero at pulldown data signal point 722 .
- output buffers 410 transmits this data through latch circuitry 502 and impedance matching circuitry 504 out to transmission line 418 at data output 440 through output pulldown data bus 430 and output pullup data bus 432 , which is shown at data output signal point 724 of data output signal 716 .
- impedance logic circuitry 408 causes impedance logic circuitry 408 to generate a new impedance value for both the pullup and pulldown portion of data output 440 .
- impedance logic circuitry 408 generates a new impedance value based on the resistance value of resistor 420 , as is well-known in the art.
- impedance logic circuitry 408 is designed such that the intended impedance value is approximately equal to 1 ⁇ 5 of the resistance value of resistor 420 externally coupled to memory device 400 .
- resistor 420 has a resistance equal to approximately 5 times the intended impedance value (i.e., the impedance value of transmission line 418 which memory device 400 is coupled).
- Impedance logic circuitry 408 then transmits this value as pullup impedance logic signal 708 through pullup impedance logic bus 436 and as pulldown impedance logic signal 710 through pulldown impedance logic bus 434 .
- pullup impedance logic signal 708 transitions at pullup impedance logic signal point 732
- pulldown impedance logic signal 710 transitions at pulldown impedance logic signal point 740 .
- impedance logic circuitry 408 generates a new impedance value to be transmitted on pullup impedance logic bus 436 and pulldown impedance logic bus 434 approximately every 512 clock cycles.
- pulldown latch 604 becomes active (i.e., pulldown latch 604 is open). Accordingly, pulldown latch 604 passes pulldown impedance logic signal 710 to its data output as pulldown latch impedance signal 714 on pulldown latched impedance bus 506 , which causes the transition of pulldown latched impedance signal 714 at pulldown latched impedance signal point 738 .
- impedance matching circuitry 504 updates the impedance at data output 440 for the pulldown portion of the data output signal to match the impedance of transmission line 418 .
- the impedance at data output 440 for the pulldown portion of the data output signal is updated when output pulldown data bus 430 is quiescent (i.e., inactive); not while output pulldown data bus 430 is transmitting data.
- memory device 400 is designed such that pullup impedance logic signal point 732 occurs subsequently to pullup data signal point 720 .
- this design enables pullup data signal 704 to be inverted through inverter 606 and to close pullup latch 602 prior to the arrival of pullup impedance logic signal 708 at the data input of latch 602 .
- pullup latch 602 causes pullup latch 602 to delay the new impedance value being transmitted as pullup impedance logic signal 708 .
- pullup latched impedance signal 712 is precluded from transitioning by pullup latch 602 while pullup data signal 704 is high or active. Therefore, impedance matching circuitry 504 only updates the impedance for the pullup portion of data output 440 when pullup data bus 432 is inactive.
- impedance matching circuitry 504 when pullup data bus 432 is active, applies the impedance value at the pullup portion of data output 440 that was set prior to pullup data bus 432 moving from an inactive to an active state. In other words, impedance matching circuitry 504 uses the prior (i.e., old) impedance value for the pullup portion of data output 440 when pullup data bus 432 is in an active state.
- pullup data bus 428 passes a logic zero to inverter 606 which in turn enables pullup latch 602 . Accordingly, pullup latch 602 then passes pullup impedance logic signal 708 , to its data output as pullup latched impedance signal 712 on pullup latched impedance bus 508 , which causes the transition of pullup latched impedance signal 712 at pullup latched impedance signal point 736 .
- impedance matching circuitry 504 updates the impedance at data output 440 for the pullup portion of the data output signal to match the impedance of transmission line 418 .
- the impedance at data output 440 for the pullup portion of the data output signal is updated when output pullup data bus 432 is quiescent (i.e., inactive); not while output pullup data bus 432 is transmitting data.
- FIG. 7 b the timing diagrams of FIG. 7 b illustrate the timing sequences when a signal on pulldown data bus 426 transitions to a logic one when a signal on clock bus 414 transitions to a logic one.
- FIG. 7 b illustrate the timing sequences when a signal on pulldown data bus 426 transitions to a logic one when a signal on clock bus 414 transitions to a logic one.
- 7 b includes timing diagrams for (1) clock signal 702 transmitted on clock bus 414 , (2) pullup data signal 704 transmitted on pullup data bus 428 , (3) pulldown data signal 706 transmitted on pulldown data bus 426 , (4) pullup impedance logic signal 708 transmitted on pullup impedance logic bus 436 (5) pulldown impedance logic signal 710 transmitted on pulldown impedance logic bus 434 , (6) pullup latched impedance signal 712 transmitted on pullup latched impedance bus 508 , (7) pulldown latched impedance signal 714 transmitted on pulldown latched impedance bus 506 and (8) data output signal 716 transmitted on output pulldown data bus 430 and output pullup data bus 432 at data output 440 .
- memory array 402 transmits data to output buffers 410 through pullup data bus 428 and pulldown data bus 426 , which corresponds to the data located at the address on address bus 412 .
- this causes pulldown data signal 706 to transition from logic zero to logic one at pullup data signal point 752 and pullup data signal 704 to transition from logic one to logic zero at pullup data signal point 754 .
- output buffers 410 transmits this data through latching circuitry 502 and impedance matching circuitry 504 out to transmission line 418 at data output 440 through output pulldown data bus 430 and output pullup data bus 432 , which is shown at data output signal point 756 of data output signal 716 .
- impedance logic circuitry 408 causes impedance logic circuitry 408 to generate a new impedance value for both the pullup and pulldown portion of data output 440 .
- impedance logic circuitry 408 generates a new impedance value based on the resistance value of resistor 420 , as is well-known in the art.
- impedance logic circuitry 408 is designed such that the intended impedance value is approximately equal to 1 ⁇ 5 of the resistance value of resistor 420 externally coupled to memory device 400 .
- resistor 420 has a resistance equal to approximately 5 times the intended impedance value (i.e., the impedance value of transmission line 418 which memory device 400 is coupled).
- Impedance logic circuitry 408 then transmits this value as pullup impedance logic signal 708 through pullup impedance logic bus 436 and as pulldown impedance logic signal 710 through pulldown impedance logic bus 434 .
- pullup impedance logic signal 708 transitions at pullup impedance logic signal point 766
- pulldown impedance logic signal 710 transitions at pulldown impedance logic signal point 762 .
- impedance logic circuitry 408 generates a new impedance value to be transmitted on pullup impedance logic bus 436 and pulldown impedance logic bus 434 approximately every 512 clock cycles.
- pullup latch 602 becomes active (i.e., pullup latch 602 is open). Accordingly, pullup latch 602 passes pullup impedance logic signal 708 to its data output as pullup latched impedance signal 712 on pullup latched impedance bus 508 , which causes the transition of pullup latched impedance signal 712 at pullup latched impedance signal point 768 .
- impedance matching circuitry 504 updates the impedance at data output 440 for the pullup portion of the data output signal to match the impedance of transmission line 418 .
- the impedance at data output 440 for the pullup portion of the data output signal is updated when output pullup data bus 432 is quiescent (i.e., inactive); not while output pullup data bus 432 is transmitting data.
- memory device 400 is designed such that pulldown impedance logic signal point 762 occurs subsequently to pulldown data signal point 752 .
- this design enables pulldown data signal 706 to be inverted through inverter 608 and to close pulldown latch 604 prior to the arrival of pulldown impedance logic signal 710 at the data input of pulldown latch 604 .
- pulldown latch 604 causes pulldown latch 604 to delay the new impedance value being transmitted as pulldown impedance logic signal 710 .
- this precludes impedance matching circuitry 504 from updating the impedance of output pulldown data bus 430 at data output 440 .
- pulldown latched impedance signal 714 is precluded from transitioning by pulldown latch 604 while pulldown data signal 706 is high or active. Therefore, impedance matching circuitry 504 only updates the impedance for the pulldown portion of data output 440 when pulldown data bus 430 is inactive.
- impedance matching circuitry 504 when output pulldown data bus 430 is active, applies the impedance value at the pulldown portion of data output 440 that was set prior to pulldown data bus 430 moving from an inactive to an active state. In other words, impedance matching circuitry 504 uses the prior (i.e., old) impedance value for the pulldown portion of data output 440 when pulldown data bus 430 is in an active state.
- pulldown data bus 426 passes a logic zero to inverter 608 which in turn enables pulldown latch 604 . Accordingly, pulldown latch 604 then passes pulldown impedance logic signal 710 to its data output as pulldown latched impedance signal 714 on pulldown latched impedance bus 506 , which causes the transition of pulldown latched impedance signal 714 at pulldown latched impedance signal point 764 .
- impedance matching circuitry 504 updates the impedance at data output 440 for the pulldown portion of the data output signal to match the impedance of transmission line 418 .
- the impedance at data output 440 for the pulldown portion of the data output signal is updated when output pulldown data bus 430 is quiescent (i.e., inactive); not while output pulldown data bus 430 is transmitting data.
- FIG. 8 is one embodiment of impedance matching circuitry 504 according to the teachings of the present invention.
- FIG. 8 illustrates impedance matching circuitry 504 which is coupled to (1) pullup latched impedance bus 508 , which includes pullup latched impedance lines 508 a-c , (2) pulldown latched impedance bus 506 , which includes pulldown latched impedance lines 506 a-c , (3) pullup data bus 428 , (4) pulldown data bus 426 , (5) upper voltage source 826 and (6) lower voltage source 828 .
- Pullup latched impedance lines 508 a-c are each respectively coupled to the input of inverters 802 - 806 .
- the output of inverters 802 - 806 are respectively coupled to the gates of transistors 808 - 812 .
- the sources of transistors 808 - 812 are coupled to upper voltage source 826 while the drains of transistors 808 - 812 are coupled to the source of transistor 816 .
- impedance matching circuitry 504 includes inverter 814 whose input is coupled to pullup data bus 428 .
- the output of inverter 814 is coupled to the gate of transistor 816 .
- the drain of transistor 816 is coupled to output pullup data bus 432 .
- transistors 808 - 812 and 816 are p-MOSFETs.
- the drain of transistor 818 is coupled to output pulldown data bus 430 .
- the gate of transistor 818 is coupled to pulldown data bus 426 and the source of transistor 818 is coupled to the drain of transistors 820 - 824 .
- pulldown latched impedance lines 506 a-c are each respectively coupled to the gates of transistors 820 - 824 .
- the source of transistors 820 - 824 are coupled to lower voltage source 828 .
- transistors 818 and 820 - 824 are n-MOSFETs.
- Impedance matching circuitry 504 is designed such that transistors 808 - 812 have various impedances. Accordingly, the level of impedance at data output 440 for the pullup portion of the data output signal is dependent on which and how many transistors 808 - 812 are turned on. In particular, impedance matching circuitry 504 receives a binary code from pullup impedance logic bus 436 . Multiple lines within pullup impedance logic bus 436 each transmit a high or a low value, which causes transistors 808 - 812 to turn on or off, respectively.
- output pullup data bus 432 receives a current flow from upper voltage source 826 which is dependent on the impedance level which is set by which and how many of transistors 808 - 812 are turned on.
- the impedance level for the pullup portion of the data output signal is set by the binary code transmitted on pullup latched impedance bus 508 .
- impedance logic circuitry 408 determines the impedance level at output pullup data bus 432 that matches the impedance of transmission line 418 , using techniques well-known in the art, and transmits this impedance level as a binary code to impedance matching circuitry 504 along pullup latched impedance bus 508 . Accordingly, impedance matching circuitry 504 matches the impedance level for the pullup portion of the data output signal to the impedance level of transmission line 418 .
- impedance matching circuitry 504 is designed such that transistors 820 - 824 have various impedances. Accordingly, the level of impedance at data output 440 for the pulldown portion of the data output signal is dependent on which and how many transistors 820 - 824 are turned on. In particular, impedance matching circuitry 504 receives a binary code from pulldown impedance logic bus 434 . Multiple lines within pulldown impedance logic bus 434 each transmit a high or a low value, which causes transistors 820 - 824 to turn on or off, respectively.
- output pulldown data bus 430 receives a current flow from lower voltage source 828 which is dependent on the impedance level which is set by which and how many of transistors 820 - 824 are turned on.
- the impedance level for the pulldown portion of the data output signal is set by the binary code transmitted on pulldown latched impedance bus 506 .
- impedance logic circuitry 408 determines the impedance level at output pulldown data bus 430 that matches the impedance of transmission line 418 , using techniques well-known in the art, and transmits this impedance level as a binary code to impedance matching circuitry 504 along pulldown latched impedance bus 506 . Accordingly, impedance matching circuitry 504 matches the impedance level for the pulldown portion of the data output signal to the impedance level of transmission line 418 .
- FIG. 9 is a flowchart of method embodiments for impedance matching according to the teachings of the present invention.
- a data line is sensed.
- the data line is sensed (i.e., checked) to determined whether data is being transmitted on such data line.
- the data line is sensed by latching circuitry to determine whether to delay or pass the latched impedance signal.
- the latched impedance signal is computed by an onboard controller, as is known in the art.
- the latched impedance signal is delayed in a latch when a data line is transmitting a data signal.
- the impedance is updated.
- the impedance of the data output of the circuit is updated when the latched impedance signal is passed and thereby allowing impedance matching circuitry to update the impedance value of the data output to match the impedance of the transmission line.
- the impedance value for the data output is only updated when the data line coupled to such data output is not transmitting data (i.e., the data line is quiescent). Moreover, when the data line is active, the impedance matching circuitry applies the impedance value to the data output that was set prior to the data line moving from an inactive to an active state. In other words, the impedance matching circuitry used the prior (i.e., old) impedance value when the data line is in an active state.
- FIG. 10 is a block diagram of electronic system 1000 suitable for use in connection with the present invention.
- Electronic system 1000 comprises processor 1002 , input/output (I/O) controller 1004 , disk drive controller 1006 and memory 1008 .
- I/O input/output
- Transmission line 1010 couples together processor 1002 , input/output (I/O) controller 1004 , disk drive controller 1006 and memory 1008 .
- processor 1002 , input/output (I/O) controller 1004 , disk drive controller 1006 and/or memory 1008 include one or more latching circuitry for updating the impedance to match the impedance of transmission line 1010 , described above in conjunction with FIG. 1-8.
- processor 1002 , input/output (I/O) controller 1004 , disk drive controller 1006 and/or memory 1008 can include latching circuitry that matches impedance between transmission lines that are internal to their circuitry.
- Embodiments of the present invention were applied to either one or two signal lines. However, this is by way of illustration and not by way of limitation as embodiments of the present application can be applied to any number of signal lines. Further, the detailed description illustrates the updating or matching of an impedance. However, the invention is not so limited as embodiments of the present invention can be used to update other circuit variables (e.g., voltage, current or frequency).
- circuit variables e.g., voltage, current or frequency
- improved methods and structures are provided that allow for the updating of output driver impedances for a circuit to match the impedance of the transmission line to which the circuit is coupled.
- improved methods and structures are provided which allow for a reliable updating of the output driver impedance without requiring the output driver to be tristated in order to prevent data loss.
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Abstract
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US09/416,301 US6292407B1 (en) | 1999-10-12 | 1999-10-12 | Method and apparatus for circuit variable updates |
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US09/416,301 US6292407B1 (en) | 1999-10-12 | 1999-10-12 | Method and apparatus for circuit variable updates |
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