JP4214775B2 - 半導体装置特性シミュレーション方法及び半導体装置特性シミュレータ - Google Patents

半導体装置特性シミュレーション方法及び半導体装置特性シミュレータ Download PDF

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JP4214775B2
JP4214775B2 JP2002368046A JP2002368046A JP4214775B2 JP 4214775 B2 JP4214775 B2 JP 4214775B2 JP 2002368046 A JP2002368046 A JP 2002368046A JP 2002368046 A JP2002368046 A JP 2002368046A JP 4214775 B2 JP4214775 B2 JP 4214775B2
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transistor
deterioration
amount
gate voltage
simulation
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JP2004200461A (ja
JP2004200461A5 (enExample
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弘樹 臼井
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Sony Corp
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Sony Corp
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Priority to JP2002368046A priority Critical patent/JP4214775B2/ja
Priority to TW092135987A priority patent/TWI236040B/zh
Priority to US10/502,621 priority patent/US7240308B2/en
Priority to PCT/JP2003/016385 priority patent/WO2004057652A1/ja
Priority to CNB2003801002555A priority patent/CN100401461C/zh
Priority to KR1020047012901A priority patent/KR20050083556A/ko
Publication of JP2004200461A publication Critical patent/JP2004200461A/ja
Publication of JP2004200461A5 publication Critical patent/JP2004200461A5/ja
Priority to US11/796,262 priority patent/US20070209027A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
JP2002368046A 2002-12-19 2002-12-19 半導体装置特性シミュレーション方法及び半導体装置特性シミュレータ Expired - Fee Related JP4214775B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2002368046A JP4214775B2 (ja) 2002-12-19 2002-12-19 半導体装置特性シミュレーション方法及び半導体装置特性シミュレータ
TW092135987A TWI236040B (en) 2002-12-19 2003-12-18 Simulation method and simulator of semiconductor circuit device
PCT/JP2003/016385 WO2004057652A1 (ja) 2002-12-19 2003-12-19 半導体回路装置のシミュレーション方法および半導体回路装置のシミュレータ
CNB2003801002555A CN100401461C (zh) 2002-12-19 2003-12-19 半导体电路器件模拟方法和半导体电路器件模拟器
US10/502,621 US7240308B2 (en) 2002-12-19 2003-12-19 Simulation method for semiconductor circuit device and simulator for semiconductor circuit device
KR1020047012901A KR20050083556A (ko) 2002-12-19 2003-12-19 반도체 회로 장치의 시뮬레이션 방법 및 반도체 회로장치의 시뮬레이터
US11/796,262 US20070209027A1 (en) 2002-12-19 2007-04-27 Simulation method for semiconductor circuit device and simulator for semiconductor circuit device

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Application Number Priority Date Filing Date Title
JP2002368046A JP4214775B2 (ja) 2002-12-19 2002-12-19 半導体装置特性シミュレーション方法及び半導体装置特性シミュレータ

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JP2004200461A JP2004200461A (ja) 2004-07-15
JP2004200461A5 JP2004200461A5 (enExample) 2005-04-07
JP4214775B2 true JP4214775B2 (ja) 2009-01-28

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US (2) US7240308B2 (enExample)
JP (1) JP4214775B2 (enExample)
KR (1) KR20050083556A (enExample)
CN (1) CN100401461C (enExample)
TW (1) TWI236040B (enExample)
WO (1) WO2004057652A1 (enExample)

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US7353471B1 (en) * 2004-08-05 2008-04-01 Gradient Design Automation Inc. Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance
WO2007070879A1 (en) * 2005-12-17 2007-06-21 Gradient Design Automation, Inc. Simulation of ic temperature distributions using an adaptive 3d grid
US7472363B1 (en) * 2004-01-28 2008-12-30 Gradient Design Automation Inc. Semiconductor chip design having thermal awareness across multiple sub-system domains
US20090048801A1 (en) * 2004-01-28 2009-02-19 Rajit Chandra Method and apparatus for generating thermal test vectors
US7458052B1 (en) 2004-08-30 2008-11-25 Gradient Design Automation, Inc. Method and apparatus for normalizing thermal gradients over semiconductor chip designs
US20090224356A1 (en) * 2004-01-28 2009-09-10 Rajit Chandra Method and apparatus for thermally aware design improvement
US7203920B2 (en) * 2004-01-28 2007-04-10 Gradient Design Automation Inc. Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities
US20090077508A1 (en) * 2004-01-28 2009-03-19 Rubin Daniel I Accelerated life testing of semiconductor chips
US7383520B2 (en) * 2004-08-05 2008-06-03 Gradient Design Automation Inc. Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs
US8019580B1 (en) 2007-04-12 2011-09-13 Gradient Design Automation Inc. Transient thermal analysis
US8286111B2 (en) * 2004-03-11 2012-10-09 Gradient Design Automation Inc. Thermal simulation using adaptive 3D and hierarchical grid mechanisms
US7296247B1 (en) * 2004-08-17 2007-11-13 Xilinx, Inc. Method and apparatus to improve pass transistor performance
JP2006140284A (ja) * 2004-11-11 2006-06-01 Matsushita Electric Ind Co Ltd 半導体装置の信頼性シミュレーション方法及び信頼性シミュレータ
JP2008053692A (ja) * 2006-07-28 2008-03-06 Matsushita Electric Ind Co Ltd トランジスタのｂｔ劣化のシミュレーションモデルおよびシミュレーションモデル化方法
US7594210B2 (en) * 2006-11-16 2009-09-22 Clk Design Automation, Inc. Timing variation characterization
US7793243B1 (en) 2006-12-04 2010-09-07 Clk Design Automation, Inc. Multi-engine static analysis
US7600204B1 (en) * 2007-02-14 2009-10-06 Xilinx, Inc. Method for simulation of negative bias and temperature instability
US8935146B2 (en) * 2007-03-05 2015-01-13 Fujitsu Semiconductor Limited Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter
JP4563501B2 (ja) * 2007-06-20 2010-10-13 富士通株式会社 回路シミュレーションモデル生成装置、回路シミュレーションモデル生成プログラム、回路シミュレーションモデル生成方法及び回路シミュレーション装置
US7750400B2 (en) 2008-08-15 2010-07-06 Texas Instruments Incorporated Integrated circuit modeling, design, and fabrication based on degradation mechanisms
KR101478554B1 (ko) * 2008-10-02 2015-01-06 삼성전자 주식회사 오버 슈트 전압의 산출 방법 및 그를 이용한 게이트 절연막열화분석방법
CN101739471B (zh) * 2008-11-13 2011-09-28 上海华虹Nec电子有限公司 双极型晶体管工艺偏差模型参数的在线测试及提取方法
CN102054066B (zh) * 2009-10-30 2015-12-09 新思科技(上海)有限公司 集成电路的退化分析方法及装置
JP5394943B2 (ja) * 2010-01-15 2014-01-22 ラピスセミコンダクタ株式会社 試験結果記憶方法、試験結果表示方法、及び試験結果表示装置
CN102437025B (zh) * 2011-12-02 2013-04-24 南京大学 一种消除pmos中负偏压温度不稳定性影响的方法
US9323870B2 (en) 2012-05-01 2016-04-26 Advanced Micro Devices, Inc. Method and apparatus for improved integrated circuit temperature evaluation and IC design
US20140095126A1 (en) * 2012-10-03 2014-04-03 Lsi Corporation Hot-carrier injection reliability checks based on gate voltage dependency
US20140304445A1 (en) * 2013-04-09 2014-10-09 William Michael Gervasi Memory bus loading and conditioning module
CN103324813B (zh) * 2013-07-11 2016-01-20 深圳大学 Mos器件非均匀界面退化电荷的数值模拟方法及系统
US9857409B2 (en) 2013-08-27 2018-01-02 Synopsys, Inc. Negative bias thermal instability stress testing of transistors
CN104699880B (zh) * 2013-12-10 2018-06-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的评估方法和rc时序测试方法
CN103744008B (zh) * 2013-12-12 2016-02-03 华为技术有限公司 确定电路老化性能的方法和装置
KR102268591B1 (ko) * 2014-08-18 2021-06-25 삼성전자주식회사 회로의 자가 발열 특성을 예측하는 시뮬레이션 시스템 및 그것의 회로 설계 방법
US9996650B2 (en) 2015-03-17 2018-06-12 International Business Machines Corporation Modeling the performance of a field effect transistor having a dynamically depleted channel region
CN105067985B (zh) * 2015-07-22 2018-01-02 工业和信息化部电子第五研究所 基于nbti效应pmos管参数退化的失效预警装置
US10621494B2 (en) * 2017-11-08 2020-04-14 Samsung Electronics Co., Ltd. System and method for circuit simulation based on recurrent neural networks

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JP2001267260A (ja) * 2000-03-22 2001-09-28 Oki Electric Ind Co Ltd 半導体モデリング方法
JP2001308317A (ja) * 2000-04-18 2001-11-02 Nec Corp 半導体装置の製造方法
JP2001352059A (ja) * 2000-06-09 2001-12-21 Nec Corp Ｐｍｏｓトランジスタの特性劣化シミュレーション方法
JP2003264292A (ja) * 2002-03-11 2003-09-19 Fujitsu Display Technologies Corp シミュレーション方法

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Publication number Publication date
US20050138581A1 (en) 2005-06-23
US20070209027A1 (en) 2007-09-06
WO2004057652A1 (ja) 2004-07-08
JP2004200461A (ja) 2004-07-15
US7240308B2 (en) 2007-07-03
TW200416799A (en) 2004-09-01
TWI236040B (en) 2005-07-11
KR20050083556A (ko) 2005-08-26
CN100401461C (zh) 2008-07-09
CN1692471A (zh) 2005-11-02

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