Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
  • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Definitions

• the present invention relates to a transistor and a characteristic simulation method of a semiconductor circuit device including the transistor, and a characteristic simulator of a semiconductor circuit device that executes the method.
• the present invention relates to a MIS (Metal Insulator Semiconductor) transistor due to an NBT (Negative Bias Temperature Instability) phenomenon, a method for simulating the characteristic deterioration of a semiconductor circuit device including a MIS transistor, and a simulator for implementing the method.
• NBT Negative Bias Temperature Instability
• the drain current may decrease with time.
• Such a decrease in the drain current causes a deterioration in the characteristic that the delay time of the circuit increases with time. If the delay time increases beyond a certain level, a timing error occurs in the input / output operation of signals inside or outside the semiconductor integrated circuit, which may cause a malfunction of the entire system in which the semiconductor integrated circuit is incorporated.
• hot carrier degradation has been mainly studied for the degradation of characteristics of MOS transistors. For example, JP-A-11-135388 and JP-A-2001-352059 describe contents relating to hot carrier deterioration.
• the hot carrier deterioration phenomenon is a phenomenon in which a high electric field generates high-energy electrons and holes (hereinafter referred to as “hot carriers”) at the drain end of a MOS transistor, and the hot carriers deteriorate the characteristics of the gate oxide film. It is.
• the Lucky Electron model (hereinafter referred to as the LE model), which is still used as an existing technology for simulating hot carrier degradation, and announced at the IEEE in 1985, is expressed by the following equation 1. This is a method for calculating a characteristic degradation model that is limited to one phenomenon related to high-energy electrons (Hot Electrons) due to a high electric field.
• Hot Electrons high-energy electrons
• ⁇ P represents the amount of deterioration of transistor characteristics after the passage of time
• I ds represents the source-drain current of the transistor
• lb represents the substrate current
• w represents the channel width
• m and n are constants. It is.
• transistor degradation that can be expressed using the LE model that is, transistor degradation that can be expressed using the source-drain current I ds and the substrate current I b, has been the most important degradation phenomenon.
• NBT I Negative Bias Temperature Instability
• the NBT I degradation phenomenon means that the semiconductor substrate that constitutes the transistor When a negative voltage (negative bias voltage) is continuously applied to the gate electrode of a transistor, the characteristics of the transistor, such as its driving capability, deteriorate.
• a negative voltage negative bias voltage
• MIS type transistors such as p-type MOS transistors with a surface channel structure that uses nitride for the gate insulating film
• the characteristic deterioration due to the NBTI deterioration phenomenon is large.
• the NBT I degradation phenomenon is interpreted as a phenomenon caused by a change in the equilibrium state of the chemical reaction occurring at the interface between the silicon substrate and the silicon oxide insulating film due to the high temperature state and the application of a negative voltage.
• the deterioration of transistor characteristics generally progresses with time, and the amount of deterioration increases or decreases in a short time.
• the NBT I deterioration phenomenon there is no known change in the transistor operating temperature or the deterioration of the transistor characteristics due to the application of a negative gate voltage as a negative bias voltage.
• the NBTI deterioration phenomenon cannot be accurately grasped and the deterioration cannot be estimated accurately.
• the degradation may be underestimated, or conversely, the degradation may be overestimated. Disclosure of the invention
• An object of the present invention is to provide a method for accurately simulating the characteristic deterioration phenomenon of a circuit including a transistor by accurately predicting the fluctuation of the characteristic deterioration amount in consideration of the transistor deterioration phenomenon. .
• Another object of the present invention is to provide a semiconductor characteristic simulator that effectively performs such a simulation method.
• a semiconductor circuit device for simulating characteristics of a circuit using an arithmetic processing unit when a negative bias voltage and a bias-free voltage are applied to the semiconductor circuit device having an MIS transistor.
• the method of simulation, wherein the negative bias voltage applied to the transistor is
• XD basic deterioration amount
• Q is a constant that indicates the characteristics of the transistor.
• T O is the reference absolute operating temperature (K) of the transistor
• T is the absolute operating temperature of the transistor
• V g 0 is the reference gate voltage
• V g j is the gate voltage at j time
• the second step it is determined whether or not the transistor is deteriorated by the application of the negative bias voltage. If the transistor is deteriorated, the deterioration amount ( ⁇ ) is calculated.
• CB D is defined by the following equation, is a constant which is defined in dependence on the negative bias voltage
• t is the elapsed time after the application of the negative bias voltage.
• n ⁇ n Bv is a constant obtained from experiments
• Vg is a gate voltage as a negative bias voltage applied to the transistor.
• C D and B D are constants defined by the following formula and depending on the negative bias voltage
• t is determined by the elapsed time after the application of the negative bias voltage.
• n ⁇ and n Bv are constants obtained from experiments
• V g is a gate voltage as a negative bias voltage applied to the transistor.
• C. , BD is a constant defined by the following equation, which is defined depending on the negative bias voltage and the temperature of the transistor;
• t is the elapsed time after the application of the negative bias voltage.
• C DV and BDV are constants defined by the following equations and defined by the operating temperature of the transistor.
• n cv n Bv is a constant obtained from experiments
• V g is a gate voltage as a negative bias voltage applied to the transistor.
• T is the absolute operating temperature of the transistor
• T 0 is the reference absolute operating temperature of the transistor
• the recovery amount (AP R ) is calculated.
• the calculation of the recovery amount ( ⁇ ) is performed based on any of the following.
• C R VM, B R VM is a constant determined from the real
• n BRV M is an experimentally determined constant
• K oRVM, K BR VM is a constant determined from the experiment
• V gm is the maximum gate voltage during the negative bias voltage application period.
• n CR VM and n BKVM are constants obtained from experiments
• ORVM, and BRVM are constants obtained from experiments.
• V gm is the maximum gate voltage during the negative bias voltage application period.
• C R and B R are constants defined by the following equations.
• R- shi RVM e R B RVM e
• C RVM and B RVM are constants depending on the temperature of the transistor defined by the following equation.
• n BRV M is an experimentally determined constant
• ⁇ ⁇ BRVM is a constant obtained from experiments
• V gm is the maximum gain during the negative bias voltage application period.
• T is the voltage
• RVM c RVMT e Ho '
• T is the absolute operating temperature of the transistor
• T 0 is the reference absolute operating temperature of the transistor
• k is the Ponoletzman constant.
• the accumulated time until reaching the deterioration value is output as the transistor life.
• the method further includes a step of continuously calculating a characteristic deterioration and a characteristic recovery of each of the transistors for a plurality of continuous gate voltage states of each of the transistors and operating temperature states of the plurality of transistors.
• the method further includes the step of, when detecting that the characteristic of the transistor has recovered to a predetermined value, calculating a recovery amount by setting a new gate voltage.
• a simulation method for simulating characteristics comprising: a condition inputting step of inputting a use condition of the semiconductor circuit device; and a simulation of an operation of a transistor in the semiconductor circuit device based on the input use condition.
• a circuit simulation step before deterioration in which an effective gate voltage of the transistor is calculated, and a characteristic deterioration amount ( ⁇ ) and a recovery amount (AP R ) of the transistor are calculated, and the life of the transistor is calculated.
• simulators for performing the simulation methods of the first and second aspects.
• the semiconductor characteristics simulation method of the present invention a basic deterioration amount X D, the variation amount of degradation delta [rho.
• the Yotsute the variation of characteristics which performs variation of deterioration with basic deterioration amount X D (an increase), the simulation in consideration of the recovery (decreased deterioration with foundation deterioration amount X.) characteristics.
• the characteristic degradation amount of the transistor which depends on the time elapsed since the voltage was first applied after the transistor was formed, such as the measurement process and burn-in process, or the time elapsed since the start of use, is determined.
• FIGS. 1A and 1B are diagrams showing, as a first embodiment of the present invention, deterioration and recovery of transistor characteristics and their dependence on gate voltage.
• FIGS. 2A and 2B are diagrams showing the good voltage dependence of the transistor characteristic deterioration amount as the first embodiment of the present invention.
• FIGS. 3A and 3B are diagrams showing the dependence of the transistor characteristic recovery amount on the gate voltage according to the first embodiment of the present invention.
• FIG. 4 is a diagram illustrating a method of calculating a basic deterioration amount of a transistor characteristic in a divided time region according to a second embodiment of the present invention.
• FIG. 5 is a diagram showing a configuration of a semiconductor device characteristic simulator according to the third embodiment of the present invention.
• FIG. 6 is a diagram showing a configuration of a constant measuring device according to the third embodiment of the present invention.
• FIG. 7 is a flowchart showing the contents of arithmetic processing by the semiconductor device characteristic simulator according to the third embodiment of the present invention.
• FIG. 8 is a flowchart showing details of the process of step 2 illustrated in FIG.
• FIG. 9 is a flowchart showing details of the process of step 3 illustrated in FIG.
• FIG. 10 is a flowchart showing details of the process of step 5 illustrated in FIG. 7.
• FIG. 11 is a diagram showing a configuration of a semiconductor device characteristic simulator according to the fourth embodiment of the present invention.
• FIG. 12 is a flowchart showing the arithmetic processing content of the semiconductor device characteristic simulator according to the fourth embodiment of the present invention.
• the inventor of the present application has grasped the details of the NBTI (Negative Bias Temperature Instability) degradation phenomenon of the MIS transistor, in particular, the transistor characteristic degradation phenomenon, and the details of the transistor characteristic recovery phenomenon after the characteristic degradation by experimental data.
• NBTI Negative Bias Temperature Instability
• FIG. 1A and 1B show NBTI degradation phenomena, for example, MIS transistor It schematically shows the change over time of the transistor characteristics such as the driving capability of the transistor and the threshold voltage.As an example, the characteristics of the transistor deteriorate over time due to the gate voltage applied to the gate of the transistor An example is shown.
• FIG. 1A shows a change in the pulse waveform of the gate voltage Vg with the passage of time
• FIG. 1B shows the total deterioration amount ⁇ of an arbitrary characteristic on the vertical axis, and the time on the horizontal axis.
• Period ⁇ as shown in Figure 1 ⁇ and Figure IB.
• V g negative (L) level gate voltage V g
• V g 2 second gate voltage V g 2
• the deterioration characteristic of the transistor rises as shown by a curve D (the characteristic deteriorates. ).
• the application of the gate voltage V g 2 as a negative bias voltage applied to the transistor is released, or the first gate voltage V g1 as a bias-free voltage higher than the second gate voltage V g 2,
• V gl 0
• the deterioration characteristic of the transistor decreases as shown by the curve R (the deterioration characteristic recovers).
• the gate voltage V g at which the first gate voltage V g 1 as the bias-free voltage and the second gate voltage V g 2 at the negative level as the negative bias voltage alternately change in a pulse shape is shown in FIG.
• the progress of deterioration and the recovery of deterioration are repeated, but the total deterioration amount P increases with time.
• the curve L1 connecting the minimum value of deterioration or the maximum value of recovery (the lowest point) is a DC part of the amount of deterioration that does not take into account fluctuations in transistor characteristics, so-called deterioration and recovery of transistor characteristics. Also called.
• the amount of deterioration of this DC part is referred to as “basic deterioration amount”. Call.
• the amount of increase in deterioration with respect to the basic deterioration amount X D is referred to as “variation amount of deterioration amount” or simply “deterioration amount”, and symbol ⁇ . It is written.
• the amount of basic deterioration X is referred to as the “recovery amount” and is denoted by the symbol ⁇ ⁇ .
• CD and BD are constants.
• Degradation ⁇ Is a certain degradation period ⁇ .
• a characteristic deterioration amount or a deterioration ratio from the initial characteristics for example, a threshold value such as threshold! Vth or Swing which is a characteristic value of a transistor is used.
• There are degradation rates and degradation rates such as transconductance gm, source-drain current Ids, off-current Ioff, gate current Ig, and swing. Further, for example, there is a deterioration rate or a deterioration amount of a constant V th0, u 0, rdsw of a circuit simulator such as a SPICE simulator.
• the change over time of the degradation amount ⁇ > depends on the gate voltage V g as a negative bias voltage, that is, the application duration of the second gate voltage V g2. Therefore, the constants CD and BD are determined by the duration of application of the second gate voltage Vg2 applied to the transistor.
• a constant C that depends on the application duration of the gate voltage Vg (Vg 2) is obtained by using the following equation 3 or equation 4 obtained based on experimental data.
• C DV is a constant obtained experimentally.
• a gate voltage V g as a negative bias voltage that is, a constant ⁇ that depends on the duration of application of the second gate voltage V g 2, using Equation 5 or Equation 6. Ask for.
• Deterioration amount AP D is currently applied to the transistor, as well as the gate voltage Vg (V g 2) as a negative bias voltage, the gate voltage Vg p immediately before you apply a second gate voltage V g 2, i.e. It also depends on the bias-free voltage.
• Figures 2A and 2B show the degradation amount ⁇ . 3 shows the dependence of the gate voltage Vgp immediately before the application of the negative-level second gate voltage Vg2 to the gate of the transistor.
• FIG. 2A shows the change in the gate voltage Vg applied to the transistor
• FIG. 2B shows the total deterioration amount P of an arbitrary characteristic amount on the vertical axis and the time on the horizontal axis.
• the first gate voltage Vg1 having a higher level than the negative second gate voltage Vg2 is, for example, two kinds of gate voltages, that is, a high voltage Vg.
• g 1 a and low V gib are applied to the gate electrode of the transistor, respectively.
• the deterioration amount of the transistor in the deterioration period T2 during which the second gate voltage Vg2 is applied is determined by the fact that the first gate voltage Vg1 applied to the transistor during the recovery period T1 is higher or lower than Vg1a. It depends on V gib.
• Vg1a When a high voltage Vg1a is applied during the recovery period T1, the characteristics of the transistor deteriorate along the curve D1.
• Vg 1 b When a low voltage Vg 1 b is applied during the recovery period T 1, the characteristics of the transistor deteriorate along the curve D 2. That is, from the illustration in FIG.
• Equations 3 to 6 which represent the dependence of the currently applied gate voltage Vg (second gate voltage Vg2) on the application duration, during period T2, In the period T1, the deterioration amount ⁇ depending on the magnitude of the gate voltage V gp (first gate voltage V gl) applied to the gate of the transistor immediately before the application of the second gate voltage V g 2.
• the deterioration amount ⁇ depending on the magnitude of the gate voltage V gp (first gate voltage V gl) applied to the gate of the transistor immediately before the application of the second gate voltage V g 2.
• B DV n Bv BDVP n BvP ⁇ ⁇ ⁇ Bv ⁇ ⁇ > ⁇ are constants obtained from experimental force.
• the constant CB d applied to Equation 2 is the degradation period ⁇ . It depends on the gate voltage Vg applied to the gate electrode, ie, the second gate voltage Vg2, and the gate voltage Vgp applied during the recovery period, ie, the first gate voltage Vg1.
• the amount of degradation ⁇ > also depends on the temperature of the transistor during operation.
• Equation 11 and 12 show the relationship between the constant C DV and the absolute temperature T of the constant C DV B DV in Equation 71 (or Equation 36 ).
• C DVT Q DC B DVT Q DB is a constant obtained from experiments, etc.
• T is The absolute operating temperature of the transistor
• T0 is the reference absolute operating temperature of the transistor.
• k is Boltzmann's constant.
• Equations 11 and 12 to Equations 5 and 7 or Equations 6 and 8 yields a constant C that accounts for temperature dependence.
• BD is determined, and the constant C thus determined.
• B d is applied to Equation 2
• the deterioration amount ⁇ P in consideration of the temperature dependency can be calculated.
• an accurate degradation amount ⁇ P can be calculated.
• the inventor of the present application grasped the details of the recovery state of the characteristics after the deterioration in the ⁇ III deterioration phenomenon based on experimental measurement results based on experimental data, and found an empirical expression representing the recovery based on the experimental data.
• the empirical formula is shown as the following formula 13.
• Time course of recovery amount [Delta] [rho] kappa depends on the magnitude of the gate voltage V g. Further, the recovery amount ⁇ ⁇ ⁇ depends on the maximum gate voltage Vgm previously applied as a negative bias voltage during the deterioration period.
• Figure 3 A, Figure 3 B is that not show the dependence of the maximum gate voltage V gm recovery amount AP R.
• Figures 3A and 3B show the characteristics fc of the MIS transistor degraded by the gate voltage.
• FIG. 3A shows the gate voltage Vg
• FIG. 3B shows the total deterioration amount ⁇ of an arbitrary characteristic amount on the vertical axis and the logarithm of time on the horizontal axis.
• a maximum gate voltage V gm with a maximum amplitude at a negative level, and an absolute value (amplitude) smaller than the maximum gate voltage Vgm, and a high level gate voltage V gX are applied to the gate of the transistor, respectively.
• Figure 3 As shown in B, and the maximum gate voltage Vgm or gate voltage Vg X when mark addition to the transistor between the degradation period T D, the transistor is deteriorated, then the recovery period T each line characteristics of the transistor in the R R 3 And recover along R4. From the experimental results, the slopes of the lines R 3 and R 4 representing the change over time in the amount of recovery mainly depend on the maximum gate voltage V gm applied in the past. That is, in FIG. 3B, the gradient of R 3 and R 4 depends on the maximum gate voltage V gm and is almost the same.
• Equation 14 or Equation 1 5 obtained based on experimental data, obtaining the constant C R which depends on the maximum gate voltage Vgm.
• Equation 1 6 or Formula 1 7 determine the constants B R which depends on the maximum gate voltage V gm.
• VM ⁇ II BRVM ⁇ BRV ⁇ ⁇ BRVM is a constant obtained from an experiment.
• Recovery amount AP R is past not only the maximum gate voltage V gm was applied to the gate of the transistor, also depends on the gate voltage V g which is currently applied.
• Constant CK defining a recovery amount delta P R determined based on experimental data
• B R is the formula 1 4-1 7 representing the dependence of the maximum gate voltage V gm which was marked pressure in the past, your recovery time Equations 18 and 19 or Equations 20 and 21 include the dependence of the gate voltage V g (bias-free voltage) currently applied.
• Constant C K is beta kappa, the gate voltage V g which are currently applied in the recovery period, and, depending on the maximum gate voltage V gm was applied in the past in the deterioration period.
• Equation 13 To calculate the recovery amount ⁇ ⁇ .
• the amount of recovery ⁇ also depends on the temperature of the transistor during operation.
• CQBQ RB is a constant obtained from an experiment or the like
• T is the absolute temperature of the transistor at the time of the experiment
• T 0 is the reference temperature.
• the total deterioration amount P generated during the deterioration period T D is the basic deterioration amount X as shown in Equation 24. (T) and degradation amount ⁇ . (t). Shikabane two ⁇ ? ⁇ ))
• Equation 25 the recovery period T total deterioration amount generated in the R [rho, as shown in Equation 25, basic deterioration amount X. (T) and the amount of deterioration ⁇ during the deterioration period immediately before the application of the gate voltage to the gate of the transistor. It is the value obtained by subtracting the recovery amount AP K (t) from the sum of (t).
• the following equations 26 to 29 are expressed as the first time timel, the total accumulated time of the deterioration period in which the negative level (L) second gate voltage V g 2 (negative bias voltage) is applied, and the second time time2. It continuously calculates the total accumulated time plus the first gate voltage Vgl (bias-free voltage).
• Equations 26 and 27 are, for example, as shown in FIG. 1A, the second gate voltage Vg2 at a negative level (L) and the high level (H) higher than the second gate voltage Vg2.
• the amount of deterioration is ⁇ .
• a criterion is established to determine whether or not to calculate the amount of recovery or to calculate the amount of recovery ⁇ ⁇ .
• the simulation of the transistor characteristics approximates the actual degradation and recovery. It is possible to obtain high-speed, optimum reliability degradation margin even for the design of semiconductor circuits (for example, when the design rule is smaller than 180 nm) with more advanced transistor miniaturization. Can be given.
• the basic deterioration amount X is set.
• (T) was expressed using Equations 26 to 29, but the present inventor calculated the actual amount of basic deterioration X based on experimental data. It has been found that (t) is represented by a plurality of different functions in a plurality of time domains, instead of being represented by one function defined in one time domain as in the past.
• Figure 4 shows the amount of basic deterioration X.
• the graph shows the change over time of (t), and illustrates a comparison between the conventional calculation method and the calculation method of the present invention.
• the broken line indicates the change over time of the basic deterioration amount X according to the conventional formula, and the solid broken line indicates the change over time of the basic deterioration amount according to the embodiment of the present invention.
• Equations 30 and 31 the symbol V g0 is the reference gate voltage, Vg j is the gate voltage at a certain point j, ⁇ tj is the time when V gj is added, and time is V g0 and the reference. This is the time converted to the absolute temperature T0. 1 t is the life time.
• the symbol j is a suffix representing the time domain, stimme-k is the start time of domain j under Vg0 and T0 conditions, and etime-k is the end time of domain j under Vg0 and T0 conditions. It is.
• the deterioration amount ⁇ ⁇ is determined in advance.
• calculate the amount of recovery ⁇ calculate the elapsed time “time” using Equation 30, and substitute the result in Equation 31 to obtain the basic deterioration amount X. Get.
• the total degradation P can be obtained from Equation 24 or Equation 25.
• the degradation obtained using Equations 30 and 31 was close to the actual transistor characteristics. That is, the deterioration amount accurately indicates the actual deterioration amount. According to the embodiment of the present invention, the improvement of the conventional method that estimates the deterioration amount larger than the actual amount due to the inaccuracy of the simulation is achieved. Can be achieved.
• the transistor is applied by applying the new NBT I method.
• the new NBT I method By dealing with the degradation and recovery phenomena of the transistor, it is possible to obtain a simulation result that approximates the actual degradation and recovery of the transistor characteristics. (Less than 180 nm), it is possible to provide a high-speed, optimal reliability degradation margin.
• the second embodiment of the present invention by calculating the deterioration amount in each time region by making the deterioration formula different for each predetermined time region, the deterioration of the transistor as a whole is obtained.
• the amount can be close to the actual amount of degradation.
• the amount of deterioration could be reduced from the value of the amount of deterioration obtained by the conventional method.
• a more accurate degradation amount can be simulated by taking into account the variation in transistor degradation as a new NBTI degradation phenomenon.
• the amount of deterioration is larger than the result of the simulations so far.
• a more accurate final degradation amount can be simulated by considering a new NBTI recovery phenomenon.
• the amount of deterioration is significantly reduced as compared with the conventional method.
• the simulator according to the third embodiment of the present invention continuously performs a plurality of stress states and use states of a transistor in a semiconductor manufacturing process, a user's use, and the like with respect to one circuit including an MIS transistor and the like. Simulates the deterioration and recovery of the characteristics of the circuit including the transistor and the transistor, and evaluates the characteristic change of the circuit including the transistor and the transistor.
• deterioration or recovery of MIS transistor characteristics in the transistor characteristic measurement process of applying a voltage to the transistor in the semiconductor manufacturing process recovery of transistor characteristics during the standing period after the measurement process, and initial failure by heating the transistor Deterioration and recovery of transistor characteristics during burn-in process, which is a manufacturing process that performs screening, recovery of transistor characteristics during the standing period after burn-in process, application of voltage to transistors during user use, and heating during transistor operation Deterioration and recovery of transistor characteristics that occur at times, recovery of transistor characteristics over a period of use after user use, and some or all of transistor characteristic deterioration, and some or all of transistor characteristic recovery Is calculated continuously.
• the deterioration amount obtained by the above-described method according to the embodiment of the present invention is much smaller than the deterioration amount obtained only by considering the burn-in process as in the related art.
• FIG. 5 is a diagram showing a configuration of the semiconductor characteristic simulator 1 according to the present embodiment.
• the semiconductor characteristic simulator 1 is composed of a computer system for calculating the deterioration and recovery of transistor characteristics described in the first embodiment.
• a processor (CPU) 2 for performing calculations and control, a simulation model and a simulation model are described.
• Memory 3 that stores the data required for the simulation, input unit 4 that inputs data such as the conditions required for simulation, output unit 5 that outputs the simulation results, processor 2, memory 3, input unit 4, and output.
• a bus 6 connecting the parts 5 to each other. No.
• the semiconductor characteristic simulator 1 may have a plurality of the above configurations, and each semiconductor characteristic simulator 1 may perform the shared processing.
• the memory 3 includes constant groups 7 obtained by experiments necessary for the simulation described in the first embodiment, netlists 8 which are data on connection relationships of target circuits to be simulated, and simulations. It stores the model 9 that performs
• the input unit 4 inputs to the processor 2 a netlist 7 of a target circuit to be simulated and a reference destination of a simulation model 8 of the target circuit, for example, a reference destination of a parameter of an SPICE circuit simulator of a transistor.
• the processor 2 in order to simulate the deterioration and recovery of the characteristics of a transistor and a circuit that includes a transistor accurately, it simulates the deterioration of the characteristics of the circuit and the transistor in order to process multiple usage states of the circuit that includes the transistor continuously.
• the operating conditions of the circuit and the transistor for example, the operating temperature, the applied voltage, and the elapsed time under those conditions are input to the processor 2 from the input unit 4.
• an allowable deterioration value is input from the input unit 4 to the processor 2 as a failure determination criterion for the deteriorated circuit and each transistor.
• the processor 2 compares the deterioration amount obtained as a result of the simulation with a deterioration allowable value, and optimizes the circuit after the deterioration.
• the output unit 5 outputs the transistor life, the amount of deterioration, the total amount of deterioration, and the characteristics after deterioration obtained as a result of the simulation in the processor 2.
• the constant group 7 necessary for simulating a transistor or a circuit including a transistor by the semiconductor characteristic simulator 1 is measured by an apparatus having a configuration shown in FIG. In Figure 6, the characteristics of the transistor, for example, The characteristics of the transistor are measured by a measuring device 11 composed of a DC tester that measures the current Ids.
• the measuring device control unit 12 is, for example, a computer, calculates the constant group described in the first embodiment from the measured values of the transistor characteristics obtained by the measuring device 11, and inputs the constant group to the simulator 1. Store in memory 3. Therefore, the measuring device control unit 12 controls the measuring device 11 to measure data on the characteristics of the transistor, and automatically calculates a constant from the measurement result.
• the semiconductor characteristic simulator 1 calculates the result. To continuously simulate the degradation of transistors and circuits under multiple operating conditions.
• the measuring device 11 and the measuring device control section 12 measure, for example, constants used for simulating the characteristics of the transistor for each gate length of the transistor, and further measure various constants depending on the source-drain voltage of each transistor.
• the data is measured, and the result is output to the semiconductor characteristic simulator 1 and stored in the memory 3.
• the semiconductor device characteristic simulator 1 refers to the netlist 7 of the target circuit to be simulated and the reference to the simulation model 8, for example, the reference to the transistor SPICE circuit simulator parameters.
• the semiconductor device characteristic simulator 1 executes the simulation model 8, and starts the simulation of the characteristic of the target circuit and the characteristic deterioration of the transistor constituting the target circuit.
• FIG. 7 is a flowchart showing the calculation contents of the semiconductor device characteristic simulator 1. You.
• Step S1 Enter simulation usage conditions
• the processor 2 is connected to the processor 2 via the input unit 4 of the semiconductor characteristic simulator 1 to use the transistor circuit to be simulated under certain operating conditions, for example, the temperature such as the transistor operating temperature in the process of measuring the characteristics of the transistor circuit. Inputs various voltages such as gate voltage and gate voltage, and the elapsed time when the transistor operates under such conditions.
• Step S2 Simulation of circuit before deterioration
• the processor 2 simulates the circuit characteristics before the deterioration of the transistor according to the model 9 and stores the result in the memory 3 in order to evaluate the change in the characteristics of the transistor circuit due to the deterioration. The details of this processing will be described in detail with reference to FIG.
• Step S3 Simulation of degradation of each transistor
• the processor 2 receives an input from the input unit 4 according to the model 9 for each MIS transistor constituting the target circuit, for example, by a calculation method defined by the equations 2 to 31 described in the first embodiment. Calculate transistor degradation, recovery, total degradation, and their gate voltage and temperature dependence until the specified operating conditions and the specified elapsed time are reached.
• the processor 2 outputs the life and deterioration amount of the transistor obtained from the output unit 5. The details of this processing will be described in detail with reference to FIG.
• Step S4 Determine next use condition
• step S2 If you want to continue the simulation under different usage conditions, for example, in the standing period after the above characteristic measurement process, or after the operation in the burn-in process, under different temperature conditions and various voltage conditions such as gate applied voltage, If the operation by the user continues, the processor 2 returns to step 1, inputs the next use condition from the input unit 4, and under the condition, simulates the circuit characteristics before deterioration (step S2) according to the model 9 (step S2). Is repeated (step S 3).
• Step S5 Simulation of the deteriorated circuit
• the processor 2 simulates the circuit characteristics after the deterioration based on the total deterioration amount obtained under the plurality of use conditions described above according to the model 9. The details of this process will be described in detail with reference to FIG.
• Step S6 Output simulation results
• the processor 2 displays and compares the simulation result after the deterioration with the circuit characteristics before the deterioration stored in the memory 3 to evaluate a change in the circuit characteristics due to the deterioration.
• the processor 2 creates, for example, a deterioration amount library from the deterioration amount for each transistor under the conditions obtained by the above simulation and stores the deterioration amount library in the memory 3 according to the model 9, and stores the other transistors configured with the same transistor. It can be used for simulation of circuit characteristic deterioration.
• Processor 2 Also, based on the simulation results after deterioration, calculate the increase in circuit delay time due to characteristic deterioration according to Model 9, create a library of delay amounts for each circuit, save it in memory 3, and save the other circuits. Enable to use for characteristic deterioration simulation.
• FIG. 8 shows the contents of the simulation of the circuit characteristics before deterioration in step S2 illustrated in FIG.
• the processor 2 simulates the target circuit by using a circuit simulator such as a circuit simulator or SPICE as a part of the model 9 stored in the memory 3, and extracts circuit characteristics before deterioration.
• a circuit simulator such as a circuit simulator or SPICE as a part of the model 9 stored in the memory 3, and extracts circuit characteristics before deterioration.
• the simulation results are shown, for example, as a time course of the gate voltage and the source and drain voltages.
• Step S12 Effective gate voltage calculation
• Processor 2 uses the simulations obtained in the above manner according to Model 9. From the result, calculate the effective gate voltage for each MIS transistor, and proceed to step 3 in FIG.
• the calculation of the effective gate voltage in the processor 2 is performed using the constant group 7 calculated in the measuring device 11 and stored in the memory 3.
• FIG. 9 shows a degradation simulation method for each transistor in step S3 illustrated in FIG.
• Step S21 Calculation of degradation and recovery
• the processor 2 uses, for example, Equations 2 to 31 for each of the MIS transistors, the deterioration amount, the recovery amount, and the amount of the transistor until the use condition input from the input unit 4 and the specified elapsed time are reached. Calculate their voltage and temperature dependence.
• the processor 2 calculates the lifetime of the transistor until the instantaneous total deterioration reaches the allowable deterioration value, using the allowable deterioration value as a failure judgment reference input for each MIS transistor according to the model 9.
• the calculation of the amount of deterioration, the amount of recovery, and the calculation of the life in the processor 2 are performed using the constant group 7 measured by the measuring device 11, calculated by the measuring device control section 12 and stored in the memory 3.
• the processor 2 outputs the calculated deterioration amount and life from the output unit 5.
• Step S23 Total degradation calculation
• the processor 2 calculates the total deterioration amount for each MIS transistor from the deterioration amounts calculated in the past for all the use conditions input from the input unit 4, and proceeds to step 4 in FIG.
• the processor 2 calculates, for example, the deterioration amount ⁇ ⁇ under the current use condition. Check the maximum value of or the minimum value of the recovery amount ⁇ ⁇ ⁇ . That is, the processor 2 calculates the time time from the result calculated in consideration of all the past and current usage conditions using the equation 30 and substitutes the value obtained by substituting the equation into the equation 31 with the basic deterioration amount. X. And The total deterioration P until then can be obtained from Equation 24 or Equation 25.
• FIG. 10 shows a simulation of the circuit characteristics after deterioration in step S5 illustrated in FIG.
• Step S31 Calculate characteristics after deterioration
• the processor 2 calculates the model parameters of the MIS transistor after deterioration, for example, VthO uO, rdsw after deterioration in the SPICE, from the total deterioration amount calculated under the above conditions, and calculates the calculated result. Output from output unit 5.
• the processor 2 performs a circuit simulation such as SPICE using the calculated model parameters to calculate circuit characteristics after deterioration.
• the semiconductor characteristic simulator 1 continuously simulates the deterioration characteristics and the recovery characteristics of the transistors generated in a plurality of use states for one circuit composed of MIS transistors and the like, and the circuit characteristics Changes are evaluated.
• Non-periodic periods such as the standing period after measuring transistor characteristics in the semiconductor manufacturing process, the leaving period after the burn-in process, or the leaving period after turning off the power after using the user As there are many.
• the characteristics of the transistor and the circuit may continue to recover, and it may be possible to recover to a state close to a perfect state without deterioration.
• the simulator of the present embodiment detects that the characteristics have been sufficiently recovered, and reflects this in the calculation of the total deterioration amount. For example, the processor 2 determines that the total deterioration amount P calculated by the equations 30 and 31 has recovered to a certain value, and in that case, the parameters or parameters required for calculating the deterioration and the recovery. Set some of the parameters again. For example, at this time, the dependency of the maximum gate voltage V gm on the amount of recovery disappears, so the value of the maximum gut voltage V gm is reset when calculating the amount of recovery.
• the characteristics of the transistor and / or the circuit including the transistor are degraded and / or the amount of recovery is actually approximated. It can be quickly and optimally used for the design of even more miniaturized semiconductor circuits (for example, when the design rule is smaller than 18 O nm). Gin can be given.
• a more accurate degradation amount can be simulated by considering a plurality of use conditions such as an actual semiconductor manufacturing process and use by a user.
• the degradation amount obtained by the embodiment of the present invention by such a method is usually much smaller than the degradation amount obtained by considering only one process as in the related art.
• the measuring device 11 and the measuring device control section 12 to automate the calculation of constants necessary for the simulation and the measurement of experimental data, a large amount of data required for the simulation can be obtained. Parameters can be acquired in a short time, and the results can be input to the semiconductor characteristic simulator 1 to calculate the degradation and recovery at high speed, and new NBTI degradation phenomena and recovery phenomena can be calculated. Can be accurately grasped.
• the simulator according to the fourth embodiment of the present invention can be suitably used for characteristic degradation simulation of a large-scale integrated circuit (VLSI).
• VLSI large-scale integrated circuit
• a deterioration amount library of the transistor or the basic circuit is created from the result obtained by the deterioration simulation for the transistor or the basic circuit. Then, when performing a deterioration simulation of the target circuit, the deterioration amount of the transistor and the basic circuit including the transistor in the target circuit can be quickly obtained by using the deterioration amount library.
• FIG. 11 is a diagram showing a configuration of a semiconductor characteristic simulator 20 according to the fourth embodiment.
• the configuration of the semiconductor characteristic simulator 20 is basically the same as that of the semiconductor characteristic simulator 1 of the third embodiment illustrated in FIG. 5, except that data required for calculation stored in a memory is different. Also, the operation procedure of the entire simulator is different from that of the semiconductor characteristic simulator 1 illustrated in FIG.
• the semiconductor characteristic simulator 20 includes, for example, a processor (CPU) 2, a memory 3 for storing simulation models and data necessary for simulation, an input unit 4 for inputting data such as conditions necessary for simulation, and a simulation unit. An output section 5 for outputting a result of one section, and a bus 6 for interconnecting the processor 2, the memory 3, the input section 4, and the output section 5 are included.
• a processor CPU
• memory 3 for storing simulation models and data necessary for simulation
• an input unit 4 for inputting data such as conditions necessary for simulation
• a simulation unit for inputting data such as conditions necessary for simulation
• An output section 5 for outputting a result of one section
• a bus 6 for interconnecting the processor 2, the memory 3, the input section 4, and the output section 5 are included.
• the semiconductor characteristic simulator 1 illustrated in FIG. 5 may have a plurality of the above configurations.
• the memory 3 contains in addition to the constant group 7 obtained in the experiment necessary for the simulation, the netlist 8 that is the connection relation data of the target circuit to be simulated, and the model 9 for performing the simulation.
• Deterioration amount library 21 which is the deterioration amount data created from the simulation results of the transistors
• basic circuit library 22 which is the data of the basic circuit that constitutes the target circuit to be a large-scale integrated circuit to be simulated
• target Circuit diagram showing the circuit configuration of the circuit Data 2 and 3 are stored.
• the use conditions of the circuit to be simulated such as the operating temperature or heating temperature of the transistor in the characteristic test process of the semiconductor circuit device, various voltages such as the gate voltage, and such conditions.
• the elapsed time at is input.
• the allowable deterioration value is input from the input unit 4 to the processor 2 as a failure determination criterion.
• the output unit 5 outputs the fault location and post-deterioration characteristics found as a result of the simulation in the processor 2.
• measuring means for measuring the experimental data and calculating the constants are provided. Connected to 0.
• the deterioration amount library 21 is configured in advance, or the deterioration amount is prepared in advance for each basic circuit group.
• the deterioration amount library 21 may be created from a result of a simulation of deterioration of a transistor and another circuit performed in advance, or all of the transistors are most severe.
• a library can be created by calculating the amount of deterioration on the assumption that deterioration will occur. This can be easily calculated using, for example, Equations 30 and 31.
• the library in the simulator 20 is composed of a deterioration amount library 21 and a basic circuit library 22 consisting of data of a basic circuit group, and a circuit is constructed by using the deterioration amount library 21 and the basic circuit library 22.
• the degradation of characteristics is calculated quickly and accurately.
• FIG. 12 is a flowchart showing the arithmetic processing contents of the semiconductor device characteristic simulator 20.
• the overall processing operation of the semiconductor characteristic simulator 20 is as follows: first, the reference destination of the simulation model 8 of the target circuit to be simulated; For example, enter the reference of parameters for transistor SPICE circuit simulation. Next, the simulation model 8 is executed to start a simulation on the characteristics of the target circuit and the deterioration and recovery of the characteristics of the transistors constituting the target circuit.
• Step S41 Initial circuit simulation
• the processor 2 performs an initial circuit simulation using the model 9 before performing a precise circuit simulation in step S44.
• the processor 2 uses the deterioration amount library 21 and the basic circuit library 22 to determine a target circuit having a circuit diagram 23 formed from a basic circuit group included in the basic circuit library 22. Calculate the deterioration amount of the basic circuit at high speed.
• Step S42 Extract circuits with large deterioration
• the processor 2 extracts, as the deterioration amount, only a circuit indicating the deterioration amount of the inputted failure determination criterion that is so large that it cannot be ignored. Processor 2 also extracts the operation waveform and operation pattern of the target circuit at the same time.
• Step S43 Netlist synthesis
• the processor 2 synthesizes, for example, a netlist 8 that enables a SPICE simulation, based on the extracted circuit, operation waveform, and basic circuit library 22.
• -Step S44 Precise simulation
• the processor 2 uses the netlist 8 stored in the memory 3 to perform more accurate (precise) circuit simulation, for example, as described in the second embodiment.
• Step S45 Failure judgment
• the processor 2 determines a failure of the circuit using the input failure determination criterion based on the result of the precise circuit simulation in step S44.
• Step S46 Output simulation results
• the processor 2 outputs, from the output unit 5, a result of the simulation result determination, for example, a failure location, a deteriorated circuit delay value, and the like based on the failure determination result.
• the degradation amount and the recovery amount can be simulated quickly and accurately as in the third embodiment.
• the amount and the recovery amount can be obtained, and the reliability degradation margin can be quickly and optimally given to the design of a further miniaturized semiconductor circuit.
• the fourth embodiment unlike the conventional formula for calculating the amount of deterioration, by calculating the appropriate amount of deterioration and the amount of recovery for each time region by dividing the time region, the actual deterioration of the transistor circuit is obtained. Results close to volume and recovery can be obtained. In many cases, the deterioration amount obtained in the present embodiment is smaller than the deterioration amount obtained by the conventional method.
• a more accurate deterioration amount can be simulated by considering the change in the characteristic deterioration. In this way, the deterioration amount obtained in the present embodiment increases in many cases.
• the final deterioration amount can be simulated more accurately by considering the recovery of the characteristics of the transistor. In this way, the deterioration amount obtained in the present embodiment is largely reduced in many cases.
• the present embodiment by considering a plurality of use conditions from the manufacture of a semiconductor device to the use of a user, it is possible to more accurately simulate the amount of deterioration and the amount of recovery, and consider only one process.
• the deterioration amount can be greatly reduced from the obtained deterioration amount.
• the size of the MIS transistor can be reduced if the degradation amount obtained in the present embodiment is smaller than the degradation amount obtained in the conventional technology.
• the area occupied by wafers for products can be reduced, and as a result, the number of products that can be manufactured per wafer can be increased, and manufacturing costs can be reduced.
• the deterioration amount obtained in the present embodiment is larger than the deterioration amount obtained by the conventional method, measures are taken in advance in consideration of reliability so that the product can be used normally up to the specified life. Circuit can be designed.

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• 2002
  • 2002-12-19 JP JP2002368046A patent/JP4214775B2/ja not_active Expired - Fee Related
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